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patch apic-simplify
patch remove-apic_cr8pri
patch spacing-fix
patch apic-task-reg-write-dup
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--- old/usr/src/uts/i86pc/io/pcplusmp/apic.c
+++ new/usr/src/uts/i86pc/io/pcplusmp/apic.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
31 31 */
32 32
33 33 /*
34 34 * To understand how the pcplusmp module interacts with the interrupt subsystem
35 35 * read the theory statement in uts/i86pc/os/intr.c.
36 36 */
37 37
38 38 /*
39 39 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
40 40 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
41 41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
42 42 * PSMI 1.5 extensions are supported in Solaris Nevada.
43 43 * PSMI 1.6 extensions are supported in Solaris Nevada.
44 44 * PSMI 1.7 extensions are supported in Solaris Nevada.
45 45 */
46 46 #define PSMI_1_7
47 47
48 48 #include <sys/processor.h>
49 49 #include <sys/time.h>
50 50 #include <sys/psm.h>
51 51 #include <sys/smp_impldefs.h>
52 52 #include <sys/cram.h>
53 53 #include <sys/acpi/acpi.h>
54 54 #include <sys/acpica.h>
55 55 #include <sys/psm_common.h>
56 56 #include <sys/apic.h>
57 57 #include <sys/pit.h>
58 58 #include <sys/ddi.h>
59 59 #include <sys/sunddi.h>
60 60 #include <sys/ddi_impldefs.h>
61 61 #include <sys/pci.h>
62 62 #include <sys/promif.h>
63 63 #include <sys/x86_archext.h>
64 64 #include <sys/cpc_impl.h>
65 65 #include <sys/uadmin.h>
66 66 #include <sys/panic.h>
67 67 #include <sys/debug.h>
68 68 #include <sys/archsystm.h>
69 69 #include <sys/trap.h>
70 70 #include <sys/machsystm.h>
71 71 #include <sys/sysmacros.h>
72 72 #include <sys/cpuvar.h>
73 73 #include <sys/rm_platter.h>
74 74 #include <sys/privregs.h>
75 75 #include <sys/note.h>
76 76 #include <sys/pci_intr_lib.h>
77 77 #include <sys/spl.h>
78 78 #include <sys/clock.h>
79 79 #include <sys/cyclic.h>
80 80 #include <sys/dditypes.h>
81 81 #include <sys/sunddi.h>
82 82 #include <sys/x_call.h>
83 83 #include <sys/reboot.h>
84 84 #include <sys/hpet.h>
85 85 #include <sys/apic_common.h>
86 86 #include <sys/apic_timer.h>
87 87
88 88 /*
89 89 * Local Function Prototypes
90 90 */
91 91 static void apic_init_intr(void);
92 92
93 93 /*
94 94 * standard MP entries
95 95 */
96 96 static int apic_probe(void);
97 97 static int apic_getclkirq(int ipl);
98 98 static void apic_init(void);
99 99 static void apic_picinit(void);
100 100 static int apic_post_cpu_start(void);
101 101 static int apic_intr_enter(int ipl, int *vect);
102 102 static void apic_setspl(int ipl);
103 103 static void x2apic_setspl(int ipl);
104 104 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
105 105 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
106 106 static int apic_disable_intr(processorid_t cpun);
107 107 static void apic_enable_intr(processorid_t cpun);
108 108 static int apic_get_ipivect(int ipl, int type);
109 109 static void apic_post_cyclic_setup(void *arg);
110 110
111 111 /*
112 112 * The following vector assignments influence the value of ipltopri and
113 113 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
114 114 * idle to 0 and IPL 0 to 0xf to differentiate idle in case
115 115 * we care to do so in future. Note some IPLs which are rarely used
116 116 * will share the vector ranges and heavily used IPLs (5 and 6) have
117 117 * a wide range.
118 118 *
119 119 * This array is used to initialize apic_ipls[] (in apic_init()).
120 120 *
121 121 * IPL Vector range. as passed to intr_enter
122 122 * 0 none.
123 123 * 1,2,3 0x20-0x2f 0x0-0xf
124 124 * 4 0x30-0x3f 0x10-0x1f
125 125 * 5 0x40-0x5f 0x20-0x3f
126 126 * 6 0x60-0x7f 0x40-0x5f
127 127 * 7,8,9 0x80-0x8f 0x60-0x6f
128 128 * 10 0x90-0x9f 0x70-0x7f
129 129 * 11 0xa0-0xaf 0x80-0x8f
130 130 * ... ...
131 131 * 15 0xe0-0xef 0xc0-0xcf
132 132 * 15 0xf0-0xff 0xd0-0xdf
133 133 */
134 134 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
135 135 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
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136 136 };
137 137 /*
138 138 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
139 139 * NOTE that this is vector as passed into intr_enter which is
140 140 * programmed vector - 0x20 (APIC_BASE_VECT)
141 141 */
142 142
143 143 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
144 144 /* The taskpri to be programmed into apic to mask given ipl */
145 145
146 -#if defined(__amd64)
147 -uchar_t apic_cr8pri[MAXIPL + 1]; /* unix ipl to cr8 pri */
148 -#endif
149 -
150 146 /*
151 147 * Correlation of the hardware vector to the IPL in use, initialized
152 148 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
153 149 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
154 150 * connected to errata-stricken IOAPICs
155 151 */
156 152 uchar_t apic_ipls[APIC_AVAIL_VECTOR];
157 153
158 154 /*
159 155 * Patchable global variables.
160 156 */
161 157 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
162 158 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
163 159
164 160 /*
165 161 * Local static data
166 162 */
167 163 static struct psm_ops apic_ops = {
168 164 apic_probe,
169 165
170 166 apic_init,
171 167 apic_picinit,
172 168 apic_intr_enter,
173 169 apic_intr_exit,
174 170 apic_setspl,
175 171 apic_addspl,
176 172 apic_delspl,
177 173 apic_disable_intr,
178 174 apic_enable_intr,
179 175 (int (*)(int))NULL, /* psm_softlvl_to_irq */
180 176 (void (*)(int))NULL, /* psm_set_softintr */
181 177
182 178 apic_set_idlecpu,
183 179 apic_unset_idlecpu,
184 180
185 181 apic_clkinit,
186 182 apic_getclkirq,
187 183 (void (*)(void))NULL, /* psm_hrtimeinit */
188 184 apic_gethrtime,
189 185
190 186 apic_get_next_processorid,
191 187 apic_cpu_start,
192 188 apic_post_cpu_start,
193 189 apic_shutdown,
194 190 apic_get_ipivect,
195 191 apic_send_ipi,
196 192
197 193 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
198 194 (void (*)(int, char *))NULL, /* psm_notify_error */
199 195 (void (*)(int))NULL, /* psm_notify_func */
200 196 apic_timer_reprogram,
201 197 apic_timer_enable,
202 198 apic_timer_disable,
203 199 apic_post_cyclic_setup,
204 200 apic_preshutdown,
205 201 apic_intr_ops, /* Advanced DDI Interrupt framework */
206 202 apic_state, /* save, restore apic state for S3 */
207 203 apic_cpu_ops, /* CPU control interface. */
208 204 };
209 205
210 206 struct psm_ops *psmops = &apic_ops;
211 207
212 208 static struct psm_info apic_psm_info = {
213 209 PSM_INFO_VER01_7, /* version */
214 210 PSM_OWN_EXCLUSIVE, /* ownership */
215 211 (struct psm_ops *)&apic_ops, /* operation */
216 212 APIC_PCPLUSMP_NAME, /* machine name */
217 213 "pcplusmp v1.4 compatible",
218 214 };
219 215
220 216 static void *apic_hdlp;
221 217
222 218 /*
223 219 * apic_let_idle_redistribute can have the following values:
224 220 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute.
225 221 * apic_redistribute_lock prevents multiple idle cpus from redistributing
226 222 */
227 223 int apic_num_idle_redistributions = 0;
228 224 static int apic_let_idle_redistribute = 0;
229 225
230 226 /* to gather intr data and redistribute */
231 227 static void apic_redistribute_compute(void);
232 228
233 229 /*
234 230 * This is the loadable module wrapper
235 231 */
236 232
237 233 int
238 234 _init(void)
239 235 {
240 236 if (apic_coarse_hrtime)
241 237 apic_ops.psm_gethrtime = &apic_gettime;
242 238 return (psm_mod_init(&apic_hdlp, &apic_psm_info));
243 239 }
244 240
245 241 int
246 242 _fini(void)
247 243 {
248 244 return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
249 245 }
250 246
251 247 int
252 248 _info(struct modinfo *modinfop)
253 249 {
254 250 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
255 251 }
256 252
257 253 static int
258 254 apic_probe(void)
259 255 {
260 256 /* check if apix is initialized */
261 257 if (apix_enable && apix_loaded())
262 258 return (PSM_FAILURE);
263 259 else
264 260 apix_enable = 0; /* continue using pcplusmp PSM */
265 261
266 262 return (apic_probe_common(apic_psm_info.p_mach_idstring));
267 263 }
268 264
269 265 static uchar_t
270 266 apic_xlate_vector_by_irq(uchar_t irq)
271 267 {
272 268 if (apic_irq_table[irq] == NULL)
273 269 return (0);
274 270
275 271 return (apic_irq_table[irq]->airq_vector);
276 272 }
277 273
278 274 void
279 275 apic_init(void)
280 276 {
281 277 int i;
282 278 int j = 1;
283 279
284 280 psm_get_ioapicid = apic_get_ioapicid;
285 281 psm_get_localapicid = apic_get_localapicid;
286 282 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
287 283
288 284 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
289 285 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
290 286 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
291 287 (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
292 288 /* get to highest vector at the same ipl */
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293 289 continue;
294 290 for (; j <= apic_vectortoipl[i]; j++) {
295 291 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
296 292 APIC_BASE_VECT;
297 293 }
298 294 }
299 295 for (; j < MAXIPL + 1; j++)
300 296 /* fill up any empty ipltopri slots */
301 297 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
302 298 apic_init_common();
303 -#if defined(__amd64)
304 - /*
305 - * Make cpu-specific interrupt info point to cr8pri vector
306 - */
307 - for (i = 0; i <= MAXIPL; i++)
308 - apic_cr8pri[i] = apic_ipltopri[i] >> APIC_IPL_SHIFT;
309 - CPU->cpu_pri_data = apic_cr8pri;
310 -#else
299 +#ifndef __amd64
311 300 if (cpuid_have_cr8access(CPU))
312 301 apic_have_32bit_cr8 = 1;
313 -#endif /* __amd64 */
302 +#endif /* !__amd64 */
314 303 }
315 304
316 305 static void
317 306 apic_init_intr(void)
318 307 {
319 308 processorid_t cpun = psm_get_cpu_id();
320 309 uint_t nlvt;
321 310 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
322 311
323 312 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
324 313
325 314 if (apic_mode == LOCAL_APIC) {
326 315 /*
327 316 * We are running APIC in MMIO mode.
328 317 */
329 318 if (apic_flat_model) {
330 319 apic_reg_ops->apic_write(APIC_FORMAT_REG,
331 320 APIC_FLAT_MODEL);
332 321 } else {
333 322 apic_reg_ops->apic_write(APIC_FORMAT_REG,
334 323 APIC_CLUSTER_MODEL);
335 324 }
336 325
337 326 apic_reg_ops->apic_write(APIC_DEST_REG,
338 327 AV_HIGH_ORDER >> cpun);
339 328 }
340 329
341 330 if (apic_directed_EOI_supported()) {
342 331 /*
343 332 * Setting the 12th bit in the Spurious Interrupt Vector
344 333 * Register suppresses broadcast EOIs generated by the local
345 334 * APIC. The suppression of broadcast EOIs happens only when
346 335 * interrupts are level-triggered.
347 336 */
348 337 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
349 338 }
350 339
351 340 /* need to enable APIC before unmasking NMI */
352 341 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
353 342
354 343 /*
355 344 * Presence of an invalid vector with delivery mode AV_FIXED can
356 345 * cause an error interrupt, even if the entry is masked...so
357 346 * write a valid vector to LVT entries along with the mask bit
358 347 */
359 348
360 349 /* All APICs have timer and LINT0/1 */
361 350 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
362 351 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
363 352 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
364 353
365 354 /*
366 355 * On integrated APICs, the number of LVT entries is
367 356 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
368 357 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
369 358 */
370 359
371 360 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
372 361 nlvt = 3;
373 362 } else {
374 363 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
375 364 0xFF) + 1;
376 365 }
377 366
378 367 if (nlvt >= 5) {
379 368 /* Enable performance counter overflow interrupt */
380 369
381 370 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
382 371 apic_enable_cpcovf_intr = 0;
383 372 if (apic_enable_cpcovf_intr) {
384 373 if (apic_cpcovf_vect == 0) {
385 374 int ipl = APIC_PCINT_IPL;
386 375 int irq = apic_get_ipivect(ipl, -1);
387 376
388 377 ASSERT(irq != -1);
389 378 apic_cpcovf_vect =
390 379 apic_irq_table[irq]->airq_vector;
391 380 ASSERT(apic_cpcovf_vect);
392 381 (void) add_avintr(NULL, ipl,
393 382 (avfunc)kcpc_hw_overflow_intr,
394 383 "apic pcint", irq, NULL, NULL, NULL, NULL);
395 384 kcpc_hw_overflow_intr_installed = 1;
396 385 kcpc_hw_enable_cpc_intr =
397 386 apic_cpcovf_mask_clear;
398 387 }
399 388 apic_reg_ops->apic_write(APIC_PCINT_VECT,
400 389 apic_cpcovf_vect);
401 390 }
402 391 }
403 392
404 393 if (nlvt >= 6) {
405 394 /* Only mask TM intr if the BIOS apparently doesn't use it */
406 395
407 396 uint32_t lvtval;
408 397
409 398 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
410 399 if (((lvtval & AV_MASK) == AV_MASK) ||
411 400 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
412 401 apic_reg_ops->apic_write(APIC_THERM_VECT,
413 402 AV_MASK|APIC_RESV_IRQ);
414 403 }
415 404 }
416 405
417 406 /* Enable error interrupt */
418 407
419 408 if (nlvt >= 4 && apic_enable_error_intr) {
420 409 if (apic_errvect == 0) {
421 410 int ipl = 0xf; /* get highest priority intr */
422 411 int irq = apic_get_ipivect(ipl, -1);
423 412
424 413 ASSERT(irq != -1);
425 414 apic_errvect = apic_irq_table[irq]->airq_vector;
426 415 ASSERT(apic_errvect);
427 416 /*
428 417 * Not PSMI compliant, but we are going to merge
429 418 * with ON anyway
430 419 */
431 420 (void) add_avintr((void *)NULL, ipl,
432 421 (avfunc)apic_error_intr, "apic error intr",
433 422 irq, NULL, NULL, NULL, NULL);
434 423 }
435 424 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
436 425 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
437 426 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
438 427 }
439 428
440 429 /* Enable CMCI interrupt */
441 430 if (cmi_enable_cmci) {
442 431
443 432 mutex_enter(&cmci_cpu_setup_lock);
444 433 if (cmci_cpu_setup_registered == 0) {
445 434 mutex_enter(&cpu_lock);
446 435 register_cpu_setup_func(cmci_cpu_setup, NULL);
447 436 mutex_exit(&cpu_lock);
448 437 cmci_cpu_setup_registered = 1;
449 438 }
450 439 mutex_exit(&cmci_cpu_setup_lock);
451 440
452 441 if (apic_cmci_vect == 0) {
453 442 int ipl = 0x2;
454 443 int irq = apic_get_ipivect(ipl, -1);
455 444
456 445 ASSERT(irq != -1);
457 446 apic_cmci_vect = apic_irq_table[irq]->airq_vector;
458 447 ASSERT(apic_cmci_vect);
459 448
460 449 (void) add_avintr(NULL, ipl,
461 450 (avfunc)cmi_cmci_trap,
462 451 "apic cmci intr", irq, NULL, NULL, NULL, NULL);
463 452 }
464 453 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect);
465 454 }
466 455 }
467 456
468 457 static void
469 458 apic_picinit(void)
470 459 {
471 460 int i, j;
472 461 uint_t isr;
473 462
474 463 /*
475 464 * Initialize and enable interrupt remapping before apic
476 465 * hardware initialization
477 466 */
478 467 apic_intrmap_init(apic_mode);
479 468
480 469 /*
481 470 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
482 471 * bit on without clearing it with EOI. Since softint
483 472 * uses vector 0x20 to interrupt itself, so softint will
484 473 * not work on this machine. In order to fix this problem
485 474 * a check is made to verify all the isr bits are clear.
486 475 * If not, EOIs are issued to clear the bits.
487 476 */
488 477 for (i = 7; i >= 1; i--) {
489 478 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
490 479 if (isr != 0)
491 480 for (j = 0; ((j < 32) && (isr != 0)); j++)
492 481 if (isr & (1 << j)) {
493 482 apic_reg_ops->apic_write(
494 483 APIC_EOI_REG, 0);
495 484 isr &= ~(1 << j);
496 485 apic_error |= APIC_ERR_BOOT_EOI;
497 486 }
498 487 }
499 488
500 489 /* set a flag so we know we have run apic_picinit() */
501 490 apic_picinit_called = 1;
502 491 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
503 492 LOCK_INIT_CLEAR(&apic_ioapic_lock);
504 493 LOCK_INIT_CLEAR(&apic_error_lock);
505 494 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
506 495
507 496 picsetup(); /* initialise the 8259 */
508 497
509 498 /* add nmi handler - least priority nmi handler */
510 499 LOCK_INIT_CLEAR(&apic_nmi_lock);
511 500
512 501 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
513 502 "pcplusmp NMI handler", (caddr_t)NULL))
514 503 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
515 504
516 505 /*
517 506 * Check for directed-EOI capability in the local APIC.
518 507 */
519 508 if (apic_directed_EOI_supported() == 1) {
520 509 apic_set_directed_EOI_handler();
521 510 }
522 511
523 512 apic_init_intr();
524 513
525 514 /* enable apic mode if imcr present */
526 515 if (apic_imcrp) {
527 516 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
528 517 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
529 518 }
530 519
531 520 ioapic_init_intr(IOAPIC_MASK);
532 521 }
533 522
534 523 #ifdef DEBUG
535 524 void
536 525 apic_break(void)
537 526 {
538 527 }
539 528 #endif /* DEBUG */
540 529
541 530 /*
542 531 * platform_intr_enter
543 532 *
544 533 * Called at the beginning of the interrupt service routine to
545 534 * mask all level equal to and below the interrupt priority
546 535 * of the interrupting vector. An EOI should be given to
547 536 * the interrupt controller to enable other HW interrupts.
548 537 *
549 538 * Return -1 for spurious interrupts
550 539 *
551 540 */
552 541 /*ARGSUSED*/
553 542 static int
554 543 apic_intr_enter(int ipl, int *vectorp)
555 544 {
556 545 uchar_t vector;
557 546 int nipl;
558 547 int irq;
559 548 ulong_t iflag;
560 549 apic_cpus_info_t *cpu_infop;
561 550
562 551 /*
563 552 * The real vector delivered is (*vectorp + 0x20), but our caller
564 553 * subtracts 0x20 from the vector before passing it to us.
565 554 * (That's why APIC_BASE_VECT is 0x20.)
566 555 */
567 556 vector = (uchar_t)*vectorp;
568 557
569 558 /* if interrupted by the clock, increment apic_nsec_since_boot */
570 559 if (vector == apic_clkvect) {
571 560 if (!apic_oneshot) {
572 561 /* NOTE: this is not MT aware */
573 562 apic_hrtime_stamp++;
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574 563 apic_nsec_since_boot += apic_nsec_per_intr;
575 564 apic_hrtime_stamp++;
576 565 last_count_read = apic_hertz_count;
577 566 apic_redistribute_compute();
578 567 }
579 568
580 569 /* We will avoid all the book keeping overhead for clock */
581 570 nipl = apic_ipls[vector];
582 571
583 572 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
584 - if (apic_mode == LOCAL_APIC) {
585 -#if defined(__amd64)
586 - setcr8((ulong_t)(apic_ipltopri[nipl] >>
587 - APIC_IPL_SHIFT));
588 -#else
589 - if (apic_have_32bit_cr8)
590 - setcr8((ulong_t)(apic_ipltopri[nipl] >>
591 - APIC_IPL_SHIFT));
592 - else
593 - LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
594 - (uint32_t)apic_ipltopri[nipl]);
595 -#endif
596 - LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
597 - } else {
598 - X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
599 - X2APIC_WRITE(APIC_EOI_REG, 0);
600 - }
573 +
574 + apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
575 + apic_reg_ops->apic_send_eoi(0);
601 576
602 577 return (nipl);
603 578 }
604 579
605 580 cpu_infop = &apic_cpus[psm_get_cpu_id()];
606 581
607 582 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
608 583 cpu_infop->aci_spur_cnt++;
609 584 return (APIC_INT_SPURIOUS);
610 585 }
611 586
612 587 /* Check if the vector we got is really what we need */
613 588 if (apic_revector_pending) {
614 589 /*
615 590 * Disable interrupts for the duration of
616 591 * the vector translation to prevent a self-race for
617 592 * the apic_revector_lock. This cannot be done
618 593 * in apic_xlate_vector because it is recursive and
619 594 * we want the vector translation to be atomic with
620 595 * respect to other (higher-priority) interrupts.
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621 596 */
622 597 iflag = intr_clear();
623 598 vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
624 599 APIC_BASE_VECT;
625 600 intr_restore(iflag);
626 601 }
627 602
628 603 nipl = apic_ipls[vector];
629 604 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
630 605
631 - if (apic_mode == LOCAL_APIC) {
632 -#if defined(__amd64)
633 - setcr8((ulong_t)(apic_ipltopri[nipl] >> APIC_IPL_SHIFT));
634 -#else
635 - if (apic_have_32bit_cr8)
636 - setcr8((ulong_t)(apic_ipltopri[nipl] >>
637 - APIC_IPL_SHIFT));
638 - else
639 - LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
640 - (uint32_t)apic_ipltopri[nipl]);
641 -#endif
642 - } else {
643 - X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
644 - }
606 + apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
645 607
646 608 cpu_infop->aci_current[nipl] = (uchar_t)irq;
647 609 cpu_infop->aci_curipl = (uchar_t)nipl;
648 610 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
649 611
650 612 /*
651 613 * apic_level_intr could have been assimilated into the irq struct.
652 614 * but, having it as a character array is more efficient in terms of
653 615 * cache usage. So, we leave it as is.
654 616 */
655 617 if (!apic_level_intr[irq]) {
656 - if (apic_mode == LOCAL_APIC) {
657 - LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
658 - } else {
659 - X2APIC_WRITE(APIC_EOI_REG, 0);
660 - }
618 + apic_reg_ops->apic_send_eoi(0);
661 619 }
662 620
663 621 #ifdef DEBUG
664 622 APIC_DEBUG_BUF_PUT(vector);
665 623 APIC_DEBUG_BUF_PUT(irq);
666 624 APIC_DEBUG_BUF_PUT(nipl);
667 625 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
668 626 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
669 627 drv_usecwait(apic_stretch_interrupts);
670 628
671 629 if (apic_break_on_cpu == psm_get_cpu_id())
672 630 apic_break();
673 631 #endif /* DEBUG */
674 632 return (nipl);
675 633 }
676 634
677 635 /*
678 636 * This macro is a common code used by MMIO local apic and X2APIC
679 637 * local apic.
680 638 */
681 639 #define APIC_INTR_EXIT() \
682 640 { \
683 641 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \
684 642 if (apic_level_intr[irq]) \
685 643 apic_reg_ops->apic_send_eoi(irq); \
686 644 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \
687 645 /* ISR above current pri could not be in progress */ \
688 646 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \
689 647 }
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690 648
691 649 /*
692 650 * Any changes made to this function must also change X2APIC
693 651 * version of intr_exit.
694 652 */
695 653 void
696 654 apic_intr_exit(int prev_ipl, int irq)
697 655 {
698 656 apic_cpus_info_t *cpu_infop;
699 657
700 -#if defined(__amd64)
701 - setcr8((ulong_t)apic_cr8pri[prev_ipl]);
702 -#else
703 - if (apic_have_32bit_cr8)
704 - setcr8((ulong_t)(apic_ipltopri[prev_ipl] >> APIC_IPL_SHIFT));
705 - else
706 - apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl];
707 -#endif
658 + local_apic_write_task_reg(apic_ipltopri[prev_ipl]);
708 659
709 660 APIC_INTR_EXIT();
710 661 }
711 662
712 663 /*
713 664 * Same as apic_intr_exit() except it uses MSR rather than MMIO
714 665 * to access local apic registers.
715 666 */
716 667 void
717 668 x2apic_intr_exit(int prev_ipl, int irq)
718 669 {
719 670 apic_cpus_info_t *cpu_infop;
720 671
721 672 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]);
722 673 APIC_INTR_EXIT();
723 674 }
724 675
725 676 intr_exit_fn_t
726 677 psm_intr_exit_fn(void)
727 678 {
728 679 if (apic_mode == LOCAL_X2APIC)
729 680 return (x2apic_intr_exit);
730 681
731 682 return (apic_intr_exit);
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732 683 }
733 684
734 685 /*
735 686 * Mask all interrupts below or equal to the given IPL.
736 687 * Any changes made to this function must also change X2APIC
737 688 * version of setspl.
738 689 */
739 690 static void
740 691 apic_setspl(int ipl)
741 692 {
742 -#if defined(__amd64)
743 - setcr8((ulong_t)apic_cr8pri[ipl]);
744 -#else
745 - if (apic_have_32bit_cr8)
746 - setcr8((ulong_t)(apic_ipltopri[ipl] >> APIC_IPL_SHIFT));
747 - else
748 - apicadr[APIC_TASK_REG] = apic_ipltopri[ipl];
749 -#endif
693 + local_apic_write_task_reg(apic_ipltopri[ipl]);
750 694
751 695 /* interrupts at ipl above this cannot be in progress */
752 696 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
753 697 /*
754 698 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
755 699 * have enough time to come in before the priority is raised again
756 700 * during the idle() loop.
757 701 */
758 702 if (apic_setspl_delay)
759 703 (void) apic_reg_ops->apic_get_pri();
760 704 }
761 705
762 706 /*
763 707 * X2APIC version of setspl.
764 708 * Mask all interrupts below or equal to the given IPL
765 709 */
766 710 static void
767 711 x2apic_setspl(int ipl)
768 712 {
769 713 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]);
770 714
771 715 /* interrupts at ipl above this cannot be in progress */
772 716 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
773 717 }
774 718
775 719 /*ARGSUSED*/
776 720 static int
777 721 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
778 722 {
779 723 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
780 724 }
781 725
782 726 static int
783 727 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
784 728 {
785 729 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
786 730 }
787 731
788 732 static int
789 733 apic_post_cpu_start(void)
790 734 {
791 735 int cpun;
792 736 static int cpus_started = 1;
793 737
794 738 /* We know this CPU + BSP started successfully. */
795 739 cpus_started++;
796 740
797 741 /*
798 742 * On BSP we would have enabled X2APIC, if supported by processor,
799 743 * in acpi_probe(), but on AP we do it here.
800 744 *
801 745 * We enable X2APIC mode only if BSP is running in X2APIC & the
802 746 * local APIC mode of the current CPU is MMIO (xAPIC).
803 747 */
804 748 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
805 749 apic_local_mode() == LOCAL_APIC) {
806 750 apic_enable_x2apic();
807 751 }
808 752
809 753 /*
810 754 * Switch back to x2apic IPI sending method for performance when target
811 755 * CPU has entered x2apic mode.
812 756 */
813 757 if (apic_mode == LOCAL_X2APIC) {
814 758 apic_switch_ipi_callback(B_FALSE);
815 759 }
816 760
817 761 splx(ipltospl(LOCK_LEVEL));
818 762 apic_init_intr();
819 763
820 764 /*
821 765 * since some systems don't enable the internal cache on the non-boot
822 766 * cpus, so we have to enable them here
823 767 */
824 768 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
825 769
826 770 #ifdef DEBUG
827 771 APIC_AV_PENDING_SET();
828 772 #else
829 773 if (apic_mode == LOCAL_APIC)
830 774 APIC_AV_PENDING_SET();
831 775 #endif /* DEBUG */
832 776
833 777 /*
834 778 * We may be booting, or resuming from suspend; aci_status will
835 779 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
836 780 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
837 781 */
838 782 cpun = psm_get_cpu_id();
839 783 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
840 784
841 785 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
842 786 return (PSM_SUCCESS);
843 787 }
844 788
845 789 /*
846 790 * type == -1 indicates it is an internal request. Do not change
847 791 * resv_vector for these requests
848 792 */
849 793 static int
850 794 apic_get_ipivect(int ipl, int type)
851 795 {
852 796 uchar_t vector;
853 797 int irq;
854 798
855 799 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
856 800 if (vector = apic_allocate_vector(ipl, irq, 1)) {
857 801 apic_irq_table[irq]->airq_mps_intr_index =
858 802 RESERVE_INDEX;
859 803 apic_irq_table[irq]->airq_vector = vector;
860 804 if (type != -1) {
861 805 apic_resv_vector[ipl] = vector;
862 806 }
863 807 return (irq);
864 808 }
865 809 }
866 810 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
867 811 return (-1); /* shouldn't happen */
868 812 }
869 813
870 814 static int
871 815 apic_getclkirq(int ipl)
872 816 {
873 817 int irq;
874 818
875 819 if ((irq = apic_get_ipivect(ipl, -1)) == -1)
876 820 return (-1);
877 821 /*
878 822 * Note the vector in apic_clkvect for per clock handling.
879 823 */
880 824 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
881 825 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
882 826 apic_clkvect));
883 827 return (irq);
884 828 }
885 829
886 830 /*
887 831 * Try and disable all interrupts. We just assign interrupts to other
888 832 * processors based on policy. If any were bound by user request, we
889 833 * let them continue and return failure. We do not bother to check
890 834 * for cache affinity while rebinding.
891 835 */
892 836
893 837 static int
894 838 apic_disable_intr(processorid_t cpun)
895 839 {
896 840 int bind_cpu = 0, i, hardbound = 0;
897 841 apic_irq_t *irq_ptr;
898 842 ulong_t iflag;
899 843
900 844 iflag = intr_clear();
901 845 lock_set(&apic_ioapic_lock);
902 846
903 847 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
904 848 if (apic_reprogram_info[i].done == B_FALSE) {
905 849 if (apic_reprogram_info[i].bindcpu == cpun) {
906 850 /*
907 851 * CPU is busy -- it's the target of
908 852 * a pending reprogramming attempt
909 853 */
910 854 lock_clear(&apic_ioapic_lock);
911 855 intr_restore(iflag);
912 856 return (PSM_FAILURE);
913 857 }
914 858 }
915 859 }
916 860
917 861 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
918 862
919 863 apic_cpus[cpun].aci_curipl = 0;
920 864
921 865 i = apic_min_device_irq;
922 866 for (; i <= apic_max_device_irq; i++) {
923 867 /*
924 868 * If there are bound interrupts on this cpu, then
925 869 * rebind them to other processors.
926 870 */
927 871 if ((irq_ptr = apic_irq_table[i]) != NULL) {
928 872 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
929 873 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
930 874 (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
931 875
932 876 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
933 877 hardbound = 1;
934 878 continue;
935 879 }
936 880
937 881 if (irq_ptr->airq_temp_cpu == cpun) {
938 882 do {
939 883 bind_cpu =
940 884 apic_find_cpu(APIC_CPU_INTR_ENABLE);
941 885 } while (apic_rebind_all(irq_ptr, bind_cpu));
942 886 }
943 887 }
944 888 }
945 889
946 890 lock_clear(&apic_ioapic_lock);
947 891 intr_restore(iflag);
948 892
949 893 if (hardbound) {
950 894 cmn_err(CE_WARN, "Could not disable interrupts on %d"
951 895 "due to user bound interrupts", cpun);
952 896 return (PSM_FAILURE);
953 897 }
954 898 else
955 899 return (PSM_SUCCESS);
956 900 }
957 901
958 902 /*
959 903 * Bind interrupts to the CPU's local APIC.
960 904 * Interrupts should not be bound to a CPU's local APIC until the CPU
961 905 * is ready to receive interrupts.
962 906 */
963 907 static void
964 908 apic_enable_intr(processorid_t cpun)
965 909 {
966 910 int i;
967 911 apic_irq_t *irq_ptr;
968 912 ulong_t iflag;
969 913
970 914 iflag = intr_clear();
971 915 lock_set(&apic_ioapic_lock);
972 916
973 917 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
974 918
975 919 i = apic_min_device_irq;
976 920 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
977 921 if ((irq_ptr = apic_irq_table[i]) != NULL) {
978 922 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
979 923 (void) apic_rebind_all(irq_ptr,
980 924 irq_ptr->airq_cpu);
981 925 }
982 926 }
983 927 }
984 928
985 929 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
986 930 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
987 931
988 932 lock_clear(&apic_ioapic_lock);
989 933 intr_restore(iflag);
990 934 }
991 935
992 936 /*
993 937 * If this module needs a periodic handler for the interrupt distribution, it
994 938 * can be added here. The argument to the periodic handler is not currently
995 939 * used, but is reserved for future.
996 940 */
997 941 static void
998 942 apic_post_cyclic_setup(void *arg)
999 943 {
1000 944 _NOTE(ARGUNUSED(arg))
1001 945
1002 946 cyc_handler_t cyh;
1003 947 cyc_time_t cyt;
1004 948
1005 949 /* cpu_lock is held */
1006 950 /* set up a periodic handler for intr redistribution */
1007 951
1008 952 /*
1009 953 * In peridoc mode intr redistribution processing is done in
1010 954 * apic_intr_enter during clk intr processing
1011 955 */
1012 956 if (!apic_oneshot)
1013 957 return;
1014 958
1015 959 /*
1016 960 * Register a periodical handler for the redistribution processing.
1017 961 * Though we would generally prefer to use the DDI interface for
1018 962 * periodic handler invocation, ddi_periodic_add(9F), we are
1019 963 * unfortunately already holding cpu_lock, which ddi_periodic_add will
1020 964 * attempt to take for us. Thus, we add our own cyclic directly:
1021 965 */
1022 966 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
1023 967 cyh.cyh_arg = NULL;
1024 968 cyh.cyh_level = CY_LOW_LEVEL;
1025 969
1026 970 cyt.cyt_when = 0;
1027 971 cyt.cyt_interval = apic_redistribute_sample_interval;
1028 972
1029 973 apic_cyclic_id = cyclic_add(&cyh, &cyt);
1030 974 }
1031 975
1032 976 static void
1033 977 apic_redistribute_compute(void)
1034 978 {
1035 979 int i, j, max_busy;
1036 980
1037 981 if (apic_enable_dynamic_migration) {
1038 982 if (++apic_nticks == apic_sample_factor_redistribution) {
1039 983 /*
1040 984 * Time to call apic_intr_redistribute().
1041 985 * reset apic_nticks. This will cause max_busy
1042 986 * to be calculated below and if it is more than
1043 987 * apic_int_busy, we will do the whole thing
1044 988 */
1045 989 apic_nticks = 0;
1046 990 }
1047 991 max_busy = 0;
1048 992 for (i = 0; i < apic_nproc; i++) {
1049 993 if (!apic_cpu_in_range(i))
1050 994 continue;
1051 995
1052 996 /*
1053 997 * Check if curipl is non zero & if ISR is in
1054 998 * progress
1055 999 */
1056 1000 if (((j = apic_cpus[i].aci_curipl) != 0) &&
1057 1001 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1058 1002
1059 1003 int irq;
1060 1004 apic_cpus[i].aci_busy++;
1061 1005 irq = apic_cpus[i].aci_current[j];
1062 1006 apic_irq_table[irq]->airq_busy++;
1063 1007 }
1064 1008
1065 1009 if (!apic_nticks &&
1066 1010 (apic_cpus[i].aci_busy > max_busy))
1067 1011 max_busy = apic_cpus[i].aci_busy;
1068 1012 }
1069 1013 if (!apic_nticks) {
1070 1014 if (max_busy > apic_int_busy_mark) {
1071 1015 /*
1072 1016 * We could make the following check be
1073 1017 * skipped > 1 in which case, we get a
1074 1018 * redistribution at half the busy mark (due to
1075 1019 * double interval). Need to be able to collect
1076 1020 * more empirical data to decide if that is a
1077 1021 * good strategy. Punt for now.
1078 1022 */
1079 1023 if (apic_skipped_redistribute) {
1080 1024 apic_cleanup_busy();
1081 1025 apic_skipped_redistribute = 0;
1082 1026 } else {
1083 1027 apic_intr_redistribute();
1084 1028 }
1085 1029 } else
1086 1030 apic_skipped_redistribute++;
1087 1031 }
1088 1032 }
1089 1033 }
1090 1034
1091 1035
1092 1036 /*
1093 1037 * The following functions are in the platform specific file so that they
1094 1038 * can be different functions depending on whether we are running on
1095 1039 * bare metal or a hypervisor.
1096 1040 */
1097 1041
1098 1042 /*
1099 1043 * Check to make sure there are enough irq slots
1100 1044 */
1101 1045 int
1102 1046 apic_check_free_irqs(int count)
1103 1047 {
1104 1048 int i, avail;
1105 1049
1106 1050 avail = 0;
1107 1051 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1108 1052 if ((apic_irq_table[i] == NULL) ||
1109 1053 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
1110 1054 if (++avail >= count)
1111 1055 return (PSM_SUCCESS);
1112 1056 }
1113 1057 }
1114 1058 return (PSM_FAILURE);
1115 1059 }
1116 1060
1117 1061 /*
1118 1062 * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
1119 1063 */
1120 1064 int
1121 1065 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
1122 1066 int behavior)
1123 1067 {
1124 1068 int rcount, i;
1125 1069 uchar_t start, irqno;
1126 1070 uint32_t cpu;
1127 1071 major_t major;
1128 1072 apic_irq_t *irqptr;
1129 1073
1130 1074 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
1131 1075 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1132 1076 (void *)dip, inum, pri, count, behavior));
1133 1077
1134 1078 if (count > 1) {
1135 1079 if (behavior == DDI_INTR_ALLOC_STRICT &&
1136 1080 apic_multi_msi_enable == 0)
1137 1081 return (0);
1138 1082 if (apic_multi_msi_enable == 0)
1139 1083 count = 1;
1140 1084 }
1141 1085
1142 1086 if ((rcount = apic_navail_vector(dip, pri)) > count)
1143 1087 rcount = count;
1144 1088 else if (rcount == 0 || (rcount < count &&
1145 1089 behavior == DDI_INTR_ALLOC_STRICT))
1146 1090 return (0);
1147 1091
1148 1092 /* if not ISP2, then round it down */
1149 1093 if (!ISP2(rcount))
1150 1094 rcount = 1 << (highbit(rcount) - 1);
1151 1095
1152 1096 mutex_enter(&airq_mutex);
1153 1097
1154 1098 for (start = 0; rcount > 0; rcount >>= 1) {
1155 1099 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1156 1100 behavior == DDI_INTR_ALLOC_STRICT)
1157 1101 break;
1158 1102 }
1159 1103
1160 1104 if (start == 0) {
1161 1105 /* no vector available */
1162 1106 mutex_exit(&airq_mutex);
1163 1107 return (0);
1164 1108 }
1165 1109
1166 1110 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1167 1111 /* not enough free irq slots available */
1168 1112 mutex_exit(&airq_mutex);
1169 1113 return (0);
1170 1114 }
1171 1115
1172 1116 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1173 1117 for (i = 0; i < rcount; i++) {
1174 1118 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1175 1119 (uchar_t)-1) {
1176 1120 /*
1177 1121 * shouldn't happen because of the
1178 1122 * apic_check_free_irqs() check earlier
1179 1123 */
1180 1124 mutex_exit(&airq_mutex);
1181 1125 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1182 1126 "apic_allocate_irq failed\n"));
1183 1127 return (i);
1184 1128 }
1185 1129 apic_max_device_irq = max(irqno, apic_max_device_irq);
1186 1130 apic_min_device_irq = min(irqno, apic_min_device_irq);
1187 1131 irqptr = apic_irq_table[irqno];
1188 1132 #ifdef DEBUG
1189 1133 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1190 1134 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1191 1135 "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1192 1136 #endif
1193 1137 apic_vector_to_irq[start + i] = (uchar_t)irqno;
1194 1138
1195 1139 irqptr->airq_vector = (uchar_t)(start + i);
1196 1140 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1197 1141 irqptr->airq_intin_no = (uchar_t)rcount;
1198 1142 irqptr->airq_ipl = pri;
1199 1143 irqptr->airq_vector = start + i;
1200 1144 irqptr->airq_origirq = (uchar_t)(inum + i);
1201 1145 irqptr->airq_share_id = 0;
1202 1146 irqptr->airq_mps_intr_index = MSI_INDEX;
1203 1147 irqptr->airq_dip = dip;
1204 1148 irqptr->airq_major = major;
1205 1149 if (i == 0) /* they all bound to the same cpu */
1206 1150 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
1207 1151 0xff, 0xff);
1208 1152 else
1209 1153 irqptr->airq_cpu = cpu;
1210 1154 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1211 1155 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1212 1156 (void *)irqptr->airq_dip, irqptr->airq_vector,
1213 1157 irqptr->airq_origirq, pri));
1214 1158 }
1215 1159 mutex_exit(&airq_mutex);
1216 1160 return (rcount);
1217 1161 }
1218 1162
1219 1163 /*
1220 1164 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1221 1165 */
1222 1166 int
1223 1167 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1224 1168 int behavior)
1225 1169 {
1226 1170 int rcount, i;
1227 1171 major_t major;
1228 1172
1229 1173 mutex_enter(&airq_mutex);
1230 1174
1231 1175 if ((rcount = apic_navail_vector(dip, pri)) > count)
1232 1176 rcount = count;
1233 1177 else if (rcount == 0 || (rcount < count &&
1234 1178 behavior == DDI_INTR_ALLOC_STRICT)) {
1235 1179 rcount = 0;
1236 1180 goto out;
1237 1181 }
1238 1182
1239 1183 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1240 1184 /* not enough free irq slots available */
1241 1185 rcount = 0;
1242 1186 goto out;
1243 1187 }
1244 1188
1245 1189 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1246 1190 for (i = 0; i < rcount; i++) {
1247 1191 uchar_t vector, irqno;
1248 1192 apic_irq_t *irqptr;
1249 1193
1250 1194 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1251 1195 (uchar_t)-1) {
1252 1196 /*
1253 1197 * shouldn't happen because of the
1254 1198 * apic_check_free_irqs() check earlier
1255 1199 */
1256 1200 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1257 1201 "apic_allocate_irq failed\n"));
1258 1202 rcount = i;
1259 1203 goto out;
1260 1204 }
1261 1205 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1262 1206 /*
1263 1207 * shouldn't happen because of the
1264 1208 * apic_navail_vector() call earlier
1265 1209 */
1266 1210 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1267 1211 "apic_allocate_vector failed\n"));
1268 1212 rcount = i;
1269 1213 goto out;
1270 1214 }
1271 1215 apic_max_device_irq = max(irqno, apic_max_device_irq);
1272 1216 apic_min_device_irq = min(irqno, apic_min_device_irq);
1273 1217 irqptr = apic_irq_table[irqno];
1274 1218 irqptr->airq_vector = (uchar_t)vector;
1275 1219 irqptr->airq_ipl = pri;
1276 1220 irqptr->airq_origirq = (uchar_t)(inum + i);
1277 1221 irqptr->airq_share_id = 0;
1278 1222 irqptr->airq_mps_intr_index = MSIX_INDEX;
1279 1223 irqptr->airq_dip = dip;
1280 1224 irqptr->airq_major = major;
1281 1225 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1282 1226 }
1283 1227 out:
1284 1228 mutex_exit(&airq_mutex);
1285 1229 return (rcount);
1286 1230 }
1287 1231
1288 1232 /*
1289 1233 * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1290 1234 * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1291 1235 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1292 1236 * requests and allocated only when pri is set.
1293 1237 */
1294 1238 uchar_t
1295 1239 apic_allocate_vector(int ipl, int irq, int pri)
1296 1240 {
1297 1241 int lowest, highest, i;
1298 1242
1299 1243 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1300 1244 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1301 1245
1302 1246 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1303 1247 lowest -= APIC_VECTOR_PER_IPL;
1304 1248
1305 1249 #ifdef DEBUG
1306 1250 if (apic_restrict_vector) /* for testing shared interrupt logic */
1307 1251 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1308 1252 #endif /* DEBUG */
1309 1253 if (pri == 0)
1310 1254 highest -= APIC_HI_PRI_VECTS;
1311 1255
1312 1256 for (i = lowest; i <= highest; i++) {
1313 1257 if (APIC_CHECK_RESERVE_VECTORS(i))
1314 1258 continue;
1315 1259 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1316 1260 apic_vector_to_irq[i] = (uchar_t)irq;
1317 1261 return (i);
1318 1262 }
1319 1263 }
1320 1264
1321 1265 return (0);
1322 1266 }
1323 1267
1324 1268 /* Mark vector as not being used by any irq */
1325 1269 void
1326 1270 apic_free_vector(uchar_t vector)
1327 1271 {
1328 1272 apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1329 1273 }
1330 1274
1331 1275 /*
1332 1276 * Call rebind to do the actual programming.
1333 1277 * Must be called with interrupts disabled and apic_ioapic_lock held
1334 1278 * 'p' is polymorphic -- if this function is called to process a deferred
1335 1279 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1336 1280 * the irq pointer is retrieved. If not doing deferred reprogramming,
1337 1281 * p is of the type 'apic_irq_t *'.
1338 1282 *
1339 1283 * apic_ioapic_lock must be held across this call, as it protects apic_rebind
1340 1284 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1341 1285 * taken offline after a cpu is selected, but before apic_rebind is called to
1342 1286 * bind interrupts to it.
1343 1287 */
1344 1288 int
1345 1289 apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1346 1290 {
1347 1291 apic_irq_t *irqptr;
1348 1292 struct ioapic_reprogram_data *drep = NULL;
1349 1293 int rv;
1350 1294
1351 1295 if (deferred) {
1352 1296 drep = (struct ioapic_reprogram_data *)p;
1353 1297 ASSERT(drep != NULL);
1354 1298 irqptr = drep->irqp;
1355 1299 } else
1356 1300 irqptr = (apic_irq_t *)p;
1357 1301
1358 1302 ASSERT(irqptr != NULL);
1359 1303
1360 1304 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1361 1305 if (rv) {
1362 1306 /*
1363 1307 * CPU is not up or interrupts are disabled. Fall back to
1364 1308 * the first available CPU
1365 1309 */
1366 1310 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1367 1311 drep);
1368 1312 }
1369 1313
1370 1314 return (rv);
1371 1315 }
1372 1316
1373 1317
1374 1318 uchar_t
1375 1319 apic_modify_vector(uchar_t vector, int irq)
1376 1320 {
1377 1321 apic_vector_to_irq[vector] = (uchar_t)irq;
1378 1322 return (vector);
1379 1323 }
1380 1324
1381 1325 char *
1382 1326 apic_get_apic_type(void)
1383 1327 {
1384 1328 return (apic_psm_info.p_mach_idstring);
1385 1329 }
1386 1330
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1387 1331 void
1388 1332 x2apic_update_psm(void)
1389 1333 {
1390 1334 struct psm_ops *pops = &apic_ops;
1391 1335
1392 1336 ASSERT(pops != NULL);
1393 1337
1394 1338 pops->psm_intr_exit = x2apic_intr_exit;
1395 1339 pops->psm_setspl = x2apic_setspl;
1396 1340
1397 - pops->psm_send_ipi = x2apic_send_ipi;
1341 + pops->psm_send_ipi = x2apic_send_ipi;
1398 1342 send_dirintf = pops->psm_send_ipi;
1399 1343
1400 1344 apic_mode = LOCAL_X2APIC;
1401 1345 apic_change_ops();
1402 1346 }
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