296 mc = "Intel 5000";
297 break;
298 }
299 return (mc);
300 }
301
302 static void
303 inb_create_nvl()
304 {
305 nvlist_t *nvl;
306
307 (void) nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP);
308 (void) nvlist_add_uint8(nvl, MCINTEL_NVLIST_VERSTR,
309 MCINTEL_NVLIST_VERS);
310 (void) nvlist_add_string(nvl, "memory-controller", inb_mc_name());
311 if (nb_chipset == INTEL_NB_5100)
312 (void) nvlist_add_uint8(nvl, MCINTEL_NVLIST_NMEM,
313 (uint8_t)nb_number_memory_controllers);
314 inb_dimmlist(nvl);
315
316 if (inb_mc_nvl)
317 nvlist_free(inb_mc_nvl);
318 inb_mc_nvl = nvl;
319 }
320
321 static void
322 inb_mc_snapshot_destroy()
323 {
324 ASSERT(RW_LOCK_HELD(&inb_mc_lock));
325
326 if (inb_mc_snapshot == NULL)
327 return;
328
329 kmem_free(inb_mc_snapshot, inb_mc_snapshotsz);
330 inb_mc_snapshot = NULL;
331 inb_mc_snapshotsz = 0;
332 inb_mc_snapshotgen++;
333 }
334
335 static int
336 inb_mc_snapshot_update()
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296 mc = "Intel 5000";
297 break;
298 }
299 return (mc);
300 }
301
302 static void
303 inb_create_nvl()
304 {
305 nvlist_t *nvl;
306
307 (void) nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP);
308 (void) nvlist_add_uint8(nvl, MCINTEL_NVLIST_VERSTR,
309 MCINTEL_NVLIST_VERS);
310 (void) nvlist_add_string(nvl, "memory-controller", inb_mc_name());
311 if (nb_chipset == INTEL_NB_5100)
312 (void) nvlist_add_uint8(nvl, MCINTEL_NVLIST_NMEM,
313 (uint8_t)nb_number_memory_controllers);
314 inb_dimmlist(nvl);
315
316 nvlist_free(inb_mc_nvl);
317 inb_mc_nvl = nvl;
318 }
319
320 static void
321 inb_mc_snapshot_destroy()
322 {
323 ASSERT(RW_LOCK_HELD(&inb_mc_lock));
324
325 if (inb_mc_snapshot == NULL)
326 return;
327
328 kmem_free(inb_mc_snapshot, inb_mc_snapshotsz);
329 inb_mc_snapshot = NULL;
330 inb_mc_snapshotsz = 0;
331 inb_mc_snapshotgen++;
332 }
333
334 static int
335 inb_mc_snapshot_update()
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