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XXXX introduce drv_sectohz

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          --- old/usr/src/uts/sun4u/sunfire/io/sysctrl.c
          +++ new/usr/src/uts/sun4u/sunfire/io/sysctrl.c
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 435  435          /* First set all of the timeout values */
 436  436          spur_timeout_hz = drv_usectohz(SPUR_TIMEOUT_USEC);
 437  437          spur_long_timeout_hz = drv_usectohz(SPUR_LONG_TIMEOUT_USEC);
 438  438          ac_timeout_hz = drv_usectohz(AC_TIMEOUT_USEC);
 439  439          ps_fail_timeout_hz = drv_usectohz(PS_FAIL_TIMEOUT_USEC);
 440  440          pps_fan_timeout_hz = drv_usectohz(PPS_FAN_TIMEOUT_USEC);
 441  441          bd_insert_delay_hz = drv_usectohz(BRD_INSERT_DELAY_USEC);
 442  442          bd_insert_retry_hz = drv_usectohz(BRD_INSERT_RETRY_USEC);
 443  443          bd_remove_timeout_hz = drv_usectohz(BRD_REMOVE_TIMEOUT_USEC);
 444  444          blink_led_timeout_hz = drv_usectohz(BLINK_LED_TIMEOUT_USEC);
 445      -        overtemp_timeout_hz = drv_usectohz(OVERTEMP_TIMEOUT_SEC * MICROSEC);
      445 +        overtemp_timeout_hz = drv_sectohz(OVERTEMP_TIMEOUT_SEC);
 446  446          keyswitch_timeout_hz = drv_usectohz(KEYSWITCH_TIMEOUT_USEC);
 447  447  
 448  448          /*
 449  449           * Map in the registers sets that OBP hands us. According
 450  450           * to the sun4u device tree spec., the register sets are as
 451  451           * follows:
 452  452           *
 453  453           *      0       Clock Frequency Registers (contains the bit
 454  454           *              for enabling the remote console reset)
 455  455           *      1       Misc (has all the registers that we need
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