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XXXX introduce drv_sectohz


3212             TLU_SLOT_CAPABILITIES_SPLS);
3213         reg &= ~(TLU_SLOT_CAPABILITIES_SPLV_MASK <<
3214             TLU_SLOT_CAPABILITIES_SPLV);
3215         reg |= (0x19 << TLU_SLOT_CAPABILITIES_SPLV);
3216         CSR_XS(csr_base, TLU_SLOT_CAPABILITIES, reg);
3217 
3218         /* Turn on Power LED */
3219         reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3220         reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK;
3221         reg = pcie_slotctl_pwr_indicator_set(reg,
3222             PCIE_SLOTCTL_INDICATOR_STATE_ON);
3223         CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3224 
3225         /* Notify to SCF */
3226         if (CSR_BR(csr_base, HOTPLUG_CONTROL, SLOTPON))
3227                 CSR_BC(csr_base, HOTPLUG_CONTROL, SLOTPON);
3228         else
3229                 CSR_BS(csr_base, HOTPLUG_CONTROL, SLOTPON);
3230 
3231         /* Wait for one second */
3232         delay(drv_usectohz(1000000));
3233 
3234         return (DDI_SUCCESS);
3235 
3236 fail2:
3237         /* Link up is failed */
3238         CSR_BS(csr_base, FLP_PORT_CONTROL, PORT_DIS);
3239         CSR_BC(csr_base, HOTPLUG_CONTROL, N_PERST);
3240         delay(drv_usectohz(150));
3241 
3242         CSR_BC(csr_base, HOTPLUG_CONTROL, CLKEN);
3243         delay(drv_usectohz(100));
3244 
3245 fail1:
3246         CSR_BC(csr_base, TLU_SLOT_CONTROL, PWFDEN);
3247 
3248         CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN);
3249 
3250         reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3251         reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK;
3252         reg = pcie_slotctl_pwr_indicator_set(reg,


3335         CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3336 
3337         /* Notify to SCF */
3338         if (CSR_BR(csr_base, HOTPLUG_CONTROL, SLOTPON))
3339                 CSR_BC(csr_base, HOTPLUG_CONTROL, SLOTPON);
3340         else
3341                 CSR_BS(csr_base, HOTPLUG_CONTROL, SLOTPON);
3342 
3343         start_time = gethrtime();
3344         /* Check Leaf Reset status */
3345         while (!(CSR_BR(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3))) {
3346                 if ((end_time = (gethrtime() - start_time)) >
3347                     oberon_leaf_reset_timeout) {
3348                         cmn_err(CE_WARN, "Oberon leaf reset is not completed, "
3349                             "even after waiting %llx ticks", end_time);
3350 
3351                         break;
3352                 }
3353 
3354                 /* Wait for one second */
3355                 delay(drv_usectohz(1000000));
3356         }
3357 
3358         /* Indicator LED off */
3359         reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3360         reg &= ~PCIE_SLOTCTL_ATTN_INDICATOR_MASK;
3361         reg = pcie_slotctl_attn_indicator_set(reg,
3362             PCIE_SLOTCTL_INDICATOR_STATE_OFF);
3363         CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3364 
3365         return (DDI_SUCCESS);
3366 }
3367 
3368 static uint_t
3369 oberon_hpreg_get(void *cookie, off_t off)
3370 {
3371         caddr_t csr_base = *(caddr_t *)cookie;
3372         volatile uint64_t val = -1ull;
3373 
3374         switch (off) {
3375         case PCIE_SLOTCAP:




3212             TLU_SLOT_CAPABILITIES_SPLS);
3213         reg &= ~(TLU_SLOT_CAPABILITIES_SPLV_MASK <<
3214             TLU_SLOT_CAPABILITIES_SPLV);
3215         reg |= (0x19 << TLU_SLOT_CAPABILITIES_SPLV);
3216         CSR_XS(csr_base, TLU_SLOT_CAPABILITIES, reg);
3217 
3218         /* Turn on Power LED */
3219         reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3220         reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK;
3221         reg = pcie_slotctl_pwr_indicator_set(reg,
3222             PCIE_SLOTCTL_INDICATOR_STATE_ON);
3223         CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3224 
3225         /* Notify to SCF */
3226         if (CSR_BR(csr_base, HOTPLUG_CONTROL, SLOTPON))
3227                 CSR_BC(csr_base, HOTPLUG_CONTROL, SLOTPON);
3228         else
3229                 CSR_BS(csr_base, HOTPLUG_CONTROL, SLOTPON);
3230 
3231         /* Wait for one second */
3232         delay(drv_sectohz(1));
3233 
3234         return (DDI_SUCCESS);
3235 
3236 fail2:
3237         /* Link up is failed */
3238         CSR_BS(csr_base, FLP_PORT_CONTROL, PORT_DIS);
3239         CSR_BC(csr_base, HOTPLUG_CONTROL, N_PERST);
3240         delay(drv_usectohz(150));
3241 
3242         CSR_BC(csr_base, HOTPLUG_CONTROL, CLKEN);
3243         delay(drv_usectohz(100));
3244 
3245 fail1:
3246         CSR_BC(csr_base, TLU_SLOT_CONTROL, PWFDEN);
3247 
3248         CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN);
3249 
3250         reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3251         reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK;
3252         reg = pcie_slotctl_pwr_indicator_set(reg,


3335         CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3336 
3337         /* Notify to SCF */
3338         if (CSR_BR(csr_base, HOTPLUG_CONTROL, SLOTPON))
3339                 CSR_BC(csr_base, HOTPLUG_CONTROL, SLOTPON);
3340         else
3341                 CSR_BS(csr_base, HOTPLUG_CONTROL, SLOTPON);
3342 
3343         start_time = gethrtime();
3344         /* Check Leaf Reset status */
3345         while (!(CSR_BR(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3))) {
3346                 if ((end_time = (gethrtime() - start_time)) >
3347                     oberon_leaf_reset_timeout) {
3348                         cmn_err(CE_WARN, "Oberon leaf reset is not completed, "
3349                             "even after waiting %llx ticks", end_time);
3350 
3351                         break;
3352                 }
3353 
3354                 /* Wait for one second */
3355                 delay(drv_sectohz(1));
3356         }
3357 
3358         /* Indicator LED off */
3359         reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3360         reg &= ~PCIE_SLOTCTL_ATTN_INDICATOR_MASK;
3361         reg = pcie_slotctl_attn_indicator_set(reg,
3362             PCIE_SLOTCTL_INDICATOR_STATE_OFF);
3363         CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3364 
3365         return (DDI_SUCCESS);
3366 }
3367 
3368 static uint_t
3369 oberon_hpreg_get(void *cookie, off_t off)
3370 {
3371         caddr_t csr_base = *(caddr_t *)cookie;
3372         volatile uint64_t val = -1ull;
3373 
3374         switch (off) {
3375         case PCIE_SLOTCAP: