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--- old/usr/src/uts/sun4u/daktari/os/daktari.c
+++ new/usr/src/uts/sun4u/daktari/os/daktari.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 27 #include <sys/cpuvar.h>
28 28 #include <sys/param.h>
29 29 #include <sys/systm.h>
30 30 #include <sys/sunddi.h>
31 31 #include <sys/ddi.h>
32 32 #include <sys/esunddi.h>
33 33 #include <sys/sysmacros.h>
34 34 #include <sys/note.h>
35 35
36 36 #include <sys/modctl.h> /* for modload() */
37 37 #include <sys/platform_module.h>
38 38 #include <sys/errno.h>
39 39 #include <sys/daktari.h>
40 40 #include <sys/machsystm.h>
41 41 #include <sys/promif.h>
42 42 #include <vm/page.h>
43 43 #include <sys/memnode.h>
44 44 #include <vm/vm_dep.h>
45 45
46 46 /* I2C Stuff */
47 47 #include <sys/i2c/clients/i2c_client.h>
48 48
49 49
50 50 int (*p2get_mem_unum)(int, uint64_t, char *, int, int *);
51 51
52 52 /* Daktari Keyswitch Information */
53 53 #define DAK_KEY_POLL_PORT 3
54 54 #define DAK_KEY_POLL_BIT 2
55 55 #define DAK_KEY_POLL_INTVL 10
56 56
57 57 static boolean_t key_locked_bit;
58 58 static clock_t keypoll_timeout_hz;
59 59
60 60 /*
61 61 * Table that maps memory slices to a specific memnode.
62 62 */
63 63 int slice_to_memnode[DAK_MAX_SLICE];
64 64
65 65 /*
66 66 * For software memory interleaving support.
67 67 */
68 68 static void update_mem_bounds(int, int, int, uint64_t, uint64_t);
69 69
70 70 static uint64_t
71 71 slice_table[DAK_SBD_SLOTS][DAK_CPUS_PER_BOARD][DAK_BANKS_PER_MC][2];
72 72
73 73 #define SLICE_PA 0
74 74 #define SLICE_SPAN 1
75 75
76 76 int (*daktari_ssc050_get_port_bit) (dev_info_t *, int, int, uint8_t *, int);
77 77 extern void (*abort_seq_handler)();
78 78 static int daktari_dev_search(dev_info_t *, void *);
79 79 static void keyswitch_poll(void *);
80 80 static void daktari_abort_seq_handler(char *msg);
81 81
82 82 void
83 83 startup_platform(void)
84 84 {
85 85 /*
86 86 * Disable an active h/w watchdog timer
87 87 * upon exit to OBP.
88 88 */
89 89 extern int disable_watchdog_on_exit;
90 90 disable_watchdog_on_exit = 1;
91 91 }
92 92
93 93 int
94 94 set_platform_tsb_spares()
95 95 {
96 96 return (0);
97 97 }
98 98
99 99 #pragma weak mmu_init_large_pages
100 100
101 101 void
102 102 set_platform_defaults(void)
103 103 {
104 104 extern void mmu_init_large_pages(size_t);
105 105
106 106 if ((mmu_page_sizes == max_mmu_page_sizes) &&
107 107 (mmu_ism_pagesize != DEFAULT_ISM_PAGESIZE)) {
108 108 if (&mmu_init_large_pages)
109 109 mmu_init_large_pages(mmu_ism_pagesize);
110 110 }
111 111 }
112 112
113 113 void
114 114 load_platform_modules(void)
115 115 {
116 116 if (modload("misc", "pcihp") < 0) {
117 117 cmn_err(CE_NOTE, "pcihp driver failed to load");
118 118 }
119 119 if (modload("drv", "pmc") < 0) {
120 120 cmn_err(CE_NOTE, "pmc driver failed to load");
121 121 }
122 122
123 123 }
124 124
125 125 void
126 126 load_platform_drivers(void)
127 127 {
128 128 char **drv;
129 129 dev_info_t *keysw_dip;
130 130
131 131 static char *boot_time_drivers[] = {
132 132 "hpc3130",
133 133 "todds1287",
134 134 "mc-us3",
135 135 "ssc050",
136 136 "pcisch",
137 137 NULL
138 138 };
139 139
140 140 for (drv = boot_time_drivers; *drv; drv++) {
141 141 if (i_ddi_attach_hw_nodes(*drv) != DDI_SUCCESS)
142 142 cmn_err(CE_WARN, "Failed to install \"%s\" driver.",
143 143 *drv);
144 144 }
145 145
146 146 /*
147 147 * mc-us3 & ssc050 must stay loaded for plat_get_mem_unum()
148 148 * and keyswitch_poll()
149 149 */
150 150 (void) ddi_hold_driver(ddi_name_to_major("mc-us3"));
151 151 (void) ddi_hold_driver(ddi_name_to_major("ssc050"));
152 152
153 153 /* Gain access into the ssc050_get_port function */
154 154 daktari_ssc050_get_port_bit = (int (*) (dev_info_t *, int, int,
155 155 uint8_t *, int)) modgetsymvalue("ssc050_get_port_bit", 0);
156 156 if (daktari_ssc050_get_port_bit == NULL) {
157 157 cmn_err(CE_WARN, "cannot find ssc050_get_port_bit");
158 158 return;
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159 159 }
160 160
161 161 ddi_walk_devs(ddi_root_node(), daktari_dev_search, (void *)&keysw_dip);
162 162 ASSERT(keysw_dip != NULL);
163 163
164 164 /*
165 165 * prevent detach of i2c-ssc050
166 166 */
167 167 e_ddi_hold_devi(keysw_dip);
168 168
169 - keypoll_timeout_hz = drv_usectohz(10 * MICROSEC);
169 + keypoll_timeout_hz = drv_sectohz(10);
170 170 keyswitch_poll(keysw_dip);
171 171 abort_seq_handler = daktari_abort_seq_handler;
172 172 }
173 173
174 174 static int
175 175 daktari_dev_search(dev_info_t *dip, void *arg)
176 176 {
177 177 char *compatible = NULL; /* Search tree for "i2c-ssc050" */
178 178 int *dev_regs; /* Info about where the device is. */
179 179 uint_t len;
180 180 int err;
181 181
182 182 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
183 183 "compatible", &compatible) != DDI_PROP_SUCCESS)
184 184 return (DDI_WALK_CONTINUE);
185 185
186 186 if (strcmp(compatible, "i2c-ssc050") == 0) {
187 187 ddi_prop_free(compatible);
188 188
189 189 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip,
190 190 DDI_PROP_DONTPASS, "reg", &dev_regs, &len);
191 191 if (err != DDI_PROP_SUCCESS) {
192 192 return (DDI_WALK_CONTINUE);
193 193 }
194 194 /*
195 195 * regs[0] contains the bus number and regs[1]
196 196 * contains the device address of the i2c device.
197 197 * 0x82 is the device address of the i2c device
198 198 * from which the key switch position is read.
199 199 */
200 200 if (dev_regs[0] == 0 && dev_regs[1] == 0x82) {
201 201 *((dev_info_t **)arg) = dip;
202 202 ddi_prop_free(dev_regs);
203 203 return (DDI_WALK_TERMINATE);
204 204 }
205 205 ddi_prop_free(dev_regs);
206 206 } else {
207 207 ddi_prop_free(compatible);
208 208 }
209 209 return (DDI_WALK_CONTINUE);
210 210 }
211 211
212 212 static void
213 213 keyswitch_poll(void *arg)
214 214 {
215 215 dev_info_t *dip = arg;
216 216 uchar_t port_byte;
217 217 int port = DAK_KEY_POLL_PORT;
218 218 int bit = DAK_KEY_POLL_BIT;
219 219 int err;
220 220
221 221 err = daktari_ssc050_get_port_bit(dip, port, bit,
222 222 &port_byte, I2C_NOSLEEP);
223 223 if (err != 0) {
224 224 cmn_err(CE_WARN, "keyswitch polling disabled: "
225 225 "errno=%d while reading ssc050", err);
226 226 return;
227 227 }
228 228
229 229 key_locked_bit = (boolean_t)((port_byte & 0x1));
230 230 (void) timeout(keyswitch_poll, (caddr_t)dip, keypoll_timeout_hz);
231 231 }
232 232
233 233 static void
234 234 daktari_abort_seq_handler(char *msg)
235 235 {
236 236 if (key_locked_bit == 0)
237 237 cmn_err(CE_CONT, "KEY in LOCKED position, "
238 238 "ignoring debug enter sequence");
239 239 else {
240 240 debug_enter(msg);
241 241 }
242 242 }
243 243
244 244
245 245 int
246 246 plat_cpu_poweron(struct cpu *cp)
247 247 {
248 248 _NOTE(ARGUNUSED(cp))
249 249 return (ENOTSUP);
250 250 }
251 251
252 252 int
253 253 plat_cpu_poweroff(struct cpu *cp)
254 254 {
255 255 _NOTE(ARGUNUSED(cp))
256 256 return (ENOTSUP);
257 257 }
258 258
259 259 /*
260 260 * Given a pfn, return the board and beginning/end of the page's
261 261 * memory controller's address range.
262 262 */
263 263 static int
264 264 plat_discover_slice(pfn_t pfn, pfn_t *first, pfn_t *last)
265 265 {
266 266 int bd, cpu, bank;
267 267
268 268 for (bd = 0; bd < DAK_SBD_SLOTS; bd++) {
269 269 for (cpu = 0; cpu < DAK_CPUS_PER_BOARD; cpu++) {
270 270 for (bank = 0; bank < DAK_BANKS_PER_MC; bank++) {
271 271 uint64_t *slice = slice_table[bd][cpu][bank];
272 272 uint64_t base = btop(slice[SLICE_PA]);
273 273 uint64_t len = btop(slice[SLICE_SPAN]);
274 274 if (len && pfn >= base && pfn < (base + len)) {
275 275 *first = base;
276 276 *last = base + len - 1;
277 277 return (bd);
278 278 }
279 279 }
280 280 }
281 281 }
282 282 panic("plat_discover_slice: no slice for pfn 0x%lx\n", pfn);
283 283 /* NOTREACHED */
284 284 }
285 285
286 286 /*ARGSUSED*/
287 287 void
288 288 plat_freelist_process(int mnode)
289 289 {}
290 290
291 291
292 292 /*
293 293 * Called for each board/cpu/PA range detected in plat_fill_mc().
294 294 */
295 295 static void
296 296 update_mem_bounds(int boardid, int cpuid, int bankid,
297 297 uint64_t base, uint64_t size)
298 298 {
299 299 uint64_t end;
300 300 int mnode;
301 301
302 302 slice_table[boardid][cpuid][bankid][SLICE_PA] = base;
303 303 slice_table[boardid][cpuid][bankid][SLICE_SPAN] = size;
304 304
305 305 end = base + size - 1;
306 306
307 307 /*
308 308 * First see if this board already has a memnode associated
309 309 * with it. If not, see if this slice has a memnode. This
310 310 * covers the cases where a single slice covers multiple
311 311 * boards (cross-board interleaving) and where a single
312 312 * board has multiple slices (1+GB DIMMs).
313 313 */
314 314 if ((mnode = plat_lgrphand_to_mem_node(boardid)) == -1) {
315 315 if ((mnode = slice_to_memnode[PA_2_SLICE(base)]) == -1)
316 316 mnode = mem_node_alloc();
317 317
318 318 ASSERT(mnode >= 0);
319 319 ASSERT(mnode < MAX_MEM_NODES);
320 320 plat_assign_lgrphand_to_mem_node(boardid, mnode);
321 321 }
322 322
323 323 base = P2ALIGN(base, (1ul << PA_SLICE_SHIFT));
324 324
325 325 while (base < end) {
326 326 slice_to_memnode[PA_2_SLICE(base)] = mnode;
327 327 base += (1ul << PA_SLICE_SHIFT);
328 328 }
329 329 }
330 330
331 331 /*
332 332 * Dynamically detect memory slices in the system by decoding
333 333 * the cpu memory decoder registers at boot time.
334 334 */
335 335 void
336 336 plat_fill_mc(pnode_t nodeid)
337 337 {
338 338 uint64_t mc_addr, saf_addr;
339 339 uint64_t mc_decode[DAK_BANKS_PER_MC];
340 340 uint64_t base, size;
341 341 uint64_t saf_mask;
342 342 uint64_t offset;
343 343 uint32_t regs[4];
344 344 int len;
345 345 int local_mc;
346 346 int portid;
347 347 int boardid;
348 348 int cpuid;
349 349 int i;
350 350
351 351 if ((prom_getprop(nodeid, "portid", (caddr_t)&portid) < 0) ||
352 352 (portid == -1))
353 353 return;
354 354
355 355 /*
356 356 * Decode the board number from the MC portid. Assumes
357 357 * portid == safari agentid.
358 358 */
359 359 boardid = DAK_GETSLOT(portid);
360 360 cpuid = DAK_GETSID(portid);
361 361
362 362 /*
363 363 * The "reg" property returns 4 32-bit values. The first two are
364 364 * combined to form a 64-bit address. The second two are for a
365 365 * 64-bit size, but we don't actually need to look at that value.
366 366 */
367 367 len = prom_getproplen(nodeid, "reg");
368 368 if (len != (sizeof (uint32_t) * 4)) {
369 369 prom_printf("Warning: malformed 'reg' property\n");
370 370 return;
371 371 }
372 372 if (prom_getprop(nodeid, "reg", (caddr_t)regs) < 0)
373 373 return;
374 374 mc_addr = ((uint64_t)regs[0]) << 32;
375 375 mc_addr |= (uint64_t)regs[1];
376 376
377 377 /*
378 378 * Figure out whether the memory controller we are examining
379 379 * belongs to this CPU or a different one.
380 380 */
381 381 saf_addr = lddsafaddr(8);
382 382 saf_mask = (uint64_t)SAF_MASK;
383 383 if ((mc_addr & saf_mask) == saf_addr)
384 384 local_mc = 1;
385 385 else
386 386 local_mc = 0;
387 387
388 388 for (i = 0; i < DAK_BANKS_PER_MC; i++) {
389 389 /*
390 390 * Memory decode masks are at offsets 0x10 - 0x28.
391 391 */
392 392 offset = 0x10 + (i << 3);
393 393
394 394 /*
395 395 * If the memory controller is local to this CPU, we use
396 396 * the special ASI to read the decode registers.
397 397 * Otherwise, we load the values from a magic address in
398 398 * I/O space.
399 399 */
400 400 if (local_mc)
401 401 mc_decode[i] = lddmcdecode(offset);
402 402 else
403 403 mc_decode[i] = lddphysio(mc_addr | offset);
404 404
405 405 /*
406 406 * If the upper bit is set, we have a valid mask
407 407 */
408 408 if ((int64_t)mc_decode[i] < 0) {
409 409 /*
410 410 * The memory decode register is a bitmask field,
411 411 * so we can decode that into both a base and
412 412 * a span.
413 413 */
414 414 base = MC_BASE(mc_decode[i]) << PHYS2UM_SHIFT;
415 415 size = MC_UK2SPAN(mc_decode[i]);
416 416 update_mem_bounds(boardid, cpuid, i, base, size);
417 417 }
418 418 }
419 419 }
420 420
421 421
422 422 /*
423 423 * This routine is run midway through the boot process. By the time we get
424 424 * here, we know about all the active CPU boards in the system, and we have
425 425 * extracted information about each board's memory from the memory
426 426 * controllers. We have also figured out which ranges of memory will be
427 427 * assigned to which memnodes, so we walk the slice table to build the table
428 428 * of memnodes.
429 429 */
430 430 /* ARGSUSED */
431 431 void
432 432 plat_build_mem_nodes(prom_memlist_t *list, size_t nelems)
433 433 {
434 434 int slice;
435 435 pfn_t basepfn;
436 436 pgcnt_t npgs;
437 437
438 438 mem_node_pfn_shift = PFN_SLICE_SHIFT;
439 439 mem_node_physalign = (1ull << PA_SLICE_SHIFT);
440 440 npgs = 1ull << PFN_SLICE_SHIFT;
441 441
442 442 for (slice = 0; slice < DAK_MAX_SLICE; slice++) {
443 443 if (slice_to_memnode[slice] == -1)
444 444 continue;
445 445 basepfn = (uint64_t)slice << PFN_SLICE_SHIFT;
446 446 mem_node_add_slice(basepfn, basepfn + npgs - 1);
447 447 }
448 448 }
449 449
450 450
451 451
452 452 /*
453 453 * Daktari support for lgroups.
454 454 *
455 455 * On Daktari, an lgroup platform handle == slot number.
456 456 *
457 457 * Mappings between lgroup handles and memnodes are managed
458 458 * in addition to mappings between memory slices and memnodes
459 459 * to support cross-board interleaving as well as multiple
460 460 * slices per board (e.g. >1GB DIMMs). The initial mapping
461 461 * of memnodes to lgroup handles is determined at boot time.
462 462 */
463 463 int
464 464 plat_pfn_to_mem_node(pfn_t pfn)
465 465 {
466 466 return (slice_to_memnode[PFN_2_SLICE(pfn)]);
467 467 }
468 468
469 469 /*
470 470 * Return the platform handle for the lgroup containing the given CPU
471 471 *
472 472 * For Daktari, lgroup platform handle == slot number
473 473 */
474 474 lgrp_handle_t
475 475 plat_lgrp_cpu_to_hand(processorid_t id)
476 476 {
477 477 return (DAK_GETSLOT(id));
478 478 }
479 479
480 480 /*
481 481 * Platform specific lgroup initialization
482 482 */
483 483 void
484 484 plat_lgrp_init(void)
485 485 {
486 486 int i;
487 487
488 488 /*
489 489 * Initialize lookup tables to invalid values so we catch
490 490 * any illegal use of them.
491 491 */
492 492 for (i = 0; i < DAK_MAX_SLICE; i++) {
493 493 slice_to_memnode[i] = -1;
494 494 }
495 495 }
496 496
497 497 /*
498 498 * Return latency between "from" and "to" lgroups
499 499 *
500 500 * This latency number can only be used for relative comparison
501 501 * between lgroups on the running system, cannot be used across platforms,
502 502 * and may not reflect the actual latency. It is platform and implementation
503 503 * specific, so platform gets to decide its value. It would be nice if the
504 504 * number was at least proportional to make comparisons more meaningful though.
505 505 * NOTE: The numbers below are supposed to be load latencies for uncached
506 506 * memory divided by 10.
507 507 */
508 508 int
509 509 plat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to)
510 510 {
511 511 /*
512 512 * Return min remote latency when there are more than two lgroups
513 513 * (root and child) and getting latency between two different lgroups
514 514 * or root is involved
515 515 */
516 516 if (lgrp_optimizations() && (from != to ||
517 517 from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE))
518 518 return (21);
519 519 else
520 520 return (19);
521 521 }
522 522 /*
523 523 * No platform drivers on this platform
524 524 */
525 525 char *platform_module_list[] = {
526 526 (char *)0
527 527 };
528 528
529 529 /*ARGSUSED*/
530 530 void
531 531 plat_tod_fault(enum tod_fault_type tod_bad)
532 532 {
533 533 }
534 534
535 535 /*ARGSUSED*/
536 536 int
537 537 plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id,
538 538 int flt_in_memory, ushort_t flt_status, char *buf, int buflen, int *lenp)
539 539 {
540 540 if (flt_in_memory && (p2get_mem_unum != NULL))
541 541 return (p2get_mem_unum(synd_code, P2ALIGN(flt_addr, 8),
542 542 buf, buflen, lenp));
543 543 else
544 544 return (ENOTSUP);
545 545 }
546 546
547 547 /*
548 548 * This platform hook gets called from mc_add_mem_unum_label() in the mc-us3
549 549 * driver giving each platform the opportunity to add platform
550 550 * specific label information to the unum for ECC error logging purposes.
551 551 */
552 552 void
553 553 plat_add_mem_unum_label(char *unum, int mcid, int bank, int dimm)
554 554 {
555 555 _NOTE(ARGUNUSED(bank, dimm))
556 556
557 557 char board = DAK_GETSLOT_LABEL(mcid);
558 558 char old_unum[UNUM_NAMLEN];
559 559
560 560 (void) strcpy(old_unum, unum);
561 561 (void) snprintf(unum, UNUM_NAMLEN, "Slot %c: %s", board, old_unum);
562 562 }
563 563
564 564 int
565 565 plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp)
566 566 {
567 567 char board = DAK_GETSLOT_LABEL(cpuid);
568 568
569 569 if (snprintf(buf, buflen, "Slot %c", board) >= buflen) {
570 570 return (ENOSPC);
571 571 } else {
572 572 *lenp = strlen(buf);
573 573 return (0);
574 574 }
575 575 }
576 576
577 577 /*
578 578 * The zuluvm module requires a dmv interrupt for each installed zulu board.
579 579 */
580 580 void
581 581 plat_dmv_params(uint_t *hwint, uint_t *swint)
582 582 {
583 583 *hwint = 0;
584 584 *swint = DAK_SBD_SLOTS - 1;
585 585 }
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