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--- old/usr/src/uts/sun/sys/fdreg.h
+++ new/usr/src/uts/sun/sys/fdreg.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License, Version 1.0 only
6 6 * (the "License"). You may not use this file except in compliance
7 7 * with the License.
8 8 *
9 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 10 * or http://www.opensolaris.org/os/licensing.
11 11 * See the License for the specific language governing permissions
12 12 * and limitations under the License.
13 13 *
14 14 * When distributing Covered Code, include this CDDL HEADER in each
15 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 16 * If applicable, add the following below this CDDL HEADER, with the
17 17 * fields enclosed by brackets "[]" replaced with your own identifying
18 18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 19 *
20 20 * CDDL HEADER END
21 21 */
22 22 /*
23 23 * Copyright (c) 1989-1998,2000 by Sun Microsystems, Inc.
24 24 * All rights reserved.
25 25 */
26 26
27 27 #ifndef _SYS_FDREG_H
28 28 #define _SYS_FDREG_H
29 29
30 30 #pragma ident "%Z%%M% %I% %E% SMI"
31 31
32 32 #ifdef __cplusplus
33 33 extern "C" {
34 34 #endif
35 35
36 36
37 37 /*
38 38 * Floppy Controller Registers
39 39 */
40 40 #ifndef _ASM
41 41 union fdcreg {
42 42 volatile struct {
43 43 uchar_t fdc_control;
44 44 uchar_t fdc_fifo;
45 45 } fdc_82072_reg;
46 46
47 47 volatile struct fdc_82077_reg {
48 48 uchar_t fdc_filler1[2];
49 49 uchar_t fdc_dor; /* Digital Output Register */
50 50 uchar_t fdc_filler2;
51 51 uchar_t fdc_control; /* DSR on write, MSR on read */
52 52 #define fdc_msr fdc_control
53 53 #define fdc_dsr fdc_control
54 54 uchar_t fdc_fifo;
55 55 uchar_t fdc_filler3;
56 56 uchar_t fdc_dir; /* Digital Input Register */
57 57 #define fdc_ccr fdc_dir
58 58 } fdc_82077_reg;
59 59 };
60 60 #endif /* !_ASM */
61 61
62 62 /* DSR - data rate select register */
63 63 #define SWR 0x80 /* software reset */
64 64 #define PD 0x40 /* power down */
65 65 #define EPL 0x20 /* enable phase lock loop */
66 66 #define PRECOMPMSK 0x1c /* precomp mask */
67 67 #define DRSELMSK 0x3 /* data rate select mask */
68 68
69 69 /* MSR - main status register */
70 70 #define RQM 0x80 /* request for master - chip needs attention */
71 71 #define DIO 0x40 /* data in/out - 1 = remove bytes from fifo */
72 72 #define NDM 0x20 /* non-dma mode - 1 during execution phase */
73 73 #define CB 0x10 /* controller busy - command in progress */
74 74
75 75 /* command types */
76 76 #define GPLN 0x1b /* gap length for read/write command */
77 77 #define GPLF 0x54 /* gap length for format command */
78 78 #define FDATA 0xe5 /* fill data fields during format */
79 79
80 80 /* commands */
81 81
82 82 /* 0x00-0x01 not defined */
83 83 #define RDTRK 0x02
84 84 #define SPECIFY 0x03
85 85 #define SNSDSTAT 0x04
86 86 #define WRTCMD 0x05
87 87 #define RDCMD 0x06
88 88 #define RECALIBRATE 0x07
89 89 #define SNSISTAT 0x08 /* Sense Interrupt Status */
90 90 #define WRTDEL 0x09 /* Write Deleted Data Sector */
91 91 #define RDID 0x0A /* Read Identifier */
92 92 #define MTONOFF 0x0B /* motor on/off */
93 93 #define RDDEL 0x0C /* Read Deleted Data Sector */
94 94 #define FMTTRK 0x0D /* Format Track */
95 95 #define DUMPREG 0x0E /* Dump Registers */
96 96 #define SEEK 0x0F /* Seek */
97 97 /* 0x10-0x12 not defined */
98 98 #define CONFIGURE 0x13
99 99 /* 0x14-0x1F not defined */
100 100
101 101 /* Modifier bits for the command byte */
102 102 #define MT 0x80
103 103 #define MFM 0x40
104 104 #define SK 0x20
105 105 #define MOT 0x80
106 106 #define IPS 0x80 /* Used for South Bridge superI/O */
107 107
108 108
109 109 #define SSSDTL 0xff /* special sector size */
110 110
111 111 #define NCBRW 0x09 /* number cmd bytes for read/write cmds */
112 112 #define NRBRW 0x07 /* number result bytes for read/write cmds */
113 113
114 114 /* results */
115 115 /* status reg0 */
116 116 #define IC_SR0 0xc0 /* interrupt code */
117 117 #define SE_SR0 0x20 /* seek end */
118 118 #define EC_SR0 0x10 /* equipment check */
119 119 #define NR_SR0 0x08 /* not ready */
120 120 #define H_SR0 0x04 /* head address */
121 121 #define DS_SR0 0x03 /* drive select */
122 122
123 123 /* status reg1 */
124 124 #define EN_SR1 0x80 /* end of cylinder */
125 125 #define DE_SR1 0x20 /* data error */
126 126 #define OR_SR1 0x10 /* overrun/underrun */
127 127 #define ND_SR1 0x04 /* no data */
128 128 #define NW_SR1 0x02 /* not writable */
129 129 #define MA_SR1 0x01 /* missing address mark */
130 130 #define TO_SR1 0x08 /* Timeout */
131 131
132 132 /* status reg3 */
133 133 #define WP_SR3 0x40 /* write protected */
134 134 #define T0_SR3 0x10 /* track zero */
135 135
136 136 /* DOR - Digital Output register - 82077 only */
137 137 #define EJECT 0x80 /* eject diskette - was in Auxio */
138 138 #define EJECT_DMA 0x20 /* eject diskette - on DMA platform */
139 139 #define MOTEN(unit) (unit ? 0x30 : 0x10) /* motor enable bit */
140 140 #define DMAGATE 0x8 /* must be high to enable interrupts */
141 141 #define RESET 0x4 /* reset bit */
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142 142 #define DRVSEL 0x1 /* drive select */
143 143
144 144 /* DIR - Digital Input register - 82077 only */
145 145 #define DSKCHG 0x80 /* diskette was changed - was in Auxio */
146 146
147 147 #define DRV_MASK 0x03 /* drive mask for the second command byte */
148 148
149 149 #ifndef _ASM
150 150 #define Moton_delay (drv_usectohz(750000)) /* motor on delay */
151 151 /* 0.75 seconds */
152 -#define Motoff_delay (6 * drv_usectohz(1000000)) /* motor off delay */
152 +#define Motoff_delay drv_sectohz(6) /* motor off delay */
153 153 /* 6 seconds */
154 154
155 155 /* Macros to set and retrieve data from the controller registers */
156 156 #define Msr(fdc) ddi_get8(fdc->c_handlep_cont, \
157 157 ((uint8_t *)fdc->c_control))
158 158 #define Dsr(fdc, val) ddi_put8(fdc->c_handlep_cont, \
159 159 ((uint8_t *)fdc->c_control),\
160 160 ((uint8_t)val))
161 161 #define Dir(fdc) ddi_get8(fdc->c_handlep_cont, \
162 162 ((uint8_t *)fdc->c_dir))
163 163 #define Fifo(fdc) ddi_get8(fdc->c_handlep_cont, \
164 164 ((uint8_t *)fdc->c_fifo))
165 165 #define Set_Fifo(fdc, val) ddi_put8(fdc->c_handlep_cont, \
166 166 ((uint8_t *)fdc->c_fifo), \
167 167 ((uint8_t)val))
168 168 #define Dor(fdc) ddi_get8(fdc->c_handlep_cont, ((uint8_t *)fdc->c_dor))
169 169 #define Set_dor(fdc, val, flag) \
170 170 { if (flag) \
171 171 ddi_put8(fdc->c_handlep_cont, ((uint8_t *)fdc->c_dor), \
172 172 ((uint8_t)(Dor(fdc) | (val)))); \
173 173 else \
174 174 ddi_put8(fdc->c_handlep_cont, ((uint8_t *)fdc->c_dor), \
175 175 ((uint8_t)(Dor(fdc) & ~(val)))); }
176 176 #endif /* !_ASM */
177 177
178 178 /*
179 179 * Auxio Registers
180 180 */
181 181
182 182 /*
183 183 * Definitions and structures for the floppy Auxiliary Input/Output register
184 184 * for the muchio, slavio, and cheerio I/O subsystem chips
185 185 *
186 186 * In general, muchio is found on sun4c, slavio is found on sun4m and sun4u
187 187 * with Sbus. Cheerio is found on sun4u with a PCI bus.
188 188 *
189 189 *
190 190 *
191 191 * 07 06 05 04 03 02 01 00
192 192 * muchio 1 1 DEN CHG SEL TC EJCT LED
193 193 * slavio 1 1 DEN 0 IMUX 0 TC LED
194 194 *
195 195 * The auxio register is designed poorly from a software perspective.
196 196 * a) it supports other functions as well as floppy
197 197 * b) TC is at a different bit position for muchio versus sun4m
198 198 *
199 199 * The cheerio auxio register is only for the floppy and it is a 32 bit
200 200 * register. It does not contain a TC because the cheerio supports
201 201 * floppy DMA. Please note that on the slavio auxio, the Digital
202 202 * Output register of the floppy controller contains a Density Select bit.
203 203 * On the cheerio, this bit is muxed with another
204 204 * signal. So, the cheerio auxio register contains a density select bit.
205 205 *
206 206 * cheerio auxio bit name bit#
207 207 * ------------------------------
208 208 * Floppy density sense 0
209 209 * Floppy desnity select 1
210 210 * Unused 31:1
211 211 *
212 212 */
213 213
214 214 /*
215 215 * muchio/slavio: Bits of the auxio register
216 216 * - when writing to the auxio register, the bits represented by
217 217 * AUX_MBO and AUX_MBO4M must be one
218 218 */
219 219
220 220 #define AUX_MBO 0xF0 /* Must be written with ones */
221 221 #define AUX_MBO4M 0xC0 /* Must be written with ones */
222 222
223 223 #define AUX_TC4M 0x02 /* 4m Floppy termnal count */
224 224 /* 1 = transfer over */
225 225 #define AUX_TC 0x04 /* 4c Floppy terminal count */
226 226 /* 1 = transfer over */
227 227 #define AUX_DENSITY 0x20 /* Floppy density (input value) */
228 228 /* 1 = high, 0 = low */
229 229
230 230
231 231 /*
232 232 * muchio additional floppy auxio bits
233 233 * slavio uses internal dor for these bits
234 234 */
235 235
236 236 #define AUX_DISKCHG 0x10 /* Floppy diskette change (input) */
237 237 /* 1 = new diskette inserted */
238 238 #define AUX_DRVSELECT 0x08 /* Floppy drive select (output) */
239 239 /* 1 = selected, 0 = deselected */
240 240 #define AUX_EJECT 0x02 /* Floppy eject (output,NON inverted) */
241 241 /* 0 = eject the diskette */
242 242 /*
243 243 * cheerio additional floppy auxio bits
244 244 */
245 245
246 246 #define AUX_MEDIUM_DENSITY 0x0 /* Use medium density */
247 247 #define AUX_HIGH_DENSITY 0x2
248 248
249 249 /*
250 250 * macros to set the Cheerio auxio registers.
251 251 */
252 252
253 253 #define Set_auxio(fdc, val) ddi_put32(fdc->c_handlep_aux, \
254 254 ((uint32_t *)fdc->c_auxio_reg), \
255 255 ((uint32_t)(val)))
256 256
257 257 #define Get_auxio(fdc) ddi_get32(fdc->c_handlep_aux, \
258 258 ((uint32_t *)fdc->c_auxio_reg))
259 259
260 260 /*
261 261 * DMA registers (sun4u only)
262 262 */
263 263 #ifndef _ASM
264 264 struct cheerio_dma_reg {
265 265 uint_t fdc_dcsr; /* Data Control Status Register */
266 266 uint_t fdc_dacr; /* DMA Address Count Registers */
267 267 uint_t fdc_dbcr; /* DMA Byte Count Register */
268 268 };
269 269
270 270 #define ISA_REG_LEN 0x500 /* South Bridge dma regs span */
271 271 /* complete 0x500 isa registers. */
272 272
273 273 struct sb_dma_reg {
274 274 uchar_t sb_dma_regs[ISA_REG_LEN];
275 275 };
276 276 struct fdc_dma_reg {
277 277 uchar_t fdc_dma_regs[ISA_REG_LEN]; /* registers from isa config space */
278 278 };
279 279
280 280
281 281 #endif /* !_ASM */
282 282
283 283
284 284
285 285 /*
286 286 * DMA Control and Status Register(DCSR) definitions. See Cheerio spec
287 287 * for more details
288 288 */
289 289 #define DCSR_INT_PEND 0x00000001 /* 1= floppy interrupts */
290 290 #define DCSR_ERR_PEND 0x00000002 /* 1= host bus error detected */
291 291 #define DCSR_INT_EN 0x00000010 /* 1= enable floppy interrupts */
292 292 #define DCSR_RESET 0x00000080 /* 1= resets the DCSR */
293 293 #define DCSR_WRITE 0x00000100 /* DMA direction; 1 = memory */
294 294 #define DCSR_EN_DMA 0x00000200 /* 1= enable DMA */
295 295 #define DCSR_CYC_PEND 0x00000400 /* 1 = DMA pending */
296 296 #define DCSR_EN_CNT 0x00002000 /* 1= enables byte counter */
297 297 #define DCSR_TC 0x00004000 /* 1= Terminal Count occurred */
298 298 #define DCSR_CSR_DRAIN 0x00000000 /* 1= disable draining */
299 299 #define DCSR_BURST_0 0x00080000 /* Burst Size bit 0 */
300 300 #define DCSR_BURST_1 0x00040000 /* Burst Size bit 1 */
301 301 #define DCSR_DIAG 0x00000000 /* 1= diag enable */
302 302 #define DCSR_TCI_DIS 0x00800000 /* 1= TC won't cause interrupt */
303 303 #define DCSR_INIT_BITS DCSR_INT_EN | DCSR_EN_CNT | DCSR_CSR_DRAIN \
304 304 | fd_burstsize \
305 305 | DCSR_TCI_DIS | DCSR_EN_DMA
306 306
307 307 #ifdef __cplusplus
308 308 }
309 309 #endif
310 310
311 311 #endif /* !_SYS_FDREG_H */
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