2053 */
2054 static int
2055 iwp_load_init_firmware(iwp_sc_t *sc)
2056 {
2057 int err = IWP_FAIL;
2058 clock_t clk;
2059
2060 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2061
2062 /*
2063 * load init_text section of uCode to hardware
2064 */
2065 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_init_text.cookie.dmac_address,
2066 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_init_text.cookie.dmac_size);
2067 if (err != IWP_SUCCESS) {
2068 cmn_err(CE_WARN, "iwp_load_init_firmware(): "
2069 "failed to write init uCode.\n");
2070 return (err);
2071 }
2072
2073 clk = ddi_get_lbolt() + drv_usectohz(1000000);
2074
2075 /* wait loading init_text until completed or timeout */
2076 while (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2077 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2078 break;
2079 }
2080 }
2081
2082 if (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2083 cmn_err(CE_WARN, "iwp_load_init_firmware(): "
2084 "timeout waiting for init uCode load.\n");
2085 return (IWP_FAIL);
2086 }
2087
2088 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2089
2090 /*
2091 * load init_data section of uCode to hardware
2092 */
2093 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_init_data.cookie.dmac_address,
2094 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_init_data.cookie.dmac_size);
2095 if (err != IWP_SUCCESS) {
2096 cmn_err(CE_WARN, "iwp_load_init_firmware(): "
2097 "failed to write init_data uCode.\n");
2098 return (err);
2099 }
2100
2101 clk = ddi_get_lbolt() + drv_usectohz(1000000);
2102
2103 /*
2104 * wait loading init_data until completed or timeout
2105 */
2106 while (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2107 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2108 break;
2109 }
2110 }
2111
2112 if (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2113 cmn_err(CE_WARN, "iwp_load_init_firmware(): "
2114 "timeout waiting for init_data uCode load.\n");
2115 return (IWP_FAIL);
2116 }
2117
2118 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2119
2120 return (err);
2121 }
2122
2123 static int
2124 iwp_load_run_firmware(iwp_sc_t *sc)
2125 {
2126 int err = IWP_FAIL;
2127 clock_t clk;
2128
2129 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2130
2131 /*
2132 * load init_text section of uCode to hardware
2133 */
2134 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_text.cookie.dmac_address,
2135 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_text.cookie.dmac_size);
2136 if (err != IWP_SUCCESS) {
2137 cmn_err(CE_WARN, "iwp_load_run_firmware(): "
2138 "failed to write run uCode.\n");
2139 return (err);
2140 }
2141
2142 clk = ddi_get_lbolt() + drv_usectohz(1000000);
2143
2144 /* wait loading run_text until completed or timeout */
2145 while (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2146 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2147 break;
2148 }
2149 }
2150
2151 if (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2152 cmn_err(CE_WARN, "iwp_load_run_firmware(): "
2153 "timeout waiting for run uCode load.\n");
2154 return (IWP_FAIL);
2155 }
2156
2157 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2158
2159 /*
2160 * load run_data section of uCode to hardware
2161 */
2162 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_data_bak.cookie.dmac_address,
2163 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_data.cookie.dmac_size);
2164 if (err != IWP_SUCCESS) {
2165 cmn_err(CE_WARN, "iwp_load_run_firmware(): "
2166 "failed to write run_data uCode.\n");
2167 return (err);
2168 }
2169
2170 clk = ddi_get_lbolt() + drv_usectohz(1000000);
2171
2172 /*
2173 * wait loading run_data until completed or timeout
2174 */
2175 while (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2176 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2177 break;
2178 }
2179 }
2180
2181 if (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2182 cmn_err(CE_WARN, "iwp_load_run_firmware(): "
2183 "timeout waiting for run_data uCode load.\n");
2184 return (IWP_FAIL);
2185 }
2186
2187 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2188
2189 return (err);
2190 }
3680 }
3681 }
3682 }
3683
3684 if (ic->ic_mach &&
3685 (sc->sc_flags & IWP_F_SCANNING) && sc->sc_scan_pending) {
3686 IWP_DBG((IWP_DEBUG_SCAN, "iwp_thread(): "
3687 "wait for probe response\n"));
3688
3689 sc->sc_scan_pending--;
3690 delay(drv_usectohz(200000));
3691 ieee80211_next_scan(ic);
3692 }
3693
3694 /*
3695 * rate ctl
3696 */
3697 if (ic->ic_mach &&
3698 (sc->sc_flags & IWP_F_RATE_AUTO_CTL)) {
3699 clk = ddi_get_lbolt();
3700 if (clk > sc->sc_clk + drv_usectohz(1000000)) {
3701 iwp_amrr_timeout(sc);
3702 }
3703 }
3704
3705 delay(drv_usectohz(100000));
3706
3707 mutex_enter(&sc->sc_mt_lock);
3708 if (sc->sc_tx_timer) {
3709 timeout++;
3710 if (10 == timeout) {
3711 sc->sc_tx_timer--;
3712 if (0 == sc->sc_tx_timer) {
3713 atomic_or_32(&sc->sc_flags,
3714 IWP_F_HW_ERR_RECOVER);
3715 sc->sc_ostate = IEEE80211_S_RUN;
3716 IWP_DBG((IWP_DEBUG_FW, "iwp_thread(): "
3717 "try to recover from "
3718 "send fail\n"));
3719 }
3720 timeout = 0;
4548 * backup ucode data part for future use.
4549 */
4550 (void) memcpy(sc->sc_dma_fw_data_bak.mem_va,
4551 sc->sc_dma_fw_data.mem_va,
4552 sc->sc_dma_fw_data.alength);
4553
4554 /* load firmware init segment into NIC */
4555 err = iwp_load_init_firmware(sc);
4556 if (err != IWP_SUCCESS) {
4557 cmn_err(CE_WARN, "iwp_init(): "
4558 "failed to setup init firmware\n");
4559 mutex_exit(&sc->sc_glock);
4560 return (IWP_FAIL);
4561 }
4562
4563 /*
4564 * now press "execute" start running
4565 */
4566 IWP_WRITE(sc, CSR_RESET, 0);
4567
4568 clk = ddi_get_lbolt() + drv_usectohz(1000000);
4569 while (!(sc->sc_flags & IWP_F_FW_INIT)) {
4570 if (cv_timedwait(&sc->sc_ucode_cv,
4571 &sc->sc_glock, clk) < 0) {
4572 break;
4573 }
4574 }
4575
4576 if (!(sc->sc_flags & IWP_F_FW_INIT)) {
4577 cmn_err(CE_WARN, "iwp_init(): "
4578 "failed to process init alive.\n");
4579 mutex_exit(&sc->sc_glock);
4580 return (IWP_FAIL);
4581 }
4582
4583 mutex_exit(&sc->sc_glock);
4584
4585 /*
4586 * stop chipset for initializing chipset again
4587 */
4588 iwp_stop(sc);
4595 mutex_exit(&sc->sc_glock);
4596 return (IWP_FAIL);
4597 }
4598
4599 /*
4600 * load firmware run segment into NIC
4601 */
4602 err = iwp_load_run_firmware(sc);
4603 if (err != IWP_SUCCESS) {
4604 cmn_err(CE_WARN, "iwp_init(): "
4605 "failed to setup run firmware\n");
4606 mutex_exit(&sc->sc_glock);
4607 return (IWP_FAIL);
4608 }
4609
4610 /*
4611 * now press "execute" start running
4612 */
4613 IWP_WRITE(sc, CSR_RESET, 0);
4614
4615 clk = ddi_get_lbolt() + drv_usectohz(1000000);
4616 while (!(sc->sc_flags & IWP_F_FW_INIT)) {
4617 if (cv_timedwait(&sc->sc_ucode_cv,
4618 &sc->sc_glock, clk) < 0) {
4619 break;
4620 }
4621 }
4622
4623 if (!(sc->sc_flags & IWP_F_FW_INIT)) {
4624 cmn_err(CE_WARN, "iwp_init(): "
4625 "failed to process runtime alive.\n");
4626 mutex_exit(&sc->sc_glock);
4627 return (IWP_FAIL);
4628 }
4629
4630 mutex_exit(&sc->sc_glock);
4631
4632 DELAY(1000);
4633
4634 mutex_enter(&sc->sc_glock);
4635 atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT);
|
2053 */
2054 static int
2055 iwp_load_init_firmware(iwp_sc_t *sc)
2056 {
2057 int err = IWP_FAIL;
2058 clock_t clk;
2059
2060 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2061
2062 /*
2063 * load init_text section of uCode to hardware
2064 */
2065 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_init_text.cookie.dmac_address,
2066 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_init_text.cookie.dmac_size);
2067 if (err != IWP_SUCCESS) {
2068 cmn_err(CE_WARN, "iwp_load_init_firmware(): "
2069 "failed to write init uCode.\n");
2070 return (err);
2071 }
2072
2073 clk = ddi_get_lbolt() + drv_sectohz(1);
2074
2075 /* wait loading init_text until completed or timeout */
2076 while (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2077 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2078 break;
2079 }
2080 }
2081
2082 if (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2083 cmn_err(CE_WARN, "iwp_load_init_firmware(): "
2084 "timeout waiting for init uCode load.\n");
2085 return (IWP_FAIL);
2086 }
2087
2088 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2089
2090 /*
2091 * load init_data section of uCode to hardware
2092 */
2093 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_init_data.cookie.dmac_address,
2094 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_init_data.cookie.dmac_size);
2095 if (err != IWP_SUCCESS) {
2096 cmn_err(CE_WARN, "iwp_load_init_firmware(): "
2097 "failed to write init_data uCode.\n");
2098 return (err);
2099 }
2100
2101 clk = ddi_get_lbolt() + drv_sectohz(1);
2102
2103 /*
2104 * wait loading init_data until completed or timeout
2105 */
2106 while (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2107 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2108 break;
2109 }
2110 }
2111
2112 if (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2113 cmn_err(CE_WARN, "iwp_load_init_firmware(): "
2114 "timeout waiting for init_data uCode load.\n");
2115 return (IWP_FAIL);
2116 }
2117
2118 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2119
2120 return (err);
2121 }
2122
2123 static int
2124 iwp_load_run_firmware(iwp_sc_t *sc)
2125 {
2126 int err = IWP_FAIL;
2127 clock_t clk;
2128
2129 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2130
2131 /*
2132 * load init_text section of uCode to hardware
2133 */
2134 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_text.cookie.dmac_address,
2135 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_text.cookie.dmac_size);
2136 if (err != IWP_SUCCESS) {
2137 cmn_err(CE_WARN, "iwp_load_run_firmware(): "
2138 "failed to write run uCode.\n");
2139 return (err);
2140 }
2141
2142 clk = ddi_get_lbolt() + drv_sectohz(1);
2143
2144 /* wait loading run_text until completed or timeout */
2145 while (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2146 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2147 break;
2148 }
2149 }
2150
2151 if (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2152 cmn_err(CE_WARN, "iwp_load_run_firmware(): "
2153 "timeout waiting for run uCode load.\n");
2154 return (IWP_FAIL);
2155 }
2156
2157 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2158
2159 /*
2160 * load run_data section of uCode to hardware
2161 */
2162 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_data_bak.cookie.dmac_address,
2163 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_data.cookie.dmac_size);
2164 if (err != IWP_SUCCESS) {
2165 cmn_err(CE_WARN, "iwp_load_run_firmware(): "
2166 "failed to write run_data uCode.\n");
2167 return (err);
2168 }
2169
2170 clk = ddi_get_lbolt() + drv_sectohz(1);
2171
2172 /*
2173 * wait loading run_data until completed or timeout
2174 */
2175 while (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2176 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2177 break;
2178 }
2179 }
2180
2181 if (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2182 cmn_err(CE_WARN, "iwp_load_run_firmware(): "
2183 "timeout waiting for run_data uCode load.\n");
2184 return (IWP_FAIL);
2185 }
2186
2187 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2188
2189 return (err);
2190 }
3680 }
3681 }
3682 }
3683
3684 if (ic->ic_mach &&
3685 (sc->sc_flags & IWP_F_SCANNING) && sc->sc_scan_pending) {
3686 IWP_DBG((IWP_DEBUG_SCAN, "iwp_thread(): "
3687 "wait for probe response\n"));
3688
3689 sc->sc_scan_pending--;
3690 delay(drv_usectohz(200000));
3691 ieee80211_next_scan(ic);
3692 }
3693
3694 /*
3695 * rate ctl
3696 */
3697 if (ic->ic_mach &&
3698 (sc->sc_flags & IWP_F_RATE_AUTO_CTL)) {
3699 clk = ddi_get_lbolt();
3700 if (clk > sc->sc_clk + drv_sectohz(1)) {
3701 iwp_amrr_timeout(sc);
3702 }
3703 }
3704
3705 delay(drv_usectohz(100000));
3706
3707 mutex_enter(&sc->sc_mt_lock);
3708 if (sc->sc_tx_timer) {
3709 timeout++;
3710 if (10 == timeout) {
3711 sc->sc_tx_timer--;
3712 if (0 == sc->sc_tx_timer) {
3713 atomic_or_32(&sc->sc_flags,
3714 IWP_F_HW_ERR_RECOVER);
3715 sc->sc_ostate = IEEE80211_S_RUN;
3716 IWP_DBG((IWP_DEBUG_FW, "iwp_thread(): "
3717 "try to recover from "
3718 "send fail\n"));
3719 }
3720 timeout = 0;
4548 * backup ucode data part for future use.
4549 */
4550 (void) memcpy(sc->sc_dma_fw_data_bak.mem_va,
4551 sc->sc_dma_fw_data.mem_va,
4552 sc->sc_dma_fw_data.alength);
4553
4554 /* load firmware init segment into NIC */
4555 err = iwp_load_init_firmware(sc);
4556 if (err != IWP_SUCCESS) {
4557 cmn_err(CE_WARN, "iwp_init(): "
4558 "failed to setup init firmware\n");
4559 mutex_exit(&sc->sc_glock);
4560 return (IWP_FAIL);
4561 }
4562
4563 /*
4564 * now press "execute" start running
4565 */
4566 IWP_WRITE(sc, CSR_RESET, 0);
4567
4568 clk = ddi_get_lbolt() + drv_sectohz(1);
4569 while (!(sc->sc_flags & IWP_F_FW_INIT)) {
4570 if (cv_timedwait(&sc->sc_ucode_cv,
4571 &sc->sc_glock, clk) < 0) {
4572 break;
4573 }
4574 }
4575
4576 if (!(sc->sc_flags & IWP_F_FW_INIT)) {
4577 cmn_err(CE_WARN, "iwp_init(): "
4578 "failed to process init alive.\n");
4579 mutex_exit(&sc->sc_glock);
4580 return (IWP_FAIL);
4581 }
4582
4583 mutex_exit(&sc->sc_glock);
4584
4585 /*
4586 * stop chipset for initializing chipset again
4587 */
4588 iwp_stop(sc);
4595 mutex_exit(&sc->sc_glock);
4596 return (IWP_FAIL);
4597 }
4598
4599 /*
4600 * load firmware run segment into NIC
4601 */
4602 err = iwp_load_run_firmware(sc);
4603 if (err != IWP_SUCCESS) {
4604 cmn_err(CE_WARN, "iwp_init(): "
4605 "failed to setup run firmware\n");
4606 mutex_exit(&sc->sc_glock);
4607 return (IWP_FAIL);
4608 }
4609
4610 /*
4611 * now press "execute" start running
4612 */
4613 IWP_WRITE(sc, CSR_RESET, 0);
4614
4615 clk = ddi_get_lbolt() + drv_sectohz(1);
4616 while (!(sc->sc_flags & IWP_F_FW_INIT)) {
4617 if (cv_timedwait(&sc->sc_ucode_cv,
4618 &sc->sc_glock, clk) < 0) {
4619 break;
4620 }
4621 }
4622
4623 if (!(sc->sc_flags & IWP_F_FW_INIT)) {
4624 cmn_err(CE_WARN, "iwp_init(): "
4625 "failed to process runtime alive.\n");
4626 mutex_exit(&sc->sc_glock);
4627 return (IWP_FAIL);
4628 }
4629
4630 mutex_exit(&sc->sc_glock);
4631
4632 DELAY(1000);
4633
4634 mutex_enter(&sc->sc_glock);
4635 atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT);
|