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XXXX introduce drv_sectohz


  94 
  95         QL_PRINT_3(CE_CONT, "(%d): started, cmd=%xh\n", ha->instance, mbx_cmd);
  96 
  97         /* Acquire mailbox register lock. */
  98         MBX_REGISTER_LOCK(ha);
  99 
 100         /* Check for mailbox available, if not wait for signal. */
 101         while (ha->mailbox_flags & MBX_BUSY_FLG ||
 102             (CFG_IST(ha, CFG_CTRL_8021) &&
 103             RD32_IO_REG(ha, nx_host_int) & NX_MBX_CMD)) {
 104                 ha->mailbox_flags = (uint8_t)
 105                     (ha->mailbox_flags | MBX_WANT_FLG);
 106 
 107                 if (ha->task_daemon_flags & TASK_DAEMON_POWERING_DOWN) {
 108                         EL(vha, "failed availability cmd=%xh\n", mcp->mb[0]);
 109                         MBX_REGISTER_UNLOCK(ha);
 110                         return (QL_LOCK_TIMEOUT);
 111                 }
 112 
 113                 /* Set timeout after command that is running. */
 114                 timer = (mcp->timeout + 20) * drv_usectohz(1000000);
 115                 cv_stat = cv_reltimedwait_sig(&ha->cv_mbx_wait,
 116                     &ha->pha->mbx_mutex, timer, TR_CLOCK_TICK);
 117                 if (cv_stat == -1 || cv_stat == 0) {
 118                         /*
 119                          * The timeout time 'timer' was
 120                          * reached without the condition
 121                          * being signaled.
 122                          */
 123                         ha->mailbox_flags = (uint8_t)(ha->mailbox_flags &
 124                             ~MBX_WANT_FLG);
 125                         cv_broadcast(&ha->cv_mbx_wait);
 126 
 127                         /* Release mailbox register lock. */
 128                         MBX_REGISTER_UNLOCK(ha);
 129 
 130                         if (cv_stat == 0) {
 131                                 EL(vha, "waiting for availability aborted, "
 132                                     "cmd=%xh\n", mcp->mb[0]);
 133                                 return (QL_ABORTED);
 134                         }


 149                         WRT16_IO_REG(ha, mailbox_in[cnt], mcp->mb[cnt]);
 150                 }
 151                 data >>= 1;
 152         }
 153 
 154         /* Issue set host interrupt command. */
 155         ha->mailbox_flags = (uint8_t)(ha->mailbox_flags & ~MBX_INTERRUPT);
 156         if (CFG_IST(ha, CFG_CTRL_8021)) {
 157                 WRT32_IO_REG(ha, nx_host_int, NX_MBX_CMD);
 158         } else if (CFG_IST(ha, CFG_CTRL_242581)) {
 159                 WRT32_IO_REG(ha, hccr, HC24_SET_HOST_INT);
 160         } else {
 161                 WRT16_IO_REG(ha, hccr, HC_SET_HOST_INT);
 162         }
 163 
 164         /* Wait for command to complete. */
 165         if (ha->flags & INTERRUPTS_ENABLED &&
 166             !(ha->task_daemon_flags & (TASK_THREAD_CALLED |
 167             TASK_DAEMON_POWERING_DOWN)) &&
 168             !ddi_in_panic()) {
 169                 timer = mcp->timeout * drv_usectohz(1000000);
 170                 while (!(ha->mailbox_flags & (MBX_INTERRUPT | MBX_ABORT)) &&
 171                     !(ha->task_daemon_flags & ISP_ABORT_NEEDED)) {
 172 
 173                         if (cv_reltimedwait(&ha->cv_mbx_intr,
 174                             &ha->pha->mbx_mutex, timer, TR_CLOCK_TICK) == -1) {
 175                                 /*
 176                                  * The timeout time 'timer' was
 177                                  * reached without the condition
 178                                  * being signaled.
 179                                  */
 180                                 MBX_REGISTER_UNLOCK(ha);
 181                                 while (INTERRUPT_PENDING(ha)) {
 182                                         (void) ql_isr((caddr_t)ha);
 183                                         INTR_LOCK(ha);
 184                                         ha->intr_claimed = B_TRUE;
 185                                         INTR_UNLOCK(ha);
 186                                 }
 187                                 MBX_REGISTER_LOCK(ha);
 188                                 break;
 189                         }




  94 
  95         QL_PRINT_3(CE_CONT, "(%d): started, cmd=%xh\n", ha->instance, mbx_cmd);
  96 
  97         /* Acquire mailbox register lock. */
  98         MBX_REGISTER_LOCK(ha);
  99 
 100         /* Check for mailbox available, if not wait for signal. */
 101         while (ha->mailbox_flags & MBX_BUSY_FLG ||
 102             (CFG_IST(ha, CFG_CTRL_8021) &&
 103             RD32_IO_REG(ha, nx_host_int) & NX_MBX_CMD)) {
 104                 ha->mailbox_flags = (uint8_t)
 105                     (ha->mailbox_flags | MBX_WANT_FLG);
 106 
 107                 if (ha->task_daemon_flags & TASK_DAEMON_POWERING_DOWN) {
 108                         EL(vha, "failed availability cmd=%xh\n", mcp->mb[0]);
 109                         MBX_REGISTER_UNLOCK(ha);
 110                         return (QL_LOCK_TIMEOUT);
 111                 }
 112 
 113                 /* Set timeout after command that is running. */
 114                 timer = drv_sectohz(mcp->timeout + 20);
 115                 cv_stat = cv_reltimedwait_sig(&ha->cv_mbx_wait,
 116                     &ha->pha->mbx_mutex, timer, TR_CLOCK_TICK);
 117                 if (cv_stat == -1 || cv_stat == 0) {
 118                         /*
 119                          * The timeout time 'timer' was
 120                          * reached without the condition
 121                          * being signaled.
 122                          */
 123                         ha->mailbox_flags = (uint8_t)(ha->mailbox_flags &
 124                             ~MBX_WANT_FLG);
 125                         cv_broadcast(&ha->cv_mbx_wait);
 126 
 127                         /* Release mailbox register lock. */
 128                         MBX_REGISTER_UNLOCK(ha);
 129 
 130                         if (cv_stat == 0) {
 131                                 EL(vha, "waiting for availability aborted, "
 132                                     "cmd=%xh\n", mcp->mb[0]);
 133                                 return (QL_ABORTED);
 134                         }


 149                         WRT16_IO_REG(ha, mailbox_in[cnt], mcp->mb[cnt]);
 150                 }
 151                 data >>= 1;
 152         }
 153 
 154         /* Issue set host interrupt command. */
 155         ha->mailbox_flags = (uint8_t)(ha->mailbox_flags & ~MBX_INTERRUPT);
 156         if (CFG_IST(ha, CFG_CTRL_8021)) {
 157                 WRT32_IO_REG(ha, nx_host_int, NX_MBX_CMD);
 158         } else if (CFG_IST(ha, CFG_CTRL_242581)) {
 159                 WRT32_IO_REG(ha, hccr, HC24_SET_HOST_INT);
 160         } else {
 161                 WRT16_IO_REG(ha, hccr, HC_SET_HOST_INT);
 162         }
 163 
 164         /* Wait for command to complete. */
 165         if (ha->flags & INTERRUPTS_ENABLED &&
 166             !(ha->task_daemon_flags & (TASK_THREAD_CALLED |
 167             TASK_DAEMON_POWERING_DOWN)) &&
 168             !ddi_in_panic()) {
 169                 timer = drv_sectohz(mcp->timeout);
 170                 while (!(ha->mailbox_flags & (MBX_INTERRUPT | MBX_ABORT)) &&
 171                     !(ha->task_daemon_flags & ISP_ABORT_NEEDED)) {
 172 
 173                         if (cv_reltimedwait(&ha->cv_mbx_intr,
 174                             &ha->pha->mbx_mutex, timer, TR_CLOCK_TICK) == -1) {
 175                                 /*
 176                                  * The timeout time 'timer' was
 177                                  * reached without the condition
 178                                  * being signaled.
 179                                  */
 180                                 MBX_REGISTER_UNLOCK(ha);
 181                                 while (INTERRUPT_PENDING(ha)) {
 182                                         (void) ql_isr((caddr_t)ha);
 183                                         INTR_LOCK(ha);
 184                                         ha->intr_claimed = B_TRUE;
 185                                         INTR_UNLOCK(ha);
 186                                 }
 187                                 MBX_REGISTER_LOCK(ha);
 188                                 break;
 189                         }