99 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
100 /* 0x00000004 - reserved */
101 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
102 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
103 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
104 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
105 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
106 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
107 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
108 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
109 /* 0x00000800 - reserved */
110 /* 0x00001000 - reserved */
111 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
112 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
113 /* 0x00008000 - reserved */
114 /* 0x00010000 - reserved */
115 /* 0x00020000 - reserved */
116 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
117 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
118 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
119 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
120 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
121 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
122 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
123 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
124 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
125 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
126 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
127 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
128
129 #define FMT_CPUID_INTC_ECX \
130 "\20" \
131 "\37rdrand\36f16c\35avx\34osxsav\33xsave" \
132 "\32aes" \
133 "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca" \
134 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \
135 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
136
137 /*
138 * cpuid instruction feature flags in %edx (extended function 0x80000001)
139 */
140
141 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
142 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
143 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
144 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
145 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
146 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
147 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
148 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
149 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
150 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
151 /* 0x00000400 - sysc on K6m6 */
152 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
153 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
362 #define X86FSET_CMP 20
363 #define X86FSET_TSCP 21
364 #define X86FSET_MWAIT 22
365 #define X86FSET_SSE4A 23
366 #define X86FSET_CPUID 24
367 #define X86FSET_SSSE3 25
368 #define X86FSET_SSE4_1 26
369 #define X86FSET_SSE4_2 27
370 #define X86FSET_1GPG 28
371 #define X86FSET_CLFSH 29
372 #define X86FSET_64 30
373 #define X86FSET_AES 31
374 #define X86FSET_PCLMULQDQ 32
375 #define X86FSET_XSAVE 33
376 #define X86FSET_AVX 34
377 #define X86FSET_VMX 35
378 #define X86FSET_SVM 36
379 #define X86FSET_TOPOEXT 37
380 #define X86FSET_F16C 38
381 #define X86FSET_RDRAND 39
382
383 /*
384 * flags to patch tsc_read routine.
385 */
386 #define X86_NO_TSC 0x0
387 #define X86_HAVE_TSCP 0x1
388 #define X86_TSC_MFENCE 0x2
389 #define X86_TSC_LFENCE 0x4
390
391 /*
392 * Intel Deep C-State invariant TSC in leaf 0x80000007.
393 */
394 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
395
396 /*
397 * Intel Deep C-state always-running local APIC timer
398 */
399 #define CPUID_CSTATE_ARAT (0x4)
400
401 /*
622
623 /*
624 * xgetbv/xsetbv support
625 */
626
627 #define XFEATURE_ENABLED_MASK 0x0
628 /*
629 * XFEATURE_ENABLED_MASK values (eax)
630 */
631 #define XFEATURE_LEGACY_FP 0x1
632 #define XFEATURE_SSE 0x2
633 #define XFEATURE_AVX 0x4
634 #define XFEATURE_MAX XFEATURE_AVX
635 #define XFEATURE_FP_ALL \
636 (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
637
638 #if !defined(_ASM)
639
640 #if defined(_KERNEL) || defined(_KMEMUSER)
641
642 #define NUM_X86_FEATURES 40
643 extern uchar_t x86_featureset[];
644
645 extern void free_x86_featureset(void *featureset);
646 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
647 extern void add_x86_feature(void *featureset, uint_t feature);
648 extern void remove_x86_feature(void *featureset, uint_t feature);
649 extern boolean_t compare_x86_featureset(void *setA, void *setB);
650 extern void print_x86_featureset(void *featureset);
651
652
653 extern uint_t x86_type;
654 extern uint_t x86_vendor;
655 extern uint_t x86_clflush_size;
656
657 extern uint_t pentiumpro_bug4046376;
658
659 extern const char CyrixInstead[];
660
661 #endif
662
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99 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
100 /* 0x00000004 - reserved */
101 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
102 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
103 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
104 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
105 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
106 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
107 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
108 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
109 /* 0x00000800 - reserved */
110 /* 0x00001000 - reserved */
111 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
112 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
113 /* 0x00008000 - reserved */
114 /* 0x00010000 - reserved */
115 /* 0x00020000 - reserved */
116 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
117 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
118 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
119 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
120 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
121 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
122 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
123 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
124 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
125 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
126 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
127 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
128 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
129
130 #define FMT_CPUID_INTC_ECX \
131 "\20" \
132 "\37rdrand\36f16c\35avx\34osxsav\33xsave" \
133 "\32aes" \
134 "\30popcnt\27movbe\26x2apic\25sse4.2\24sse4.1\23dca" \
135 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \
136 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
137
138 /*
139 * cpuid instruction feature flags in %edx (extended function 0x80000001)
140 */
141
142 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
143 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
144 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
145 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
146 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
147 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
148 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
149 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
150 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
151 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
152 /* 0x00000400 - sysc on K6m6 */
153 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
154 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
363 #define X86FSET_CMP 20
364 #define X86FSET_TSCP 21
365 #define X86FSET_MWAIT 22
366 #define X86FSET_SSE4A 23
367 #define X86FSET_CPUID 24
368 #define X86FSET_SSSE3 25
369 #define X86FSET_SSE4_1 26
370 #define X86FSET_SSE4_2 27
371 #define X86FSET_1GPG 28
372 #define X86FSET_CLFSH 29
373 #define X86FSET_64 30
374 #define X86FSET_AES 31
375 #define X86FSET_PCLMULQDQ 32
376 #define X86FSET_XSAVE 33
377 #define X86FSET_AVX 34
378 #define X86FSET_VMX 35
379 #define X86FSET_SVM 36
380 #define X86FSET_TOPOEXT 37
381 #define X86FSET_F16C 38
382 #define X86FSET_RDRAND 39
383 #define X86FSET_X2APIC 40
384
385 /*
386 * flags to patch tsc_read routine.
387 */
388 #define X86_NO_TSC 0x0
389 #define X86_HAVE_TSCP 0x1
390 #define X86_TSC_MFENCE 0x2
391 #define X86_TSC_LFENCE 0x4
392
393 /*
394 * Intel Deep C-State invariant TSC in leaf 0x80000007.
395 */
396 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
397
398 /*
399 * Intel Deep C-state always-running local APIC timer
400 */
401 #define CPUID_CSTATE_ARAT (0x4)
402
403 /*
624
625 /*
626 * xgetbv/xsetbv support
627 */
628
629 #define XFEATURE_ENABLED_MASK 0x0
630 /*
631 * XFEATURE_ENABLED_MASK values (eax)
632 */
633 #define XFEATURE_LEGACY_FP 0x1
634 #define XFEATURE_SSE 0x2
635 #define XFEATURE_AVX 0x4
636 #define XFEATURE_MAX XFEATURE_AVX
637 #define XFEATURE_FP_ALL \
638 (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
639
640 #if !defined(_ASM)
641
642 #if defined(_KERNEL) || defined(_KMEMUSER)
643
644 #define NUM_X86_FEATURES 41
645 extern uchar_t x86_featureset[];
646
647 extern void free_x86_featureset(void *featureset);
648 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
649 extern void add_x86_feature(void *featureset, uint_t feature);
650 extern void remove_x86_feature(void *featureset, uint_t feature);
651 extern boolean_t compare_x86_featureset(void *setA, void *setB);
652 extern void print_x86_featureset(void *featureset);
653
654
655 extern uint_t x86_type;
656 extern uint_t x86_vendor;
657 extern uint_t x86_clflush_size;
658
659 extern uint_t pentiumpro_bug4046376;
660
661 extern const char CyrixInstead[];
662
663 #endif
664
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