1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25 */
26 /*
27 * Copyright (c) 2010, Intel Corporation.
28 * All rights reserved.
29 */
30 /*
31 * Copyright (c) 2012, Joyent, Inc. All rights reserved.
32 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
33 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
34 */
35
36 #ifndef _SYS_X86_ARCHEXT_H
37 #define _SYS_X86_ARCHEXT_H
38
39 #if !defined(_ASM)
40 #include <sys/regset.h>
41 #include <sys/processor.h>
42 #include <vm/seg_enum.h>
43 #include <vm/page.h>
44 #endif /* _ASM */
45
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49
50 /*
51 * cpuid instruction feature flags in %edx (standard function 1)
52 */
53
54 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
55 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
56 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
57 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
58 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
59 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
60 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
61 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
62 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
63 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
64 /* 0x400 - reserved */
65 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
66 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
67 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
68 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
69 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
70 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
71 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
72 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
73 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
74 /* 0x100000 - reserved */
75 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
76 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
77 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
78 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
79 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
80 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
81 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
82 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
83 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
84 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
85 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
86
87 #define FMT_CPUID_INTC_EDX \
88 "\20" \
89 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \
90 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \
91 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \
92 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
93
94 /*
95 * cpuid instruction feature flags in %ecx (standard function 1)
96 */
97
98 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
99 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
100 /* 0x00000004 - reserved */
101 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
102 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
103 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
104 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
105 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
106 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
107 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
108 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
109 /* 0x00000800 - reserved */
110 /* 0x00001000 - reserved */
111 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
112 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
113 /* 0x00008000 - reserved */
114 /* 0x00010000 - reserved */
115 /* 0x00020000 - reserved */
116 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
117 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
118 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
119 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
120 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
121 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
122 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
123 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
124 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
125 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
126 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
127 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
128 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
129
130 #define FMT_CPUID_INTC_ECX \
131 "\20" \
132 "\37rdrand\36f16c\35avx\34osxsav\33xsave" \
133 "\32aes" \
134 "\30popcnt\27movbe\26x2apic\25sse4.2\24sse4.1\23dca" \
135 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \
136 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
137
138 /*
139 * cpuid instruction feature flags in %edx (extended function 0x80000001)
140 */
141
142 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
143 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
144 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
145 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
146 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
147 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
148 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
149 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
150 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
151 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
152 /* 0x00000400 - sysc on K6m6 */
153 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
154 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
155 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
156 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
157 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
158 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
159 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
160 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
161 /* 0x00040000 - reserved */
162 /* 0x00080000 - reserved */
163 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
164 /* 0x00200000 - reserved */
165 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
166 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
167 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
168 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
169 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
170 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
171 /* 0x10000000 - reserved */
172 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
173 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
174 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
175
176 #define FMT_CPUID_AMD_EDX \
177 "\20" \
178 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \
179 "\30mmx\27mmxext\25nx\22pse\21pat" \
180 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \
181 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
182
183 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
184 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
185 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
186 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
187 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
188 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
189 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
190 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
191 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
192 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
193 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
194 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
195 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
196 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
197 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
198
199 #define FMT_CPUID_AMD_ECX \
200 "\20" \
201 "\22topoext" \
202 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \
203 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
204
205 /*
206 * Intel now seems to have claimed part of the "extended" function
207 * space that we previously for non-Intel implementors to use.
208 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
209 * is available in long mode i.e. what AMD indicate using bit 0.
210 * On the other hand, everything else is labelled as reserved.
211 */
212 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
213
214
215 #define P5_MCHADDR 0x0
216 #define P5_CESR 0x11
217 #define P5_CTR0 0x12
218 #define P5_CTR1 0x13
219
220 #define K5_MCHADDR 0x0
221 #define K5_MCHTYPE 0x01
222 #define K5_TSC 0x10
223 #define K5_TR12 0x12
224
225 #define REG_PAT 0x277
226
227 #define REG_MC0_CTL 0x400
228 #define REG_MC5_MISC 0x417
229 #define REG_PERFCTR0 0xc1
230 #define REG_PERFCTR1 0xc2
231
232 #define REG_PERFEVNT0 0x186
233 #define REG_PERFEVNT1 0x187
234
235 #define REG_TSC 0x10 /* timestamp counter */
236 #define REG_APIC_BASE_MSR 0x1b
237 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
238
239 #if !defined(__xpv)
240 /*
241 * AMD C1E
242 */
243 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
244 #define AMD_ACTONCMPHALT_SHIFT 27
245 #define AMD_ACTONCMPHALT_MASK 3
246 #endif
247
248 #define MSR_DEBUGCTL 0x1d9
249
250 #define DEBUGCTL_LBR 0x01
251 #define DEBUGCTL_BTF 0x02
252
253 /* Intel P6, AMD */
254 #define MSR_LBR_FROM 0x1db
255 #define MSR_LBR_TO 0x1dc
256 #define MSR_LEX_FROM 0x1dd
257 #define MSR_LEX_TO 0x1de
258
259 /* Intel P4 (pre-Prescott, non P4 M) */
260 #define MSR_P4_LBSTK_TOS 0x1da
261 #define MSR_P4_LBSTK_0 0x1db
262 #define MSR_P4_LBSTK_1 0x1dc
263 #define MSR_P4_LBSTK_2 0x1dd
264 #define MSR_P4_LBSTK_3 0x1de
265
266 /* Intel Pentium M */
267 #define MSR_P6M_LBSTK_TOS 0x1c9
268 #define MSR_P6M_LBSTK_0 0x040
269 #define MSR_P6M_LBSTK_1 0x041
270 #define MSR_P6M_LBSTK_2 0x042
271 #define MSR_P6M_LBSTK_3 0x043
272 #define MSR_P6M_LBSTK_4 0x044
273 #define MSR_P6M_LBSTK_5 0x045
274 #define MSR_P6M_LBSTK_6 0x046
275 #define MSR_P6M_LBSTK_7 0x047
276
277 /* Intel P4 (Prescott) */
278 #define MSR_PRP4_LBSTK_TOS 0x1da
279 #define MSR_PRP4_LBSTK_FROM_0 0x680
280 #define MSR_PRP4_LBSTK_FROM_1 0x681
281 #define MSR_PRP4_LBSTK_FROM_2 0x682
282 #define MSR_PRP4_LBSTK_FROM_3 0x683
283 #define MSR_PRP4_LBSTK_FROM_4 0x684
284 #define MSR_PRP4_LBSTK_FROM_5 0x685
285 #define MSR_PRP4_LBSTK_FROM_6 0x686
286 #define MSR_PRP4_LBSTK_FROM_7 0x687
287 #define MSR_PRP4_LBSTK_FROM_8 0x688
288 #define MSR_PRP4_LBSTK_FROM_9 0x689
289 #define MSR_PRP4_LBSTK_FROM_10 0x68a
290 #define MSR_PRP4_LBSTK_FROM_11 0x68b
291 #define MSR_PRP4_LBSTK_FROM_12 0x68c
292 #define MSR_PRP4_LBSTK_FROM_13 0x68d
293 #define MSR_PRP4_LBSTK_FROM_14 0x68e
294 #define MSR_PRP4_LBSTK_FROM_15 0x68f
295 #define MSR_PRP4_LBSTK_TO_0 0x6c0
296 #define MSR_PRP4_LBSTK_TO_1 0x6c1
297 #define MSR_PRP4_LBSTK_TO_2 0x6c2
298 #define MSR_PRP4_LBSTK_TO_3 0x6c3
299 #define MSR_PRP4_LBSTK_TO_4 0x6c4
300 #define MSR_PRP4_LBSTK_TO_5 0x6c5
301 #define MSR_PRP4_LBSTK_TO_6 0x6c6
302 #define MSR_PRP4_LBSTK_TO_7 0x6c7
303 #define MSR_PRP4_LBSTK_TO_8 0x6c8
304 #define MSR_PRP4_LBSTK_TO_9 0x6c9
305 #define MSR_PRP4_LBSTK_TO_10 0x6ca
306 #define MSR_PRP4_LBSTK_TO_11 0x6cb
307 #define MSR_PRP4_LBSTK_TO_12 0x6cc
308 #define MSR_PRP4_LBSTK_TO_13 0x6cd
309 #define MSR_PRP4_LBSTK_TO_14 0x6ce
310 #define MSR_PRP4_LBSTK_TO_15 0x6cf
311
312 #define MCI_CTL_VALUE 0xffffffff
313
314 #define MTRR_TYPE_UC 0
315 #define MTRR_TYPE_WC 1
316 #define MTRR_TYPE_WT 4
317 #define MTRR_TYPE_WP 5
318 #define MTRR_TYPE_WB 6
319 #define MTRR_TYPE_UC_ 7
320
321 /*
322 * For Solaris we set up the page attritubute table in the following way:
323 * PAT0 Write-Back
324 * PAT1 Write-Through
325 * PAT2 Unchacheable-
326 * PAT3 Uncacheable
327 * PAT4 Write-Back
328 * PAT5 Write-Through
329 * PAT6 Write-Combine
330 * PAT7 Uncacheable
331 * The only difference from h/w default is entry 6.
332 */
333 #define PAT_DEFAULT_ATTRIBUTE \
334 ((uint64_t)MTRR_TYPE_WB | \
335 ((uint64_t)MTRR_TYPE_WT << 8) | \
336 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
337 ((uint64_t)MTRR_TYPE_UC << 24) | \
338 ((uint64_t)MTRR_TYPE_WB << 32) | \
339 ((uint64_t)MTRR_TYPE_WT << 40) | \
340 ((uint64_t)MTRR_TYPE_WC << 48) | \
341 ((uint64_t)MTRR_TYPE_UC << 56))
342
343 #define X86FSET_LARGEPAGE 0
344 #define X86FSET_TSC 1
345 #define X86FSET_MSR 2
346 #define X86FSET_MTRR 3
347 #define X86FSET_PGE 4
348 #define X86FSET_DE 5
349 #define X86FSET_CMOV 6
350 #define X86FSET_MMX 7
351 #define X86FSET_MCA 8
352 #define X86FSET_PAE 9
353 #define X86FSET_CX8 10
354 #define X86FSET_PAT 11
355 #define X86FSET_SEP 12
356 #define X86FSET_SSE 13
357 #define X86FSET_SSE2 14
358 #define X86FSET_HTT 15
359 #define X86FSET_ASYSC 16
360 #define X86FSET_NX 17
361 #define X86FSET_SSE3 18
362 #define X86FSET_CX16 19
363 #define X86FSET_CMP 20
364 #define X86FSET_TSCP 21
365 #define X86FSET_MWAIT 22
366 #define X86FSET_SSE4A 23
367 #define X86FSET_CPUID 24
368 #define X86FSET_SSSE3 25
369 #define X86FSET_SSE4_1 26
370 #define X86FSET_SSE4_2 27
371 #define X86FSET_1GPG 28
372 #define X86FSET_CLFSH 29
373 #define X86FSET_64 30
374 #define X86FSET_AES 31
375 #define X86FSET_PCLMULQDQ 32
376 #define X86FSET_XSAVE 33
377 #define X86FSET_AVX 34
378 #define X86FSET_VMX 35
379 #define X86FSET_SVM 36
380 #define X86FSET_TOPOEXT 37
381 #define X86FSET_F16C 38
382 #define X86FSET_RDRAND 39
383 #define X86FSET_X2APIC 40
384
385 /*
386 * flags to patch tsc_read routine.
387 */
388 #define X86_NO_TSC 0x0
389 #define X86_HAVE_TSCP 0x1
390 #define X86_TSC_MFENCE 0x2
391 #define X86_TSC_LFENCE 0x4
392
393 /*
394 * Intel Deep C-State invariant TSC in leaf 0x80000007.
395 */
396 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
397
398 /*
399 * Intel Deep C-state always-running local APIC timer
400 */
401 #define CPUID_CSTATE_ARAT (0x4)
402
403 /*
404 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
405 */
406 #define CPUID_EPB_SUPPORT (1 << 3)
407
408 /*
409 * Intel TSC deadline timer
410 */
411 #define CPUID_DEADLINE_TSC (1 << 24)
412
413 /*
414 * x86_type is a legacy concept; this is supplanted
415 * for most purposes by x86_featureset; modern CPUs
416 * should be X86_TYPE_OTHER
417 */
418 #define X86_TYPE_OTHER 0
419 #define X86_TYPE_486 1
420 #define X86_TYPE_P5 2
421 #define X86_TYPE_P6 3
422 #define X86_TYPE_CYRIX_486 4
423 #define X86_TYPE_CYRIX_6x86L 5
424 #define X86_TYPE_CYRIX_6x86 6
425 #define X86_TYPE_CYRIX_GXm 7
426 #define X86_TYPE_CYRIX_6x86MX 8
427 #define X86_TYPE_CYRIX_MediaGX 9
428 #define X86_TYPE_CYRIX_MII 10
429 #define X86_TYPE_VIA_CYRIX_III 11
430 #define X86_TYPE_P4 12
431
432 /*
433 * x86_vendor allows us to select between
434 * implementation features and helps guide
435 * the interpretation of the cpuid instruction.
436 */
437 #define X86_VENDOR_Intel 0
438 #define X86_VENDORSTR_Intel "GenuineIntel"
439
440 #define X86_VENDOR_IntelClone 1
441
442 #define X86_VENDOR_AMD 2
443 #define X86_VENDORSTR_AMD "AuthenticAMD"
444
445 #define X86_VENDOR_Cyrix 3
446 #define X86_VENDORSTR_CYRIX "CyrixInstead"
447
448 #define X86_VENDOR_UMC 4
449 #define X86_VENDORSTR_UMC "UMC UMC UMC "
450
451 #define X86_VENDOR_NexGen 5
452 #define X86_VENDORSTR_NexGen "NexGenDriven"
453
454 #define X86_VENDOR_Centaur 6
455 #define X86_VENDORSTR_Centaur "CentaurHauls"
456
457 #define X86_VENDOR_Rise 7
458 #define X86_VENDORSTR_Rise "RiseRiseRise"
459
460 #define X86_VENDOR_SiS 8
461 #define X86_VENDORSTR_SiS "SiS SiS SiS "
462
463 #define X86_VENDOR_TM 9
464 #define X86_VENDORSTR_TM "GenuineTMx86"
465
466 #define X86_VENDOR_NSC 10
467 #define X86_VENDORSTR_NSC "Geode by NSC"
468
469 /*
470 * Vendor string max len + \0
471 */
472 #define X86_VENDOR_STRLEN 13
473
474 /*
475 * Some vendor/family/model/stepping ranges are commonly grouped under
476 * a single identifying banner by the vendor. The following encode
477 * that "revision" in a uint32_t with the 8 most significant bits
478 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
479 * family, and the remaining 16 typically forming a bitmask of revisions
480 * within that family with more significant bits indicating "later" revisions.
481 */
482
483 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
484 #define _X86_CHIPREV_VENDOR_SHIFT 24
485 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
486 #define _X86_CHIPREV_FAMILY_SHIFT 16
487 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
488
489 #define _X86_CHIPREV_VENDOR(x) \
490 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
491 #define _X86_CHIPREV_FAMILY(x) \
492 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
493 #define _X86_CHIPREV_REV(x) \
494 ((x) & _X86_CHIPREV_REV_MASK)
495
496 /* True if x matches in vendor and family and if x matches the given rev mask */
497 #define X86_CHIPREV_MATCH(x, mask) \
498 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
499 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
500 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
501
502 /* True if x matches in vendor and family, and rev is at least minx */
503 #define X86_CHIPREV_ATLEAST(x, minx) \
504 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
505 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
506 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
507
508 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
509 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
510 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
511
512 /* True if x matches in vendor, and family is at least minx */
513 #define X86_CHIPFAM_ATLEAST(x, minx) \
514 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
515 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
516
517 /* Revision default */
518 #define X86_CHIPREV_UNKNOWN 0x0
519
520 /*
521 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
522 * sufficiently different that we will distinguish them; in all other
523 * case we will identify the major revision.
524 */
525 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
526 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
527 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
528 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
529 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
530 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
531 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
532
533 /*
534 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
535 */
536 #define X86_CHIPREV_AMD_10_REV_A \
537 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
538 #define X86_CHIPREV_AMD_10_REV_B \
539 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
540 #define X86_CHIPREV_AMD_10_REV_C2 \
541 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
542 #define X86_CHIPREV_AMD_10_REV_C3 \
543 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
544 #define X86_CHIPREV_AMD_10_REV_D0 \
545 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
546 #define X86_CHIPREV_AMD_10_REV_D1 \
547 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
548 #define X86_CHIPREV_AMD_10_REV_E \
549 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
550
551 /*
552 * Definitions for AMD Family 0x11.
553 */
554 #define X86_CHIPREV_AMD_11_REV_B \
555 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
556
557 /*
558 * Definitions for AMD Family 0x12.
559 */
560 #define X86_CHIPREV_AMD_12_REV_B \
561 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
562
563 /*
564 * Definitions for AMD Family 0x14.
565 */
566 #define X86_CHIPREV_AMD_14_REV_B \
567 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
568 #define X86_CHIPREV_AMD_14_REV_C \
569 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
570
571 /*
572 * Definitions for AMD Family 0x15
573 */
574 #define X86_CHIPREV_AMD_15OR_REV_B2 \
575 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
576
577 #define X86_CHIPREV_AMD_15TN_REV_A1 \
578 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
579
580 /*
581 * Various socket/package types, extended as the need to distinguish
582 * a new type arises. The top 8 byte identfies the vendor and the
583 * remaining 24 bits describe 24 socket types.
584 */
585
586 #define _X86_SOCKET_VENDOR_SHIFT 24
587 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
588 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
589 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
590
591 #define _X86_SOCKET_MKVAL(vendor, bitval) \
592 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
593
594 #define X86_SOCKET_MATCH(s, mask) \
595 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
596 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
597
598 #define X86_SOCKET_UNKNOWN 0x0
599 /*
600 * AMD socket types
601 */
602 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
603 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
604 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
605 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
606 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
607 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
608 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
609 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
610 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
611 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
612 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
613 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
614 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
615 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
616 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000)
617 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000)
618 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000)
619 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000)
620 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000)
621 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000)
622 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000)
623 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000)
624
625 /*
626 * xgetbv/xsetbv support
627 */
628
629 #define XFEATURE_ENABLED_MASK 0x0
630 /*
631 * XFEATURE_ENABLED_MASK values (eax)
632 */
633 #define XFEATURE_LEGACY_FP 0x1
634 #define XFEATURE_SSE 0x2
635 #define XFEATURE_AVX 0x4
636 #define XFEATURE_MAX XFEATURE_AVX
637 #define XFEATURE_FP_ALL \
638 (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
639
640 #if !defined(_ASM)
641
642 #if defined(_KERNEL) || defined(_KMEMUSER)
643
644 #define NUM_X86_FEATURES 41
645 extern uchar_t x86_featureset[];
646
647 extern void free_x86_featureset(void *featureset);
648 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
649 extern void add_x86_feature(void *featureset, uint_t feature);
650 extern void remove_x86_feature(void *featureset, uint_t feature);
651 extern boolean_t compare_x86_featureset(void *setA, void *setB);
652 extern void print_x86_featureset(void *featureset);
653
654
655 extern uint_t x86_type;
656 extern uint_t x86_vendor;
657 extern uint_t x86_clflush_size;
658
659 extern uint_t pentiumpro_bug4046376;
660
661 extern const char CyrixInstead[];
662
663 #endif
664
665 #if defined(_KERNEL)
666
667 /*
668 * This structure is used to pass arguments and get return values back
669 * from the CPUID instruction in __cpuid_insn() routine.
670 */
671 struct cpuid_regs {
672 uint32_t cp_eax;
673 uint32_t cp_ebx;
674 uint32_t cp_ecx;
675 uint32_t cp_edx;
676 };
677
678 /*
679 * Utility functions to get/set extended control registers (XCR)
680 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
681 */
682 extern uint64_t get_xcr(uint_t);
683 extern void set_xcr(uint_t, uint64_t);
684
685 extern uint64_t rdmsr(uint_t);
686 extern void wrmsr(uint_t, const uint64_t);
687 extern uint64_t xrdmsr(uint_t);
688 extern void xwrmsr(uint_t, const uint64_t);
689 extern int checked_rdmsr(uint_t, uint64_t *);
690 extern int checked_wrmsr(uint_t, uint64_t);
691
692 extern void invalidate_cache(void);
693 extern ulong_t getcr4(void);
694 extern void setcr4(ulong_t);
695
696 extern void mtrr_sync(void);
697
698 extern void cpu_fast_syscall_enable(void *);
699 extern void cpu_fast_syscall_disable(void *);
700
701 struct cpu;
702
703 extern int cpuid_checkpass(struct cpu *, int);
704 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
705 extern uint32_t __cpuid_insn(struct cpuid_regs *);
706 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
707 extern int cpuid_getidstr(struct cpu *, char *, size_t);
708 extern const char *cpuid_getvendorstr(struct cpu *);
709 extern uint_t cpuid_getvendor(struct cpu *);
710 extern uint_t cpuid_getfamily(struct cpu *);
711 extern uint_t cpuid_getmodel(struct cpu *);
712 extern uint_t cpuid_getstep(struct cpu *);
713 extern uint_t cpuid_getsig(struct cpu *);
714 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
715 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
716 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
717 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
718 extern int cpuid_get_chipid(struct cpu *);
719 extern id_t cpuid_get_coreid(struct cpu *);
720 extern int cpuid_get_pkgcoreid(struct cpu *);
721 extern int cpuid_get_clogid(struct cpu *);
722 extern int cpuid_get_cacheid(struct cpu *);
723 extern uint32_t cpuid_get_apicid(struct cpu *);
724 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
725 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
726 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
727 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
728 extern int cpuid_is_cmt(struct cpu *);
729 extern int cpuid_syscall32_insn(struct cpu *);
730 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
731
732 extern uint32_t cpuid_getchiprev(struct cpu *);
733 extern const char *cpuid_getchiprevstr(struct cpu *);
734 extern uint32_t cpuid_getsockettype(struct cpu *);
735 extern const char *cpuid_getsocketstr(struct cpu *);
736
737 extern int cpuid_have_cr8access(struct cpu *);
738
739 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
740
741 struct cpuid_info;
742
743 extern void setx86isalist(void);
744 extern void cpuid_alloc_space(struct cpu *);
745 extern void cpuid_free_space(struct cpu *);
746 extern void cpuid_pass1(struct cpu *, uchar_t *);
747 extern void cpuid_pass2(struct cpu *);
748 extern void cpuid_pass3(struct cpu *);
749 extern void cpuid_pass4(struct cpu *, uint_t *);
750 extern void cpuid_set_cpu_properties(void *, processorid_t,
751 struct cpuid_info *);
752
753 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
754 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
755
756 #if !defined(__xpv)
757 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
758 extern void cpuid_mwait_free(struct cpu *);
759 extern int cpuid_deep_cstates_supported(void);
760 extern int cpuid_arat_supported(void);
761 extern int cpuid_iepb_supported(struct cpu *);
762 extern int cpuid_deadline_tsc_supported(void);
763 extern void vmware_port(int, uint32_t *);
764 #endif
765
766 struct cpu_ucode_info;
767
768 extern void ucode_alloc_space(struct cpu *);
769 extern void ucode_free_space(struct cpu *);
770 extern void ucode_check(struct cpu *);
771 extern void ucode_cleanup();
772
773 #if !defined(__xpv)
774 extern char _tsc_mfence_start;
775 extern char _tsc_mfence_end;
776 extern char _tscp_start;
777 extern char _tscp_end;
778 extern char _no_rdtsc_start;
779 extern char _no_rdtsc_end;
780 extern char _tsc_lfence_start;
781 extern char _tsc_lfence_end;
782 #endif
783
784 #if !defined(__xpv)
785 extern char bcopy_patch_start;
786 extern char bcopy_patch_end;
787 extern char bcopy_ck_size;
788 #endif
789
790 extern void post_startup_cpu_fixups(void);
791
792 extern uint_t workaround_errata(struct cpu *);
793
794 #if defined(OPTERON_ERRATUM_93)
795 extern int opteron_erratum_93;
796 #endif
797
798 #if defined(OPTERON_ERRATUM_91)
799 extern int opteron_erratum_91;
800 #endif
801
802 #if defined(OPTERON_ERRATUM_100)
803 extern int opteron_erratum_100;
804 #endif
805
806 #if defined(OPTERON_ERRATUM_121)
807 extern int opteron_erratum_121;
808 #endif
809
810 #if defined(OPTERON_WORKAROUND_6323525)
811 extern int opteron_workaround_6323525;
812 extern void patch_workaround_6323525(void);
813 #endif
814
815 #if !defined(__xpv)
816 extern void determine_platform(void);
817 #endif
818 extern int get_hwenv(void);
819 extern int is_controldom(void);
820
821 extern void xsave_setup_msr(struct cpu *);
822
823 /*
824 * Hypervisor signatures
825 */
826 #define HVSIG_XEN_HVM "XenVMMXenVMM"
827 #define HVSIG_VMWARE "VMwareVMware"
828 #define HVSIG_KVM "KVMKVMKVM"
829 #define HVSIG_MICROSOFT "Microsoft Hv"
830
831 /*
832 * Defined hardware environments
833 */
834 #define HW_NATIVE (1 << 0) /* Running on bare metal */
835 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */
836
837 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */
838 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */
839 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */
840 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */
841
842 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT)
843
844 #endif /* _KERNEL */
845
846 #endif /* !_ASM */
847
848 /*
849 * VMware hypervisor related defines
850 */
851 #define VMWARE_HVMAGIC 0x564d5868
852 #define VMWARE_HVPORT 0x5658
853 #define VMWARE_HVCMD_GETVERSION 0x0a
854 #define VMWARE_HVCMD_GETTSCFREQ 0x2d
855
856 #ifdef __cplusplus
857 }
858 #endif
859
860 #endif /* _SYS_X86_ARCHEXT_H */