1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
27 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */
28 /* All Rights Reserved */
29 /* */
30 /* Copyright (c) 1987, 1988 Microsoft Corporation */
31 /* All Rights Reserved */
32 /* */
33
34 /*
35 * Copyright 2012 Joyent, Inc. All rights reserved.
36 */
37
38 #include <sys/types.h>
39 #include <sys/sysmacros.h>
40 #include <sys/param.h>
41 #include <sys/signal.h>
42 #include <sys/systm.h>
43 #include <sys/user.h>
44 #include <sys/proc.h>
45 #include <sys/disp.h>
46 #include <sys/class.h>
47 #include <sys/core.h>
48 #include <sys/syscall.h>
49 #include <sys/cpuvar.h>
50 #include <sys/vm.h>
51 #include <sys/sysinfo.h>
52 #include <sys/fault.h>
53 #include <sys/stack.h>
54 #include <sys/psw.h>
55 #include <sys/regset.h>
56 #include <sys/fp.h>
57 #include <sys/trap.h>
58 #include <sys/kmem.h>
59 #include <sys/vtrace.h>
60 #include <sys/cmn_err.h>
61 #include <sys/prsystm.h>
62 #include <sys/mutex_impl.h>
63 #include <sys/machsystm.h>
64 #include <sys/archsystm.h>
65 #include <sys/sdt.h>
66 #include <sys/avintr.h>
67 #include <sys/kobj.h>
68
69 #include <vm/hat.h>
70
71 #include <vm/seg_kmem.h>
72 #include <vm/as.h>
73 #include <vm/seg.h>
74 #include <vm/hat_pte.h>
75 #include <vm/hat_i86.h>
76
77 #include <sys/procfs.h>
78
79 #include <sys/reboot.h>
80 #include <sys/debug.h>
81 #include <sys/debugreg.h>
82 #include <sys/modctl.h>
83 #include <sys/aio_impl.h>
84 #include <sys/tnf.h>
85 #include <sys/tnf_probe.h>
86 #include <sys/cred.h>
87 #include <sys/mman.h>
88 #include <sys/x86_archext.h>
89 #include <sys/copyops.h>
90 #include <c2/audit.h>
91 #include <sys/ftrace.h>
92 #include <sys/panic.h>
93 #include <sys/traptrace.h>
94 #include <sys/ontrap.h>
95 #include <sys/cpc_impl.h>
96 #include <sys/bootconf.h>
97 #include <sys/bootinfo.h>
98 #include <sys/promif.h>
99 #include <sys/mach_mmu.h>
100 #if defined(__xpv)
101 #include <sys/hypervisor.h>
102 #endif
103 #include <sys/contract/process_impl.h>
104
105 #define USER 0x10000 /* user-mode flag added to trap type */
106
107 static const char *trap_type_mnemonic[] = {
108 "de", "db", "2", "bp",
109 "of", "br", "ud", "nm",
110 "df", "9", "ts", "np",
111 "ss", "gp", "pf", "15",
112 "mf", "ac", "mc", "xf"
113 };
114
115 static const char *trap_type[] = {
116 "Divide error", /* trap id 0 */
117 "Debug", /* trap id 1 */
118 "NMI interrupt", /* trap id 2 */
119 "Breakpoint", /* trap id 3 */
120 "Overflow", /* trap id 4 */
121 "BOUND range exceeded", /* trap id 5 */
122 "Invalid opcode", /* trap id 6 */
123 "Device not available", /* trap id 7 */
124 "Double fault", /* trap id 8 */
125 "Coprocessor segment overrun", /* trap id 9 */
126 "Invalid TSS", /* trap id 10 */
127 "Segment not present", /* trap id 11 */
128 "Stack segment fault", /* trap id 12 */
129 "General protection", /* trap id 13 */
130 "Page fault", /* trap id 14 */
131 "Reserved", /* trap id 15 */
132 "x87 floating point error", /* trap id 16 */
133 "Alignment check", /* trap id 17 */
134 "Machine check", /* trap id 18 */
135 "SIMD floating point exception", /* trap id 19 */
136 };
137
138 #define TRAP_TYPES (sizeof (trap_type) / sizeof (trap_type[0]))
139
140 #define SLOW_SCALL_SIZE 2
141 #define FAST_SCALL_SIZE 2
142
143 int tudebug = 0;
144 int tudebugbpt = 0;
145 int tudebugfpe = 0;
146 int tudebugsse = 0;
147
148 #if defined(TRAPDEBUG) || defined(lint)
149 int tdebug = 0;
150 int lodebug = 0;
151 int faultdebug = 0;
152 #else
153 #define tdebug 0
154 #define lodebug 0
155 #define faultdebug 0
156 #endif /* defined(TRAPDEBUG) || defined(lint) */
157
158 #if defined(TRAPTRACE)
159 /*
160 * trap trace record for cpu0 is allocated here.
161 * trap trace records for non-boot cpus are allocated in mp_startup_init().
162 */
163 static trap_trace_rec_t trap_tr0[TRAPTR_NENT];
164 trap_trace_ctl_t trap_trace_ctl[NCPU] = {
165 {
166 (uintptr_t)trap_tr0, /* next record */
167 (uintptr_t)trap_tr0, /* first record */
168 (uintptr_t)(trap_tr0 + TRAPTR_NENT), /* limit */
169 (uintptr_t)0 /* current */
170 },
171 };
172
173 /*
174 * default trap buffer size
175 */
176 size_t trap_trace_bufsize = TRAPTR_NENT * sizeof (trap_trace_rec_t);
177 int trap_trace_freeze = 0;
178 int trap_trace_off = 0;
179
180 /*
181 * A dummy TRAPTRACE entry to use after death.
182 */
183 trap_trace_rec_t trap_trace_postmort;
184
185 static void dump_ttrace(void);
186 #endif /* TRAPTRACE */
187 static void dumpregs(struct regs *);
188 static void showregs(uint_t, struct regs *, caddr_t);
189 static int kern_gpfault(struct regs *);
190
191 /*ARGSUSED*/
192 static int
193 die(uint_t type, struct regs *rp, caddr_t addr, processorid_t cpuid)
194 {
195 struct panic_trap_info ti;
196 const char *trap_name, *trap_mnemonic;
197
198 if (type < TRAP_TYPES) {
199 trap_name = trap_type[type];
200 trap_mnemonic = trap_type_mnemonic[type];
201 } else {
202 trap_name = "trap";
203 trap_mnemonic = "-";
204 }
205
206 #ifdef TRAPTRACE
207 TRAPTRACE_FREEZE;
208 #endif
209
210 ti.trap_regs = rp;
211 ti.trap_type = type & ~USER;
212 ti.trap_addr = addr;
213
214 curthread->t_panic_trap = &ti;
215
216 if (type == T_PGFLT && addr < (caddr_t)KERNELBASE) {
217 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p "
218 "occurred in module \"%s\" due to %s",
219 type, trap_mnemonic, trap_name, (void *)rp, (void *)addr,
220 mod_containing_pc((caddr_t)rp->r_pc),
221 addr < (caddr_t)PAGESIZE ?
222 "a NULL pointer dereference" :
223 "an illegal access to a user address");
224 } else
225 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p",
226 type, trap_mnemonic, trap_name, (void *)rp, (void *)addr);
227 return (0);
228 }
229
230 /*
231 * Rewrite the instruction at pc to be an int $T_SYSCALLINT instruction.
232 *
233 * int <vector> is two bytes: 0xCD <vector>
234 */
235
236 static int
237 rewrite_syscall(caddr_t pc)
238 {
239 uchar_t instr[SLOW_SCALL_SIZE] = { 0xCD, T_SYSCALLINT };
240
241 if (uwrite(curthread->t_procp, instr, SLOW_SCALL_SIZE,
242 (uintptr_t)pc) != 0)
243 return (1);
244
245 return (0);
246 }
247
248 /*
249 * Test to see if the instruction at pc is sysenter or syscall. The second
250 * argument should be the x86 feature flag corresponding to the expected
251 * instruction.
252 *
253 * sysenter is two bytes: 0x0F 0x34
254 * syscall is two bytes: 0x0F 0x05
255 * int $T_SYSCALLINT is two bytes: 0xCD 0x91
256 */
257
258 static int
259 instr_is_other_syscall(caddr_t pc, int which)
260 {
261 uchar_t instr[FAST_SCALL_SIZE];
262
263 ASSERT(which == X86FSET_SEP || which == X86FSET_ASYSC || which == 0xCD);
264
265 if (copyin_nowatch(pc, (caddr_t)instr, FAST_SCALL_SIZE) != 0)
266 return (0);
267
268 switch (which) {
269 case X86FSET_SEP:
270 if (instr[0] == 0x0F && instr[1] == 0x34)
271 return (1);
272 break;
273 case X86FSET_ASYSC:
274 if (instr[0] == 0x0F && instr[1] == 0x05)
275 return (1);
276 break;
277 case 0xCD:
278 if (instr[0] == 0xCD && instr[1] == T_SYSCALLINT)
279 return (1);
280 break;
281 }
282
283 return (0);
284 }
285
286 static const char *
287 syscall_insn_string(int syscall_insn)
288 {
289 switch (syscall_insn) {
290 case X86FSET_SEP:
291 return ("sysenter");
292 case X86FSET_ASYSC:
293 return ("syscall");
294 case 0xCD:
295 return ("int");
296 default:
297 return ("Unknown");
298 }
299 }
300
301 static int
302 ldt_rewrite_syscall(struct regs *rp, proc_t *p, int syscall_insn)
303 {
304 caddr_t linearpc;
305 int return_code = 0;
306
307 mutex_enter(&p->p_ldtlock); /* Must be held across linear_pc() */
308
309 if (linear_pc(rp, p, &linearpc) == 0) {
310
311 /*
312 * If another thread beat us here, it already changed
313 * this site to the slower (int) syscall instruction.
314 */
315 if (instr_is_other_syscall(linearpc, 0xCD)) {
316 return_code = 1;
317 } else if (instr_is_other_syscall(linearpc, syscall_insn)) {
318
319 if (rewrite_syscall(linearpc) == 0) {
320 return_code = 1;
321 }
322 #ifdef DEBUG
323 else
324 cmn_err(CE_WARN, "failed to rewrite %s "
325 "instruction in process %d",
326 syscall_insn_string(syscall_insn),
327 p->p_pid);
328 #endif /* DEBUG */
329 }
330 }
331
332 mutex_exit(&p->p_ldtlock); /* Must be held across linear_pc() */
333
334 return (return_code);
335 }
336
337 /*
338 * Test to see if the instruction at pc is a system call instruction.
339 *
340 * The bytes of an lcall instruction used for the syscall trap.
341 * static uchar_t lcall[7] = { 0x9a, 0, 0, 0, 0, 0x7, 0 };
342 * static uchar_t lcallalt[7] = { 0x9a, 0, 0, 0, 0, 0x27, 0 };
343 */
344
345 #define LCALLSIZE 7
346
347 static int
348 instr_is_lcall_syscall(caddr_t pc)
349 {
350 uchar_t instr[LCALLSIZE];
351
352 if (copyin_nowatch(pc, (caddr_t)instr, LCALLSIZE) == 0 &&
353 instr[0] == 0x9a &&
354 instr[1] == 0 &&
355 instr[2] == 0 &&
356 instr[3] == 0 &&
357 instr[4] == 0 &&
358 (instr[5] == 0x7 || instr[5] == 0x27) &&
359 instr[6] == 0)
360 return (1);
361
362 return (0);
363 }
364
365 #ifdef __amd64
366
367 /*
368 * In the first revisions of amd64 CPUs produced by AMD, the LAHF and
369 * SAHF instructions were not implemented in 64-bit mode. Later revisions
370 * did implement these instructions. An extension to the cpuid instruction
371 * was added to check for the capability of executing these instructions
372 * in 64-bit mode.
373 *
374 * Intel originally did not implement these instructions in EM64T either,
375 * but added them in later revisions.
376 *
377 * So, there are different chip revisions by both vendors out there that
378 * may or may not implement these instructions. The easy solution is to
379 * just always emulate these instructions on demand.
380 *
381 * SAHF == store %ah in the lower 8 bits of %rflags (opcode 0x9e)
382 * LAHF == load the lower 8 bits of %rflags into %ah (opcode 0x9f)
383 */
384
385 #define LSAHFSIZE 1
386
387 static int
388 instr_is_lsahf(caddr_t pc, uchar_t *instr)
389 {
390 if (copyin_nowatch(pc, (caddr_t)instr, LSAHFSIZE) == 0 &&
391 (*instr == 0x9e || *instr == 0x9f))
392 return (1);
393 return (0);
394 }
395
396 /*
397 * Emulate the LAHF and SAHF instructions. The reference manuals define
398 * these instructions to always load/store bit 1 as a 1, and bits 3 and 5
399 * as a 0. The other, defined, bits are copied (the PS_ICC bits and PS_P).
400 *
401 * Note that %ah is bits 8-15 of %rax.
402 */
403 static void
404 emulate_lsahf(struct regs *rp, uchar_t instr)
405 {
406 if (instr == 0x9e) {
407 /* sahf. Copy bits from %ah to flags. */
408 rp->r_ps = (rp->r_ps & ~0xff) |
409 ((rp->r_rax >> 8) & PSL_LSAHFMASK) | PS_MB1;
410 } else {
411 /* lahf. Copy bits from flags to %ah. */
412 rp->r_rax = (rp->r_rax & ~0xff00) |
413 (((rp->r_ps & PSL_LSAHFMASK) | PS_MB1) << 8);
414 }
415 rp->r_pc += LSAHFSIZE;
416 }
417 #endif /* __amd64 */
418
419 #ifdef OPTERON_ERRATUM_91
420
421 /*
422 * Test to see if the instruction at pc is a prefetch instruction.
423 *
424 * The first byte of prefetch instructions is always 0x0F.
425 * The second byte is 0x18 for regular prefetch or 0x0D for AMD 3dnow prefetch.
426 * The third byte (ModRM) contains the register field bits (bits 3-5).
427 * These bits must be between 0 and 3 inclusive for regular prefetch and
428 * 0 and 1 inclusive for AMD 3dnow prefetch.
429 *
430 * In 64-bit mode, there may be a one-byte REX prefex (0x40-0x4F).
431 */
432
433 static int
434 cmp_to_prefetch(uchar_t *p)
435 {
436 #ifdef _LP64
437 if ((p[0] & 0xF0) == 0x40) /* 64-bit REX prefix */
438 p++;
439 #endif
440 return ((p[0] == 0x0F && p[1] == 0x18 && ((p[2] >> 3) & 7) <= 3) ||
441 (p[0] == 0x0F && p[1] == 0x0D && ((p[2] >> 3) & 7) <= 1));
442 }
443
444 static int
445 instr_is_prefetch(caddr_t pc)
446 {
447 uchar_t instr[4]; /* optional REX prefix plus 3-byte opcode */
448
449 return (copyin_nowatch(pc, instr, sizeof (instr)) == 0 &&
450 cmp_to_prefetch(instr));
451 }
452
453 #endif /* OPTERON_ERRATUM_91 */
454
455 /*
456 * Called from the trap handler when a processor trap occurs.
457 *
458 * Note: All user-level traps that might call stop() must exit
459 * trap() by 'goto out' or by falling through.
460 * Note Also: trap() is usually called with interrupts enabled, (PS_IE == 1)
461 * however, there are paths that arrive here with PS_IE == 0 so special care
462 * must be taken in those cases.
463 */
464 void
465 trap(struct regs *rp, caddr_t addr, processorid_t cpuid)
466 {
467 kthread_t *ct = curthread;
468 enum seg_rw rw;
469 unsigned type;
470 proc_t *p = ttoproc(ct);
471 klwp_t *lwp = ttolwp(ct);
472 uintptr_t lofault;
473 label_t *onfault;
474 faultcode_t pagefault(), res, errcode;
475 enum fault_type fault_type;
476 k_siginfo_t siginfo;
477 uint_t fault = 0;
478 int mstate;
479 int sicode = 0;
480 int watchcode;
481 int watchpage;
482 caddr_t vaddr;
483 int singlestep_twiddle;
484 size_t sz;
485 int ta;
486 #ifdef __amd64
487 uchar_t instr;
488 #endif
489
490 ASSERT_STACK_ALIGNED();
491
492 type = rp->r_trapno;
493 CPU_STATS_ADDQ(CPU, sys, trap, 1);
494 ASSERT(ct->t_schedflag & TS_DONT_SWAP);
495
496 if (type == T_PGFLT) {
497
498 errcode = rp->r_err;
499 if (errcode & PF_ERR_WRITE)
500 rw = S_WRITE;
501 else if ((caddr_t)rp->r_pc == addr ||
502 (mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC)))
503 rw = S_EXEC;
504 else
505 rw = S_READ;
506
507 #if defined(__i386)
508 /*
509 * Pentium Pro work-around
510 */
511 if ((errcode & PF_ERR_PROT) && pentiumpro_bug4046376) {
512 uint_t attr;
513 uint_t priv_violation;
514 uint_t access_violation;
515
516 if (hat_getattr(addr < (caddr_t)kernelbase ?
517 curproc->p_as->a_hat : kas.a_hat, addr, &attr)
518 == -1) {
519 errcode &= ~PF_ERR_PROT;
520 } else {
521 priv_violation = (errcode & PF_ERR_USER) &&
522 !(attr & PROT_USER);
523 access_violation = (errcode & PF_ERR_WRITE) &&
524 !(attr & PROT_WRITE);
525 if (!priv_violation && !access_violation)
526 goto cleanup;
527 }
528 }
529 #endif /* __i386 */
530
531 } else if (type == T_SGLSTP && lwp != NULL)
532 lwp->lwp_pcb.pcb_drstat = (uintptr_t)addr;
533
534 if (tdebug)
535 showregs(type, rp, addr);
536
537 if (USERMODE(rp->r_cs)) {
538 /*
539 * Set up the current cred to use during this trap. u_cred
540 * no longer exists. t_cred is used instead.
541 * The current process credential applies to the thread for
542 * the entire trap. If trapping from the kernel, this
543 * should already be set up.
544 */
545 if (ct->t_cred != p->p_cred) {
546 cred_t *oldcred = ct->t_cred;
547 /*
548 * DTrace accesses t_cred in probe context. t_cred
549 * must always be either NULL, or point to a valid,
550 * allocated cred structure.
551 */
552 ct->t_cred = crgetcred();
553 crfree(oldcred);
554 }
555 ASSERT(lwp != NULL);
556 type |= USER;
557 ASSERT(lwptoregs(lwp) == rp);
558 lwp->lwp_state = LWP_SYS;
559
560 switch (type) {
561 case T_PGFLT + USER:
562 if ((caddr_t)rp->r_pc == addr)
563 mstate = LMS_TFAULT;
564 else
565 mstate = LMS_DFAULT;
566 break;
567 default:
568 mstate = LMS_TRAP;
569 break;
570 }
571 /* Kernel probe */
572 TNF_PROBE_1(thread_state, "thread", /* CSTYLED */,
573 tnf_microstate, state, mstate);
574 mstate = new_mstate(ct, mstate);
575
576 bzero(&siginfo, sizeof (siginfo));
577 }
578
579 switch (type) {
580 case T_PGFLT + USER:
581 case T_SGLSTP:
582 case T_SGLSTP + USER:
583 case T_BPTFLT + USER:
584 break;
585
586 default:
587 FTRACE_2("trap(): type=0x%lx, regs=0x%lx",
588 (ulong_t)type, (ulong_t)rp);
589 break;
590 }
591
592 switch (type) {
593 case T_SIMDFPE:
594 /* Make sure we enable interrupts before die()ing */
595 sti(); /* The SIMD exception comes in via cmninttrap */
596 /*FALLTHROUGH*/
597 default:
598 if (type & USER) {
599 if (tudebug)
600 showregs(type, rp, (caddr_t)0);
601 printf("trap: Unknown trap type %d in user mode\n",
602 type & ~USER);
603 siginfo.si_signo = SIGILL;
604 siginfo.si_code = ILL_ILLTRP;
605 siginfo.si_addr = (caddr_t)rp->r_pc;
606 siginfo.si_trapno = type & ~USER;
607 fault = FLTILL;
608 break;
609 } else {
610 (void) die(type, rp, addr, cpuid);
611 /*NOTREACHED*/
612 }
613
614 case T_PGFLT: /* system page fault */
615 /*
616 * If we're under on_trap() protection (see <sys/ontrap.h>),
617 * set ot_trap and bounce back to the on_trap() call site
618 * via the installed trampoline.
619 */
620 if ((ct->t_ontrap != NULL) &&
621 (ct->t_ontrap->ot_prot & OT_DATA_ACCESS)) {
622 ct->t_ontrap->ot_trap |= OT_DATA_ACCESS;
623 rp->r_pc = ct->t_ontrap->ot_trampoline;
624 goto cleanup;
625 }
626
627 /*
628 * If we have an Instruction fault in kernel mode, then that
629 * means we've tried to execute a user page (SMEP) or both of
630 * PAE and NXE are enabled. In either case, given that it's a
631 * kernel fault, we should panic immediately and not try to make
632 * any more forward progress. This indicates a bug in the
633 * kernel, which if execution continued, could be exploited to
634 * wreak havoc on the system.
635 */
636 if (errcode & PF_ERR_EXEC) {
637 (void) die(type, rp, addr, cpuid);
638 }
639
640 /*
641 * See if we can handle as pagefault. Save lofault and onfault
642 * across this. Here we assume that an address less than
643 * KERNELBASE is a user fault. We can do this as copy.s
644 * routines verify that the starting address is less than
645 * KERNELBASE before starting and because we know that we
646 * always have KERNELBASE mapped as invalid to serve as a
647 * "barrier".
648 */
649 lofault = ct->t_lofault;
650 onfault = ct->t_onfault;
651 ct->t_lofault = 0;
652
653 mstate = new_mstate(ct, LMS_KFAULT);
654
655 if (addr < (caddr_t)kernelbase) {
656 res = pagefault(addr,
657 (errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 0);
658 if (res == FC_NOMAP &&
659 addr < p->p_usrstack &&
660 grow(addr))
661 res = 0;
662 } else {
663 res = pagefault(addr,
664 (errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 1);
665 }
666 (void) new_mstate(ct, mstate);
667
668 /*
669 * Restore lofault and onfault. If we resolved the fault, exit.
670 * If we didn't and lofault wasn't set, die.
671 */
672 ct->t_lofault = lofault;
673 ct->t_onfault = onfault;
674 if (res == 0)
675 goto cleanup;
676
677 #if defined(OPTERON_ERRATUM_93) && defined(_LP64)
678 if (lofault == 0 && opteron_erratum_93) {
679 /*
680 * Workaround for Opteron Erratum 93. On return from
681 * a System Managment Interrupt at a HLT instruction
682 * the %rip might be truncated to a 32 bit value.
683 * BIOS is supposed to fix this, but some don't.
684 * If this occurs we simply restore the high order bits.
685 * The HLT instruction is 1 byte of 0xf4.
686 */
687 uintptr_t rip = rp->r_pc;
688
689 if ((rip & 0xfffffffful) == rip) {
690 rip |= 0xfffffffful << 32;
691 if (hat_getpfnum(kas.a_hat, (caddr_t)rip) !=
692 PFN_INVALID &&
693 (*(uchar_t *)rip == 0xf4 ||
694 *(uchar_t *)(rip - 1) == 0xf4)) {
695 rp->r_pc = rip;
696 goto cleanup;
697 }
698 }
699 }
700 #endif /* OPTERON_ERRATUM_93 && _LP64 */
701
702 #ifdef OPTERON_ERRATUM_91
703 if (lofault == 0 && opteron_erratum_91) {
704 /*
705 * Workaround for Opteron Erratum 91. Prefetches may
706 * generate a page fault (they're not supposed to do
707 * that!). If this occurs we simply return back to the
708 * instruction.
709 */
710 caddr_t pc = (caddr_t)rp->r_pc;
711
712 /*
713 * If the faulting PC is not mapped, this is a
714 * legitimate kernel page fault that must result in a
715 * panic. If the faulting PC is mapped, it could contain
716 * a prefetch instruction. Check for that here.
717 */
718 if (hat_getpfnum(kas.a_hat, pc) != PFN_INVALID) {
719 if (cmp_to_prefetch((uchar_t *)pc)) {
720 #ifdef DEBUG
721 cmn_err(CE_WARN, "Opteron erratum 91 "
722 "occurred: kernel prefetch"
723 " at %p generated a page fault!",
724 (void *)rp->r_pc);
725 #endif /* DEBUG */
726 goto cleanup;
727 }
728 }
729 (void) die(type, rp, addr, cpuid);
730 }
731 #endif /* OPTERON_ERRATUM_91 */
732
733 if (lofault == 0)
734 (void) die(type, rp, addr, cpuid);
735
736 /*
737 * Cannot resolve fault. Return to lofault.
738 */
739 if (lodebug) {
740 showregs(type, rp, addr);
741 traceregs(rp);
742 }
743 if (FC_CODE(res) == FC_OBJERR)
744 res = FC_ERRNO(res);
745 else
746 res = EFAULT;
747 rp->r_r0 = res;
748 rp->r_pc = ct->t_lofault;
749 goto cleanup;
750
751 case T_PGFLT + USER: /* user page fault */
752 if (faultdebug) {
753 char *fault_str;
754
755 switch (rw) {
756 case S_READ:
757 fault_str = "read";
758 break;
759 case S_WRITE:
760 fault_str = "write";
761 break;
762 case S_EXEC:
763 fault_str = "exec";
764 break;
765 default:
766 fault_str = "";
767 break;
768 }
769 printf("user %s fault: addr=0x%lx errcode=0x%x\n",
770 fault_str, (uintptr_t)addr, errcode);
771 }
772
773 #if defined(OPTERON_ERRATUM_100) && defined(_LP64)
774 /*
775 * Workaround for AMD erratum 100
776 *
777 * A 32-bit process may receive a page fault on a non
778 * 32-bit address by mistake. The range of the faulting
779 * address will be
780 *
781 * 0xffffffff80000000 .. 0xffffffffffffffff or
782 * 0x0000000100000000 .. 0x000000017fffffff
783 *
784 * The fault is always due to an instruction fetch, however
785 * the value of r_pc should be correct (in 32 bit range),
786 * so we ignore the page fault on the bogus address.
787 */
788 if (p->p_model == DATAMODEL_ILP32 &&
789 (0xffffffff80000000 <= (uintptr_t)addr ||
790 (0x100000000 <= (uintptr_t)addr &&
791 (uintptr_t)addr <= 0x17fffffff))) {
792 if (!opteron_erratum_100)
793 panic("unexpected erratum #100");
794 if (rp->r_pc <= 0xffffffff)
795 goto out;
796 }
797 #endif /* OPTERON_ERRATUM_100 && _LP64 */
798
799 ASSERT(!(curthread->t_flag & T_WATCHPT));
800 watchpage = (pr_watch_active(p) && pr_is_watchpage(addr, rw));
801 #ifdef __i386
802 /*
803 * In 32-bit mode, the lcall (system call) instruction fetches
804 * one word from the stack, at the stack pointer, because of the
805 * way the call gate is constructed. This is a bogus
806 * read and should not be counted as a read watchpoint.
807 * We work around the problem here by testing to see if
808 * this situation applies and, if so, simply jumping to
809 * the code in locore.s that fields the system call trap.
810 * The registers on the stack are already set up properly
811 * due to the match between the call gate sequence and the
812 * trap gate sequence. We just have to adjust the pc.
813 */
814 if (watchpage && addr == (caddr_t)rp->r_sp &&
815 rw == S_READ && instr_is_lcall_syscall((caddr_t)rp->r_pc)) {
816 extern void watch_syscall(void);
817
818 rp->r_pc += LCALLSIZE;
819 watch_syscall(); /* never returns */
820 /* NOTREACHED */
821 }
822 #endif /* __i386 */
823 vaddr = addr;
824 if (!watchpage || (sz = instr_size(rp, &vaddr, rw)) <= 0)
825 fault_type = (errcode & PF_ERR_PROT)? F_PROT: F_INVAL;
826 else if ((watchcode = pr_is_watchpoint(&vaddr, &ta,
827 sz, NULL, rw)) != 0) {
828 if (ta) {
829 do_watch_step(vaddr, sz, rw,
830 watchcode, rp->r_pc);
831 fault_type = F_INVAL;
832 } else {
833 bzero(&siginfo, sizeof (siginfo));
834 siginfo.si_signo = SIGTRAP;
835 siginfo.si_code = watchcode;
836 siginfo.si_addr = vaddr;
837 siginfo.si_trapafter = 0;
838 siginfo.si_pc = (caddr_t)rp->r_pc;
839 fault = FLTWATCH;
840 break;
841 }
842 } else {
843 /* XXX pr_watch_emul() never succeeds (for now) */
844 if (rw != S_EXEC && pr_watch_emul(rp, vaddr, rw))
845 goto out;
846 do_watch_step(vaddr, sz, rw, 0, 0);
847 fault_type = F_INVAL;
848 }
849
850 res = pagefault(addr, fault_type, rw, 0);
851
852 /*
853 * If pagefault() succeeded, ok.
854 * Otherwise attempt to grow the stack.
855 */
856 if (res == 0 ||
857 (res == FC_NOMAP &&
858 addr < p->p_usrstack &&
859 grow(addr))) {
860 lwp->lwp_lastfault = FLTPAGE;
861 lwp->lwp_lastfaddr = addr;
862 if (prismember(&p->p_fltmask, FLTPAGE)) {
863 bzero(&siginfo, sizeof (siginfo));
864 siginfo.si_addr = addr;
865 (void) stop_on_fault(FLTPAGE, &siginfo);
866 }
867 goto out;
868 } else if (res == FC_PROT && addr < p->p_usrstack &&
869 (mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC))) {
870 report_stack_exec(p, addr);
871 }
872
873 #ifdef OPTERON_ERRATUM_91
874 /*
875 * Workaround for Opteron Erratum 91. Prefetches may generate a
876 * page fault (they're not supposed to do that!). If this
877 * occurs we simply return back to the instruction.
878 *
879 * We rely on copyin to properly fault in the page with r_pc.
880 */
881 if (opteron_erratum_91 &&
882 addr != (caddr_t)rp->r_pc &&
883 instr_is_prefetch((caddr_t)rp->r_pc)) {
884 #ifdef DEBUG
885 cmn_err(CE_WARN, "Opteron erratum 91 occurred: "
886 "prefetch at %p in pid %d generated a trap!",
887 (void *)rp->r_pc, p->p_pid);
888 #endif /* DEBUG */
889 goto out;
890 }
891 #endif /* OPTERON_ERRATUM_91 */
892
893 if (tudebug)
894 showregs(type, rp, addr);
895 /*
896 * In the case where both pagefault and grow fail,
897 * set the code to the value provided by pagefault.
898 * We map all errors returned from pagefault() to SIGSEGV.
899 */
900 bzero(&siginfo, sizeof (siginfo));
901 siginfo.si_addr = addr;
902 switch (FC_CODE(res)) {
903 case FC_HWERR:
904 case FC_NOSUPPORT:
905 siginfo.si_signo = SIGBUS;
906 siginfo.si_code = BUS_ADRERR;
907 fault = FLTACCESS;
908 break;
909 case FC_ALIGN:
910 siginfo.si_signo = SIGBUS;
911 siginfo.si_code = BUS_ADRALN;
912 fault = FLTACCESS;
913 break;
914 case FC_OBJERR:
915 if ((siginfo.si_errno = FC_ERRNO(res)) != EINTR) {
916 siginfo.si_signo = SIGBUS;
917 siginfo.si_code = BUS_OBJERR;
918 fault = FLTACCESS;
919 }
920 break;
921 default: /* FC_NOMAP or FC_PROT */
922 siginfo.si_signo = SIGSEGV;
923 siginfo.si_code =
924 (res == FC_NOMAP)? SEGV_MAPERR : SEGV_ACCERR;
925 fault = FLTBOUNDS;
926 break;
927 }
928 break;
929
930 case T_ILLINST + USER: /* invalid opcode fault */
931 /*
932 * If the syscall instruction is disabled due to LDT usage, a
933 * user program that attempts to execute it will trigger a #ud
934 * trap. Check for that case here. If this occurs on a CPU which
935 * doesn't even support syscall, the result of all of this will
936 * be to emulate that particular instruction.
937 */
938 if (p->p_ldt != NULL &&
939 ldt_rewrite_syscall(rp, p, X86FSET_ASYSC))
940 goto out;
941
942 #ifdef __amd64
943 /*
944 * Emulate the LAHF and SAHF instructions if needed.
945 * See the instr_is_lsahf function for details.
946 */
947 if (p->p_model == DATAMODEL_LP64 &&
948 instr_is_lsahf((caddr_t)rp->r_pc, &instr)) {
949 emulate_lsahf(rp, instr);
950 goto out;
951 }
952 #endif
953
954 /*FALLTHROUGH*/
955
956 if (tudebug)
957 showregs(type, rp, (caddr_t)0);
958 siginfo.si_signo = SIGILL;
959 siginfo.si_code = ILL_ILLOPC;
960 siginfo.si_addr = (caddr_t)rp->r_pc;
961 fault = FLTILL;
962 break;
963
964 case T_ZERODIV + USER: /* integer divide by zero */
965 if (tudebug && tudebugfpe)
966 showregs(type, rp, (caddr_t)0);
967 siginfo.si_signo = SIGFPE;
968 siginfo.si_code = FPE_INTDIV;
969 siginfo.si_addr = (caddr_t)rp->r_pc;
970 fault = FLTIZDIV;
971 break;
972
973 case T_OVFLW + USER: /* integer overflow */
974 if (tudebug && tudebugfpe)
975 showregs(type, rp, (caddr_t)0);
976 siginfo.si_signo = SIGFPE;
977 siginfo.si_code = FPE_INTOVF;
978 siginfo.si_addr = (caddr_t)rp->r_pc;
979 fault = FLTIOVF;
980 break;
981
982 case T_NOEXTFLT + USER: /* math coprocessor not available */
983 if (tudebug && tudebugfpe)
984 showregs(type, rp, addr);
985 if (fpnoextflt(rp)) {
986 siginfo.si_signo = SIGILL;
987 siginfo.si_code = ILL_ILLOPC;
988 siginfo.si_addr = (caddr_t)rp->r_pc;
989 fault = FLTILL;
990 }
991 break;
992
993 case T_EXTOVRFLT: /* extension overrun fault */
994 /* check if we took a kernel trap on behalf of user */
995 {
996 extern void ndptrap_frstor(void);
997 if (rp->r_pc != (uintptr_t)ndptrap_frstor) {
998 sti(); /* T_EXTOVRFLT comes in via cmninttrap */
999 (void) die(type, rp, addr, cpuid);
1000 }
1001 type |= USER;
1002 }
1003 /*FALLTHROUGH*/
1004 case T_EXTOVRFLT + USER: /* extension overrun fault */
1005 if (tudebug && tudebugfpe)
1006 showregs(type, rp, addr);
1007 if (fpextovrflt(rp)) {
1008 siginfo.si_signo = SIGSEGV;
1009 siginfo.si_code = SEGV_MAPERR;
1010 siginfo.si_addr = (caddr_t)rp->r_pc;
1011 fault = FLTBOUNDS;
1012 }
1013 break;
1014
1015 case T_EXTERRFLT: /* x87 floating point exception pending */
1016 /* check if we took a kernel trap on behalf of user */
1017 {
1018 extern void ndptrap_frstor(void);
1019 if (rp->r_pc != (uintptr_t)ndptrap_frstor) {
1020 sti(); /* T_EXTERRFLT comes in via cmninttrap */
1021 (void) die(type, rp, addr, cpuid);
1022 }
1023 type |= USER;
1024 }
1025 /*FALLTHROUGH*/
1026
1027 case T_EXTERRFLT + USER: /* x87 floating point exception pending */
1028 if (tudebug && tudebugfpe)
1029 showregs(type, rp, addr);
1030 if (sicode = fpexterrflt(rp)) {
1031 siginfo.si_signo = SIGFPE;
1032 siginfo.si_code = sicode;
1033 siginfo.si_addr = (caddr_t)rp->r_pc;
1034 fault = FLTFPE;
1035 }
1036 break;
1037
1038 case T_SIMDFPE + USER: /* SSE and SSE2 exceptions */
1039 if (tudebug && tudebugsse)
1040 showregs(type, rp, addr);
1041 if (!is_x86_feature(x86_featureset, X86FSET_SSE) &&
1042 !is_x86_feature(x86_featureset, X86FSET_SSE2)) {
1043 /*
1044 * There are rumours that some user instructions
1045 * on older CPUs can cause this trap to occur; in
1046 * which case send a SIGILL instead of a SIGFPE.
1047 */
1048 siginfo.si_signo = SIGILL;
1049 siginfo.si_code = ILL_ILLTRP;
1050 siginfo.si_addr = (caddr_t)rp->r_pc;
1051 siginfo.si_trapno = type & ~USER;
1052 fault = FLTILL;
1053 } else if ((sicode = fpsimderrflt(rp)) != 0) {
1054 siginfo.si_signo = SIGFPE;
1055 siginfo.si_code = sicode;
1056 siginfo.si_addr = (caddr_t)rp->r_pc;
1057 fault = FLTFPE;
1058 }
1059
1060 sti(); /* The SIMD exception comes in via cmninttrap */
1061 break;
1062
1063 case T_BPTFLT: /* breakpoint trap */
1064 /*
1065 * Kernel breakpoint traps should only happen when kmdb is
1066 * active, and even then, it'll have interposed on the IDT, so
1067 * control won't get here. If it does, we've hit a breakpoint
1068 * without the debugger, which is very strange, and very
1069 * fatal.
1070 */
1071 if (tudebug && tudebugbpt)
1072 showregs(type, rp, (caddr_t)0);
1073
1074 (void) die(type, rp, addr, cpuid);
1075 break;
1076
1077 case T_SGLSTP: /* single step/hw breakpoint exception */
1078
1079 /* Now evaluate how we got here */
1080 if (lwp != NULL && (lwp->lwp_pcb.pcb_drstat & DR_SINGLESTEP)) {
1081 /*
1082 * i386 single-steps even through lcalls which
1083 * change the privilege level. So we take a trap at
1084 * the first instruction in privileged mode.
1085 *
1086 * Set a flag to indicate that upon completion of
1087 * the system call, deal with the single-step trap.
1088 *
1089 * The same thing happens for sysenter, too.
1090 */
1091 singlestep_twiddle = 0;
1092 if (rp->r_pc == (uintptr_t)sys_sysenter ||
1093 rp->r_pc == (uintptr_t)brand_sys_sysenter) {
1094 singlestep_twiddle = 1;
1095 #if defined(__amd64)
1096 /*
1097 * Since we are already on the kernel's
1098 * %gs, on 64-bit systems the sysenter case
1099 * needs to adjust the pc to avoid
1100 * executing the swapgs instruction at the
1101 * top of the handler.
1102 */
1103 if (rp->r_pc == (uintptr_t)sys_sysenter)
1104 rp->r_pc = (uintptr_t)
1105 _sys_sysenter_post_swapgs;
1106 else
1107 rp->r_pc = (uintptr_t)
1108 _brand_sys_sysenter_post_swapgs;
1109 #endif
1110 }
1111 #if defined(__i386)
1112 else if (rp->r_pc == (uintptr_t)sys_call ||
1113 rp->r_pc == (uintptr_t)brand_sys_call) {
1114 singlestep_twiddle = 1;
1115 }
1116 #endif
1117 else {
1118 /* not on sysenter/syscall; uregs available */
1119 if (tudebug && tudebugbpt)
1120 showregs(type, rp, (caddr_t)0);
1121 }
1122 if (singlestep_twiddle) {
1123 rp->r_ps &= ~PS_T; /* turn off trace */
1124 lwp->lwp_pcb.pcb_flags |= DEBUG_PENDING;
1125 ct->t_post_sys = 1;
1126 aston(curthread);
1127 goto cleanup;
1128 }
1129 }
1130 /* XXX - needs review on debugger interface? */
1131 if (boothowto & RB_DEBUG)
1132 debug_enter((char *)NULL);
1133 else
1134 (void) die(type, rp, addr, cpuid);
1135 break;
1136
1137 case T_NMIFLT: /* NMI interrupt */
1138 printf("Unexpected NMI in system mode\n");
1139 goto cleanup;
1140
1141 case T_NMIFLT + USER: /* NMI interrupt */
1142 printf("Unexpected NMI in user mode\n");
1143 break;
1144
1145 case T_GPFLT: /* general protection violation */
1146 /*
1147 * Any #GP that occurs during an on_trap .. no_trap bracket
1148 * with OT_DATA_ACCESS or OT_SEGMENT_ACCESS protection,
1149 * or in a on_fault .. no_fault bracket, is forgiven
1150 * and we trampoline. This protection is given regardless
1151 * of whether we are 32/64 bit etc - if a distinction is
1152 * required then define new on_trap protection types.
1153 *
1154 * On amd64, we can get a #gp from referencing addresses
1155 * in the virtual address hole e.g. from a copyin or in
1156 * update_sregs while updating user segment registers.
1157 *
1158 * On the 32-bit hypervisor we could also generate one in
1159 * mfn_to_pfn by reaching around or into where the hypervisor
1160 * lives which is protected by segmentation.
1161 */
1162
1163 /*
1164 * If we're under on_trap() protection (see <sys/ontrap.h>),
1165 * set ot_trap and trampoline back to the on_trap() call site
1166 * for OT_DATA_ACCESS or OT_SEGMENT_ACCESS.
1167 */
1168 if (ct->t_ontrap != NULL) {
1169 int ttype = ct->t_ontrap->ot_prot &
1170 (OT_DATA_ACCESS | OT_SEGMENT_ACCESS);
1171
1172 if (ttype != 0) {
1173 ct->t_ontrap->ot_trap |= ttype;
1174 if (tudebug)
1175 showregs(type, rp, (caddr_t)0);
1176 rp->r_pc = ct->t_ontrap->ot_trampoline;
1177 goto cleanup;
1178 }
1179 }
1180
1181 /*
1182 * If we're under lofault protection (copyin etc.),
1183 * longjmp back to lofault with an EFAULT.
1184 */
1185 if (ct->t_lofault) {
1186 /*
1187 * Fault is not resolvable, so just return to lofault
1188 */
1189 if (lodebug) {
1190 showregs(type, rp, addr);
1191 traceregs(rp);
1192 }
1193 rp->r_r0 = EFAULT;
1194 rp->r_pc = ct->t_lofault;
1195 goto cleanup;
1196 }
1197
1198 /*
1199 * We fall through to the next case, which repeats
1200 * the OT_SEGMENT_ACCESS check which we've already
1201 * done, so we'll always fall through to the
1202 * T_STKFLT case.
1203 */
1204 /*FALLTHROUGH*/
1205 case T_SEGFLT: /* segment not present fault */
1206 /*
1207 * One example of this is #NP in update_sregs while
1208 * attempting to update a user segment register
1209 * that points to a descriptor that is marked not
1210 * present.
1211 */
1212 if (ct->t_ontrap != NULL &&
1213 ct->t_ontrap->ot_prot & OT_SEGMENT_ACCESS) {
1214 ct->t_ontrap->ot_trap |= OT_SEGMENT_ACCESS;
1215 if (tudebug)
1216 showregs(type, rp, (caddr_t)0);
1217 rp->r_pc = ct->t_ontrap->ot_trampoline;
1218 goto cleanup;
1219 }
1220 /*FALLTHROUGH*/
1221 case T_STKFLT: /* stack fault */
1222 case T_TSSFLT: /* invalid TSS fault */
1223 if (tudebug)
1224 showregs(type, rp, (caddr_t)0);
1225 if (kern_gpfault(rp))
1226 (void) die(type, rp, addr, cpuid);
1227 goto cleanup;
1228
1229 /*
1230 * ONLY 32-bit PROCESSES can USE a PRIVATE LDT! 64-bit apps
1231 * should have no need for them, so we put a stop to it here.
1232 *
1233 * So: not-present fault is ONLY valid for 32-bit processes with
1234 * a private LDT trying to do a system call. Emulate it.
1235 *
1236 * #gp fault is ONLY valid for 32-bit processes also, which DO NOT
1237 * have a private LDT, and are trying to do a system call. Emulate it.
1238 */
1239
1240 case T_SEGFLT + USER: /* segment not present fault */
1241 case T_GPFLT + USER: /* general protection violation */
1242 #ifdef _SYSCALL32_IMPL
1243 if (p->p_model != DATAMODEL_NATIVE) {
1244 #endif /* _SYSCALL32_IMPL */
1245 if (instr_is_lcall_syscall((caddr_t)rp->r_pc)) {
1246 if (type == T_SEGFLT + USER)
1247 ASSERT(p->p_ldt != NULL);
1248
1249 if ((p->p_ldt == NULL && type == T_GPFLT + USER) ||
1250 type == T_SEGFLT + USER) {
1251
1252 /*
1253 * The user attempted a system call via the obsolete
1254 * call gate mechanism. Because the process doesn't have
1255 * an LDT (i.e. the ldtr contains 0), a #gp results.
1256 * Emulate the syscall here, just as we do above for a
1257 * #np trap.
1258 */
1259
1260 /*
1261 * Since this is a not-present trap, rp->r_pc points to
1262 * the trapping lcall instruction. We need to bump it
1263 * to the next insn so the app can continue on.
1264 */
1265 rp->r_pc += LCALLSIZE;
1266 lwp->lwp_regs = rp;
1267
1268 /*
1269 * Normally the microstate of the LWP is forced back to
1270 * LMS_USER by the syscall handlers. Emulate that
1271 * behavior here.
1272 */
1273 mstate = LMS_USER;
1274
1275 dosyscall();
1276 goto out;
1277 }
1278 }
1279 #ifdef _SYSCALL32_IMPL
1280 }
1281 #endif /* _SYSCALL32_IMPL */
1282 /*
1283 * If the current process is using a private LDT and the
1284 * trapping instruction is sysenter, the sysenter instruction
1285 * has been disabled on the CPU because it destroys segment
1286 * registers. If this is the case, rewrite the instruction to
1287 * be a safe system call and retry it. If this occurs on a CPU
1288 * which doesn't even support sysenter, the result of all of
1289 * this will be to emulate that particular instruction.
1290 */
1291 if (p->p_ldt != NULL &&
1292 ldt_rewrite_syscall(rp, p, X86FSET_SEP))
1293 goto out;
1294
1295 /*FALLTHROUGH*/
1296
1297 case T_BOUNDFLT + USER: /* bound fault */
1298 case T_STKFLT + USER: /* stack fault */
1299 case T_TSSFLT + USER: /* invalid TSS fault */
1300 if (tudebug)
1301 showregs(type, rp, (caddr_t)0);
1302 siginfo.si_signo = SIGSEGV;
1303 siginfo.si_code = SEGV_MAPERR;
1304 siginfo.si_addr = (caddr_t)rp->r_pc;
1305 fault = FLTBOUNDS;
1306 break;
1307
1308 case T_ALIGNMENT + USER: /* user alignment error (486) */
1309 if (tudebug)
1310 showregs(type, rp, (caddr_t)0);
1311 bzero(&siginfo, sizeof (siginfo));
1312 siginfo.si_signo = SIGBUS;
1313 siginfo.si_code = BUS_ADRALN;
1314 siginfo.si_addr = (caddr_t)rp->r_pc;
1315 fault = FLTACCESS;
1316 break;
1317
1318 case T_SGLSTP + USER: /* single step/hw breakpoint exception */
1319 if (tudebug && tudebugbpt)
1320 showregs(type, rp, (caddr_t)0);
1321
1322 /* Was it single-stepping? */
1323 if (lwp->lwp_pcb.pcb_drstat & DR_SINGLESTEP) {
1324 pcb_t *pcb = &lwp->lwp_pcb;
1325
1326 rp->r_ps &= ~PS_T;
1327 /*
1328 * If both NORMAL_STEP and WATCH_STEP are in effect,
1329 * give precedence to WATCH_STEP. If neither is set,
1330 * user must have set the PS_T bit in %efl; treat this
1331 * as NORMAL_STEP.
1332 */
1333 if ((fault = undo_watch_step(&siginfo)) == 0 &&
1334 ((pcb->pcb_flags & NORMAL_STEP) ||
1335 !(pcb->pcb_flags & WATCH_STEP))) {
1336 siginfo.si_signo = SIGTRAP;
1337 siginfo.si_code = TRAP_TRACE;
1338 siginfo.si_addr = (caddr_t)rp->r_pc;
1339 fault = FLTTRACE;
1340 }
1341 pcb->pcb_flags &= ~(NORMAL_STEP|WATCH_STEP);
1342 }
1343 break;
1344
1345 case T_BPTFLT + USER: /* breakpoint trap */
1346 if (tudebug && tudebugbpt)
1347 showregs(type, rp, (caddr_t)0);
1348 /*
1349 * int 3 (the breakpoint instruction) leaves the pc referring
1350 * to the address one byte after the breakpointed address.
1351 * If the P_PR_BPTADJ flag has been set via /proc, We adjust
1352 * it back so it refers to the breakpointed address.
1353 */
1354 if (p->p_proc_flag & P_PR_BPTADJ)
1355 rp->r_pc--;
1356 siginfo.si_signo = SIGTRAP;
1357 siginfo.si_code = TRAP_BRKPT;
1358 siginfo.si_addr = (caddr_t)rp->r_pc;
1359 fault = FLTBPT;
1360 break;
1361
1362 case T_AST:
1363 /*
1364 * This occurs only after the cs register has been made to
1365 * look like a kernel selector, either through debugging or
1366 * possibly by functions like setcontext(). The thread is
1367 * about to cause a general protection fault at common_iret()
1368 * in locore. We let that happen immediately instead of
1369 * doing the T_AST processing.
1370 */
1371 goto cleanup;
1372
1373 case T_AST + USER: /* profiling, resched, h/w error pseudo trap */
1374 if (lwp->lwp_pcb.pcb_flags & ASYNC_HWERR) {
1375 proc_t *p = ttoproc(curthread);
1376 extern void print_msg_hwerr(ctid_t ct_id, proc_t *p);
1377
1378 lwp->lwp_pcb.pcb_flags &= ~ASYNC_HWERR;
1379 print_msg_hwerr(p->p_ct_process->conp_contract.ct_id,
1380 p);
1381 contract_process_hwerr(p->p_ct_process, p);
1382 siginfo.si_signo = SIGKILL;
1383 siginfo.si_code = SI_NOINFO;
1384 } else if (lwp->lwp_pcb.pcb_flags & CPC_OVERFLOW) {
1385 lwp->lwp_pcb.pcb_flags &= ~CPC_OVERFLOW;
1386 if (kcpc_overflow_ast()) {
1387 /*
1388 * Signal performance counter overflow
1389 */
1390 if (tudebug)
1391 showregs(type, rp, (caddr_t)0);
1392 bzero(&siginfo, sizeof (siginfo));
1393 siginfo.si_signo = SIGEMT;
1394 siginfo.si_code = EMT_CPCOVF;
1395 siginfo.si_addr = (caddr_t)rp->r_pc;
1396 fault = FLTCPCOVF;
1397 }
1398 }
1399
1400 break;
1401 }
1402
1403 /*
1404 * We can't get here from a system trap
1405 */
1406 ASSERT(type & USER);
1407
1408 if (fault) {
1409 /* We took a fault so abort single step. */
1410 lwp->lwp_pcb.pcb_flags &= ~(NORMAL_STEP|WATCH_STEP);
1411 /*
1412 * Remember the fault and fault adddress
1413 * for real-time (SIGPROF) profiling.
1414 */
1415 lwp->lwp_lastfault = fault;
1416 lwp->lwp_lastfaddr = siginfo.si_addr;
1417
1418 DTRACE_PROC2(fault, int, fault, ksiginfo_t *, &siginfo);
1419
1420 /*
1421 * If a debugger has declared this fault to be an
1422 * event of interest, stop the lwp. Otherwise just
1423 * deliver the associated signal.
1424 */
1425 if (siginfo.si_signo != SIGKILL &&
1426 prismember(&p->p_fltmask, fault) &&
1427 stop_on_fault(fault, &siginfo) == 0)
1428 siginfo.si_signo = 0;
1429 }
1430
1431 if (siginfo.si_signo)
1432 trapsig(&siginfo, (fault != FLTFPE && fault != FLTCPCOVF));
1433
1434 if (lwp->lwp_oweupc)
1435 profil_tick(rp->r_pc);
1436
1437 if (ct->t_astflag | ct->t_sig_check) {
1438 /*
1439 * Turn off the AST flag before checking all the conditions that
1440 * may have caused an AST. This flag is on whenever a signal or
1441 * unusual condition should be handled after the next trap or
1442 * syscall.
1443 */
1444 astoff(ct);
1445 /*
1446 * If a single-step trap occurred on a syscall (see above)
1447 * recognize it now. Do this before checking for signals
1448 * because deferred_singlestep_trap() may generate a SIGTRAP to
1449 * the LWP or may otherwise mark the LWP to call issig(FORREAL).
1450 */
1451 if (lwp->lwp_pcb.pcb_flags & DEBUG_PENDING)
1452 deferred_singlestep_trap((caddr_t)rp->r_pc);
1453
1454 ct->t_sig_check = 0;
1455
1456 mutex_enter(&p->p_lock);
1457 if (curthread->t_proc_flag & TP_CHANGEBIND) {
1458 timer_lwpbind();
1459 curthread->t_proc_flag &= ~TP_CHANGEBIND;
1460 }
1461 mutex_exit(&p->p_lock);
1462
1463 /*
1464 * for kaio requests that are on the per-process poll queue,
1465 * aiop->aio_pollq, they're AIO_POLL bit is set, the kernel
1466 * should copyout their result_t to user memory. by copying
1467 * out the result_t, the user can poll on memory waiting
1468 * for the kaio request to complete.
1469 */
1470 if (p->p_aio)
1471 aio_cleanup(0);
1472 /*
1473 * If this LWP was asked to hold, call holdlwp(), which will
1474 * stop. holdlwps() sets this up and calls pokelwps() which
1475 * sets the AST flag.
1476 *
1477 * Also check TP_EXITLWP, since this is used by fresh new LWPs
1478 * through lwp_rtt(). That flag is set if the lwp_create(2)
1479 * syscall failed after creating the LWP.
1480 */
1481 if (ISHOLD(p))
1482 holdlwp();
1483
1484 /*
1485 * All code that sets signals and makes ISSIG evaluate true must
1486 * set t_astflag afterwards.
1487 */
1488 if (ISSIG_PENDING(ct, lwp, p)) {
1489 if (issig(FORREAL))
1490 psig();
1491 ct->t_sig_check = 1;
1492 }
1493
1494 if (ct->t_rprof != NULL) {
1495 realsigprof(0, 0, 0);
1496 ct->t_sig_check = 1;
1497 }
1498
1499 /*
1500 * /proc can't enable/disable the trace bit itself
1501 * because that could race with the call gate used by
1502 * system calls via "lcall". If that happened, an
1503 * invalid EFLAGS would result. prstep()/prnostep()
1504 * therefore schedule an AST for the purpose.
1505 */
1506 if (lwp->lwp_pcb.pcb_flags & REQUEST_STEP) {
1507 lwp->lwp_pcb.pcb_flags &= ~REQUEST_STEP;
1508 rp->r_ps |= PS_T;
1509 }
1510 if (lwp->lwp_pcb.pcb_flags & REQUEST_NOSTEP) {
1511 lwp->lwp_pcb.pcb_flags &= ~REQUEST_NOSTEP;
1512 rp->r_ps &= ~PS_T;
1513 }
1514 }
1515
1516 out: /* We can't get here from a system trap */
1517 ASSERT(type & USER);
1518
1519 if (ISHOLD(p))
1520 holdlwp();
1521
1522 /*
1523 * Set state to LWP_USER here so preempt won't give us a kernel
1524 * priority if it occurs after this point. Call CL_TRAPRET() to
1525 * restore the user-level priority.
1526 *
1527 * It is important that no locks (other than spinlocks) be entered
1528 * after this point before returning to user mode (unless lwp_state
1529 * is set back to LWP_SYS).
1530 */
1531 lwp->lwp_state = LWP_USER;
1532
1533 if (ct->t_trapret) {
1534 ct->t_trapret = 0;
1535 thread_lock(ct);
1536 CL_TRAPRET(ct);
1537 thread_unlock(ct);
1538 }
1539 if (CPU->cpu_runrun || curthread->t_schedflag & TS_ANYWAITQ)
1540 preempt();
1541 prunstop();
1542 (void) new_mstate(ct, mstate);
1543
1544 /* Kernel probe */
1545 TNF_PROBE_1(thread_state, "thread", /* CSTYLED */,
1546 tnf_microstate, state, LMS_USER);
1547
1548 return;
1549
1550 cleanup: /* system traps end up here */
1551 ASSERT(!(type & USER));
1552 }
1553
1554 /*
1555 * Patch non-zero to disable preemption of threads in the kernel.
1556 */
1557 int IGNORE_KERNEL_PREEMPTION = 0; /* XXX - delete this someday */
1558
1559 struct kpreempt_cnts { /* kernel preemption statistics */
1560 int kpc_idle; /* executing idle thread */
1561 int kpc_intr; /* executing interrupt thread */
1562 int kpc_clock; /* executing clock thread */
1563 int kpc_blocked; /* thread has blocked preemption (t_preempt) */
1564 int kpc_notonproc; /* thread is surrendering processor */
1565 int kpc_inswtch; /* thread has ratified scheduling decision */
1566 int kpc_prilevel; /* processor interrupt level is too high */
1567 int kpc_apreempt; /* asynchronous preemption */
1568 int kpc_spreempt; /* synchronous preemption */
1569 } kpreempt_cnts;
1570
1571 /*
1572 * kernel preemption: forced rescheduling, preempt the running kernel thread.
1573 * the argument is old PIL for an interrupt,
1574 * or the distingished value KPREEMPT_SYNC.
1575 */
1576 void
1577 kpreempt(int asyncspl)
1578 {
1579 kthread_t *ct = curthread;
1580
1581 if (IGNORE_KERNEL_PREEMPTION) {
1582 aston(CPU->cpu_dispthread);
1583 return;
1584 }
1585
1586 /*
1587 * Check that conditions are right for kernel preemption
1588 */
1589 do {
1590 if (ct->t_preempt) {
1591 /*
1592 * either a privileged thread (idle, panic, interrupt)
1593 * or will check when t_preempt is lowered
1594 * We need to specifically handle the case where
1595 * the thread is in the middle of swtch (resume has
1596 * been called) and has its t_preempt set
1597 * [idle thread and a thread which is in kpreempt
1598 * already] and then a high priority thread is
1599 * available in the local dispatch queue.
1600 * In this case the resumed thread needs to take a
1601 * trap so that it can call kpreempt. We achieve
1602 * this by using siron().
1603 * How do we detect this condition:
1604 * idle thread is running and is in the midst of
1605 * resume: curthread->t_pri == -1 && CPU->dispthread
1606 * != CPU->thread
1607 * Need to ensure that this happens only at high pil
1608 * resume is called at high pil
1609 * Only in resume_from_idle is the pil changed.
1610 */
1611 if (ct->t_pri < 0) {
1612 kpreempt_cnts.kpc_idle++;
1613 if (CPU->cpu_dispthread != CPU->cpu_thread)
1614 siron();
1615 } else if (ct->t_flag & T_INTR_THREAD) {
1616 kpreempt_cnts.kpc_intr++;
1617 if (ct->t_pil == CLOCK_LEVEL)
1618 kpreempt_cnts.kpc_clock++;
1619 } else {
1620 kpreempt_cnts.kpc_blocked++;
1621 if (CPU->cpu_dispthread != CPU->cpu_thread)
1622 siron();
1623 }
1624 aston(CPU->cpu_dispthread);
1625 return;
1626 }
1627 if (ct->t_state != TS_ONPROC ||
1628 ct->t_disp_queue != CPU->cpu_disp) {
1629 /* this thread will be calling swtch() shortly */
1630 kpreempt_cnts.kpc_notonproc++;
1631 if (CPU->cpu_thread != CPU->cpu_dispthread) {
1632 /* already in swtch(), force another */
1633 kpreempt_cnts.kpc_inswtch++;
1634 siron();
1635 }
1636 return;
1637 }
1638 if (getpil() >= DISP_LEVEL) {
1639 /*
1640 * We can't preempt this thread if it is at
1641 * a PIL >= DISP_LEVEL since it may be holding
1642 * a spin lock (like sched_lock).
1643 */
1644 siron(); /* check back later */
1645 kpreempt_cnts.kpc_prilevel++;
1646 return;
1647 }
1648 if (!interrupts_enabled()) {
1649 /*
1650 * Can't preempt while running with ints disabled
1651 */
1652 kpreempt_cnts.kpc_prilevel++;
1653 return;
1654 }
1655 if (asyncspl != KPREEMPT_SYNC)
1656 kpreempt_cnts.kpc_apreempt++;
1657 else
1658 kpreempt_cnts.kpc_spreempt++;
1659
1660 ct->t_preempt++;
1661 preempt();
1662 ct->t_preempt--;
1663 } while (CPU->cpu_kprunrun);
1664 }
1665
1666 /*
1667 * Print out debugging info.
1668 */
1669 static void
1670 showregs(uint_t type, struct regs *rp, caddr_t addr)
1671 {
1672 int s;
1673
1674 s = spl7();
1675 type &= ~USER;
1676 if (PTOU(curproc)->u_comm[0])
1677 printf("%s: ", PTOU(curproc)->u_comm);
1678 if (type < TRAP_TYPES)
1679 printf("#%s %s\n", trap_type_mnemonic[type], trap_type[type]);
1680 else
1681 switch (type) {
1682 case T_SYSCALL:
1683 printf("Syscall Trap:\n");
1684 break;
1685 case T_AST:
1686 printf("AST\n");
1687 break;
1688 default:
1689 printf("Bad Trap = %d\n", type);
1690 break;
1691 }
1692 if (type == T_PGFLT) {
1693 printf("Bad %s fault at addr=0x%lx\n",
1694 USERMODE(rp->r_cs) ? "user": "kernel", (uintptr_t)addr);
1695 } else if (addr) {
1696 printf("addr=0x%lx\n", (uintptr_t)addr);
1697 }
1698
1699 printf("pid=%d, pc=0x%lx, sp=0x%lx, eflags=0x%lx\n",
1700 (ttoproc(curthread) && ttoproc(curthread)->p_pidp) ?
1701 ttoproc(curthread)->p_pid : 0, rp->r_pc, rp->r_sp, rp->r_ps);
1702
1703 #if defined(__lint)
1704 /*
1705 * this clause can be deleted when lint bug 4870403 is fixed
1706 * (lint thinks that bit 32 is illegal in a %b format string)
1707 */
1708 printf("cr0: %x cr4: %b\n",
1709 (uint_t)getcr0(), (uint_t)getcr4(), FMT_CR4);
1710 #else
1711 printf("cr0: %b cr4: %b\n",
1712 (uint_t)getcr0(), FMT_CR0, (uint_t)getcr4(), FMT_CR4);
1713 #endif /* __lint */
1714
1715 printf("cr2: %lx", getcr2());
1716 #if !defined(__xpv)
1717 printf("cr3: %lx", getcr3());
1718 #if defined(__amd64)
1719 printf("cr8: %lx\n", getcr8());
1720 #endif
1721 #endif
1722 printf("\n");
1723
1724 dumpregs(rp);
1725 splx(s);
1726 }
1727
1728 static void
1729 dumpregs(struct regs *rp)
1730 {
1731 #if defined(__amd64)
1732 const char fmt[] = "\t%3s: %16lx %3s: %16lx %3s: %16lx\n";
1733
1734 printf(fmt, "rdi", rp->r_rdi, "rsi", rp->r_rsi, "rdx", rp->r_rdx);
1735 printf(fmt, "rcx", rp->r_rcx, " r8", rp->r_r8, " r9", rp->r_r9);
1736 printf(fmt, "rax", rp->r_rax, "rbx", rp->r_rbx, "rbp", rp->r_rbp);
1737 printf(fmt, "r10", rp->r_r10, "r11", rp->r_r11, "r12", rp->r_r12);
1738 printf(fmt, "r13", rp->r_r13, "r14", rp->r_r14, "r15", rp->r_r15);
1739
1740 printf(fmt, "fsb", rdmsr(MSR_AMD_FSBASE), "gsb", rdmsr(MSR_AMD_GSBASE),
1741 " ds", rp->r_ds);
1742 printf(fmt, " es", rp->r_es, " fs", rp->r_fs, " gs", rp->r_gs);
1743
1744 printf(fmt, "trp", rp->r_trapno, "err", rp->r_err, "rip", rp->r_rip);
1745 printf(fmt, " cs", rp->r_cs, "rfl", rp->r_rfl, "rsp", rp->r_rsp);
1746
1747 printf("\t%3s: %16lx\n", " ss", rp->r_ss);
1748
1749 #elif defined(__i386)
1750 const char fmt[] = "\t%3s: %8lx %3s: %8lx %3s: %8lx %3s: %8lx\n";
1751
1752 printf(fmt, " gs", rp->r_gs, " fs", rp->r_fs,
1753 " es", rp->r_es, " ds", rp->r_ds);
1754 printf(fmt, "edi", rp->r_edi, "esi", rp->r_esi,
1755 "ebp", rp->r_ebp, "esp", rp->r_esp);
1756 printf(fmt, "ebx", rp->r_ebx, "edx", rp->r_edx,
1757 "ecx", rp->r_ecx, "eax", rp->r_eax);
1758 printf(fmt, "trp", rp->r_trapno, "err", rp->r_err,
1759 "eip", rp->r_eip, " cs", rp->r_cs);
1760 printf("\t%3s: %8lx %3s: %8lx %3s: %8lx\n",
1761 "efl", rp->r_efl, "usp", rp->r_uesp, " ss", rp->r_ss);
1762
1763 #endif /* __i386 */
1764 }
1765
1766 /*
1767 * Test to see if the instruction is iret on i386 or iretq on amd64.
1768 *
1769 * On the hypervisor we can only test for nopop_sys_rtt_syscall. If true
1770 * then we are in the context of hypervisor's failsafe handler because it
1771 * tried to iret and failed due to a bad selector. See xen_failsafe_callback.
1772 */
1773 static int
1774 instr_is_iret(caddr_t pc)
1775 {
1776
1777 #if defined(__xpv)
1778 extern void nopop_sys_rtt_syscall(void);
1779 return ((pc == (caddr_t)nopop_sys_rtt_syscall) ? 1 : 0);
1780
1781 #else
1782
1783 #if defined(__amd64)
1784 static const uint8_t iret_insn[2] = { 0x48, 0xcf }; /* iretq */
1785
1786 #elif defined(__i386)
1787 static const uint8_t iret_insn[1] = { 0xcf }; /* iret */
1788 #endif /* __i386 */
1789 return (bcmp(pc, iret_insn, sizeof (iret_insn)) == 0);
1790
1791 #endif /* __xpv */
1792 }
1793
1794 #if defined(__i386)
1795
1796 /*
1797 * Test to see if the instruction is part of __SEGREGS_POP
1798 *
1799 * Note carefully the appallingly awful dependency between
1800 * the instruction sequence used in __SEGREGS_POP and these
1801 * instructions encoded here.
1802 */
1803 static int
1804 instr_is_segregs_pop(caddr_t pc)
1805 {
1806 static const uint8_t movw_0_esp_gs[4] = { 0x8e, 0x6c, 0x24, 0x0 };
1807 static const uint8_t movw_4_esp_fs[4] = { 0x8e, 0x64, 0x24, 0x4 };
1808 static const uint8_t movw_8_esp_es[4] = { 0x8e, 0x44, 0x24, 0x8 };
1809 static const uint8_t movw_c_esp_ds[4] = { 0x8e, 0x5c, 0x24, 0xc };
1810
1811 if (bcmp(pc, movw_0_esp_gs, sizeof (movw_0_esp_gs)) == 0 ||
1812 bcmp(pc, movw_4_esp_fs, sizeof (movw_4_esp_fs)) == 0 ||
1813 bcmp(pc, movw_8_esp_es, sizeof (movw_8_esp_es)) == 0 ||
1814 bcmp(pc, movw_c_esp_ds, sizeof (movw_c_esp_ds)) == 0)
1815 return (1);
1816
1817 return (0);
1818 }
1819
1820 #endif /* __i386 */
1821
1822 /*
1823 * Test to see if the instruction is part of _sys_rtt.
1824 *
1825 * Again on the hypervisor if we try to IRET to user land with a bad code
1826 * or stack selector we will get vectored through xen_failsafe_callback.
1827 * In which case we assume we got here via _sys_rtt since we only allow
1828 * IRET to user land to take place in _sys_rtt.
1829 */
1830 static int
1831 instr_is_sys_rtt(caddr_t pc)
1832 {
1833 extern void _sys_rtt(), _sys_rtt_end();
1834
1835 if ((uintptr_t)pc < (uintptr_t)_sys_rtt ||
1836 (uintptr_t)pc > (uintptr_t)_sys_rtt_end)
1837 return (0);
1838
1839 return (1);
1840 }
1841
1842 /*
1843 * Handle #gp faults in kernel mode.
1844 *
1845 * One legitimate way this can happen is if we attempt to update segment
1846 * registers to naughty values on the way out of the kernel.
1847 *
1848 * This can happen in a couple of ways: someone - either accidentally or
1849 * on purpose - creates (setcontext(2), lwp_create(2)) or modifies
1850 * (signal(2)) a ucontext that contains silly segment register values.
1851 * Or someone - either accidentally or on purpose - modifies the prgregset_t
1852 * of a subject process via /proc to contain silly segment register values.
1853 *
1854 * (The unfortunate part is that we can end up discovering the bad segment
1855 * register value in the middle of an 'iret' after we've popped most of the
1856 * stack. So it becomes quite difficult to associate an accurate ucontext
1857 * with the lwp, because the act of taking the #gp trap overwrites most of
1858 * what we were going to send the lwp.)
1859 *
1860 * OTOH if it turns out that's -not- the problem, and we're -not- an lwp
1861 * trying to return to user mode and we get a #gp fault, then we need
1862 * to die() -- which will happen if we return non-zero from this routine.
1863 */
1864 static int
1865 kern_gpfault(struct regs *rp)
1866 {
1867 kthread_t *t = curthread;
1868 proc_t *p = ttoproc(t);
1869 klwp_t *lwp = ttolwp(t);
1870 struct regs tmpregs, *trp = NULL;
1871 caddr_t pc = (caddr_t)rp->r_pc;
1872 int v;
1873 uint32_t auditing = AU_AUDITING();
1874
1875 /*
1876 * if we're not an lwp, or in the case of running native the
1877 * pc range is outside _sys_rtt, then we should immediately
1878 * be die()ing horribly.
1879 */
1880 if (lwp == NULL || !instr_is_sys_rtt(pc))
1881 return (1);
1882
1883 /*
1884 * So at least we're in the right part of the kernel.
1885 *
1886 * Disassemble the instruction at the faulting pc.
1887 * Once we know what it is, we carefully reconstruct the stack
1888 * based on the order in which the stack is deconstructed in
1889 * _sys_rtt. Ew.
1890 */
1891 if (instr_is_iret(pc)) {
1892 /*
1893 * We took the #gp while trying to perform the IRET.
1894 * This means that either %cs or %ss are bad.
1895 * All we know for sure is that most of the general
1896 * registers have been restored, including the
1897 * segment registers, and all we have left on the
1898 * topmost part of the lwp's stack are the
1899 * registers that the iretq was unable to consume.
1900 *
1901 * All the rest of the state was crushed by the #gp
1902 * which pushed -its- registers atop our old save area
1903 * (because we had to decrement the stack pointer, sigh) so
1904 * all that we can try and do is to reconstruct the
1905 * crushed frame from the #gp trap frame itself.
1906 */
1907 trp = &tmpregs;
1908 trp->r_ss = lwptoregs(lwp)->r_ss;
1909 trp->r_sp = lwptoregs(lwp)->r_sp;
1910 trp->r_ps = lwptoregs(lwp)->r_ps;
1911 trp->r_cs = lwptoregs(lwp)->r_cs;
1912 trp->r_pc = lwptoregs(lwp)->r_pc;
1913 bcopy(rp, trp, offsetof(struct regs, r_pc));
1914
1915 /*
1916 * Validate simple math
1917 */
1918 ASSERT(trp->r_pc == lwptoregs(lwp)->r_pc);
1919 ASSERT(trp->r_err == rp->r_err);
1920
1921
1922
1923 }
1924
1925 #if defined(__amd64)
1926 if (trp == NULL && lwp->lwp_pcb.pcb_rupdate != 0) {
1927
1928 /*
1929 * This is the common case -- we're trying to load
1930 * a bad segment register value in the only section
1931 * of kernel code that ever loads segment registers.
1932 *
1933 * We don't need to do anything at this point because
1934 * the pcb contains all the pending segment register
1935 * state, and the regs are still intact because we
1936 * didn't adjust the stack pointer yet. Given the fidelity
1937 * of all this, we could conceivably send a signal
1938 * to the lwp, rather than core-ing.
1939 */
1940 trp = lwptoregs(lwp);
1941 ASSERT((caddr_t)trp == (caddr_t)rp->r_sp);
1942 }
1943
1944 #elif defined(__i386)
1945
1946 if (trp == NULL && instr_is_segregs_pop(pc))
1947 trp = lwptoregs(lwp);
1948
1949 #endif /* __i386 */
1950
1951 if (trp == NULL)
1952 return (1);
1953
1954 /*
1955 * If we get to here, we're reasonably confident that we've
1956 * correctly decoded what happened on the way out of the kernel.
1957 * Rewrite the lwp's registers so that we can create a core dump
1958 * the (at least vaguely) represents the mcontext we were
1959 * being asked to restore when things went so terribly wrong.
1960 */
1961
1962 /*
1963 * Make sure that we have a meaningful %trapno and %err.
1964 */
1965 trp->r_trapno = rp->r_trapno;
1966 trp->r_err = rp->r_err;
1967
1968 if ((caddr_t)trp != (caddr_t)lwptoregs(lwp))
1969 bcopy(trp, lwptoregs(lwp), sizeof (*trp));
1970
1971
1972 mutex_enter(&p->p_lock);
1973 lwp->lwp_cursig = SIGSEGV;
1974 mutex_exit(&p->p_lock);
1975
1976 /*
1977 * Terminate all LWPs but don't discard them. If another lwp beat
1978 * us to the punch by calling exit(), evaporate now.
1979 */
1980 proc_is_exiting(p);
1981 if (exitlwps(1) != 0) {
1982 mutex_enter(&p->p_lock);
1983 lwp_exit();
1984 }
1985
1986 if (auditing) /* audit core dump */
1987 audit_core_start(SIGSEGV);
1988 v = core(SIGSEGV, B_FALSE);
1989 if (auditing) /* audit core dump */
1990 audit_core_finish(v ? CLD_KILLED : CLD_DUMPED);
1991 exit(v ? CLD_KILLED : CLD_DUMPED, SIGSEGV);
1992 return (0);
1993 }
1994
1995 /*
1996 * dump_tss() - Display the TSS structure
1997 */
1998
1999 #if !defined(__xpv)
2000 #if defined(__amd64)
2001
2002 static void
2003 dump_tss(void)
2004 {
2005 const char tss_fmt[] = "tss.%s:\t0x%p\n"; /* Format string */
2006 tss_t *tss = CPU->cpu_tss;
2007
2008 printf(tss_fmt, "tss_rsp0", (void *)tss->tss_rsp0);
2009 printf(tss_fmt, "tss_rsp1", (void *)tss->tss_rsp1);
2010 printf(tss_fmt, "tss_rsp2", (void *)tss->tss_rsp2);
2011
2012 printf(tss_fmt, "tss_ist1", (void *)tss->tss_ist1);
2013 printf(tss_fmt, "tss_ist2", (void *)tss->tss_ist2);
2014 printf(tss_fmt, "tss_ist3", (void *)tss->tss_ist3);
2015 printf(tss_fmt, "tss_ist4", (void *)tss->tss_ist4);
2016 printf(tss_fmt, "tss_ist5", (void *)tss->tss_ist5);
2017 printf(tss_fmt, "tss_ist6", (void *)tss->tss_ist6);
2018 printf(tss_fmt, "tss_ist7", (void *)tss->tss_ist7);
2019 }
2020
2021 #elif defined(__i386)
2022
2023 static void
2024 dump_tss(void)
2025 {
2026 const char tss_fmt[] = "tss.%s:\t0x%p\n"; /* Format string */
2027 tss_t *tss = CPU->cpu_tss;
2028
2029 printf(tss_fmt, "tss_link", (void *)(uintptr_t)tss->tss_link);
2030 printf(tss_fmt, "tss_esp0", (void *)(uintptr_t)tss->tss_esp0);
2031 printf(tss_fmt, "tss_ss0", (void *)(uintptr_t)tss->tss_ss0);
2032 printf(tss_fmt, "tss_esp1", (void *)(uintptr_t)tss->tss_esp1);
2033 printf(tss_fmt, "tss_ss1", (void *)(uintptr_t)tss->tss_ss1);
2034 printf(tss_fmt, "tss_esp2", (void *)(uintptr_t)tss->tss_esp2);
2035 printf(tss_fmt, "tss_ss2", (void *)(uintptr_t)tss->tss_ss2);
2036 printf(tss_fmt, "tss_cr3", (void *)(uintptr_t)tss->tss_cr3);
2037 printf(tss_fmt, "tss_eip", (void *)(uintptr_t)tss->tss_eip);
2038 printf(tss_fmt, "tss_eflags", (void *)(uintptr_t)tss->tss_eflags);
2039 printf(tss_fmt, "tss_eax", (void *)(uintptr_t)tss->tss_eax);
2040 printf(tss_fmt, "tss_ebx", (void *)(uintptr_t)tss->tss_ebx);
2041 printf(tss_fmt, "tss_ecx", (void *)(uintptr_t)tss->tss_ecx);
2042 printf(tss_fmt, "tss_edx", (void *)(uintptr_t)tss->tss_edx);
2043 printf(tss_fmt, "tss_esp", (void *)(uintptr_t)tss->tss_esp);
2044 }
2045
2046 #endif /* __amd64 */
2047 #endif /* !__xpv */
2048
2049 #if defined(TRAPTRACE)
2050
2051 int ttrace_nrec = 10; /* number of records to dump out */
2052 int ttrace_dump_nregs = 0; /* dump out this many records with regs too */
2053
2054 /*
2055 * Dump out the last ttrace_nrec traptrace records on each CPU
2056 */
2057 static void
2058 dump_ttrace(void)
2059 {
2060 trap_trace_ctl_t *ttc;
2061 trap_trace_rec_t *rec;
2062 uintptr_t current;
2063 int i, j, k;
2064 int n = NCPU;
2065 #if defined(__amd64)
2066 const char banner[] =
2067 "\ncpu address timestamp "
2068 "type vc handler pc\n";
2069 const char fmt1[] = "%3d %016lx %12llx ";
2070 #elif defined(__i386)
2071 const char banner[] =
2072 "\ncpu address timestamp type vc handler pc\n";
2073 const char fmt1[] = "%3d %08lx %12llx ";
2074 #endif
2075 const char fmt2[] = "%4s %3x ";
2076 const char fmt3[] = "%8s ";
2077
2078 if (ttrace_nrec == 0)
2079 return;
2080
2081 printf(banner);
2082
2083 for (i = 0; i < n; i++) {
2084 ttc = &trap_trace_ctl[i];
2085 if (ttc->ttc_first == NULL)
2086 continue;
2087
2088 current = ttc->ttc_next - sizeof (trap_trace_rec_t);
2089 for (j = 0; j < ttrace_nrec; j++) {
2090 struct sysent *sys;
2091 struct autovec *vec;
2092 extern struct av_head autovect[];
2093 int type;
2094 ulong_t off;
2095 char *sym, *stype;
2096
2097 if (current < ttc->ttc_first)
2098 current =
2099 ttc->ttc_limit - sizeof (trap_trace_rec_t);
2100
2101 if (current == NULL)
2102 continue;
2103
2104 rec = (trap_trace_rec_t *)current;
2105
2106 if (rec->ttr_stamp == 0)
2107 break;
2108
2109 printf(fmt1, i, (uintptr_t)rec, rec->ttr_stamp);
2110
2111 switch (rec->ttr_marker) {
2112 case TT_SYSCALL:
2113 case TT_SYSENTER:
2114 case TT_SYSC:
2115 case TT_SYSC64:
2116 #if defined(__amd64)
2117 sys = &sysent32[rec->ttr_sysnum];
2118 switch (rec->ttr_marker) {
2119 case TT_SYSC64:
2120 sys = &sysent[rec->ttr_sysnum];
2121 /*FALLTHROUGH*/
2122 #elif defined(__i386)
2123 sys = &sysent[rec->ttr_sysnum];
2124 switch (rec->ttr_marker) {
2125 case TT_SYSC64:
2126 #endif
2127 case TT_SYSC:
2128 stype = "sysc"; /* syscall */
2129 break;
2130 case TT_SYSCALL:
2131 stype = "lcal"; /* lcall */
2132 break;
2133 case TT_SYSENTER:
2134 stype = "syse"; /* sysenter */
2135 break;
2136 default:
2137 break;
2138 }
2139 printf(fmt2, "sysc", rec->ttr_sysnum);
2140 if (sys != NULL) {
2141 sym = kobj_getsymname(
2142 (uintptr_t)sys->sy_callc,
2143 &off);
2144 if (sym != NULL)
2145 printf(fmt3, sym);
2146 else
2147 printf("%p ", sys->sy_callc);
2148 } else {
2149 printf(fmt3, "unknown");
2150 }
2151 break;
2152
2153 case TT_INTERRUPT:
2154 printf(fmt2, "intr", rec->ttr_vector);
2155 if (get_intr_handler != NULL)
2156 vec = (struct autovec *)
2157 (*get_intr_handler)
2158 (rec->ttr_cpuid, rec->ttr_vector);
2159 else
2160 vec =
2161 autovect[rec->ttr_vector].avh_link;
2162
2163 if (vec != NULL) {
2164 sym = kobj_getsymname(
2165 (uintptr_t)vec->av_vector, &off);
2166 if (sym != NULL)
2167 printf(fmt3, sym);
2168 else
2169 printf("%p ", vec->av_vector);
2170 } else {
2171 printf(fmt3, "unknown ");
2172 }
2173 break;
2174
2175 case TT_TRAP:
2176 case TT_EVENT:
2177 type = rec->ttr_regs.r_trapno;
2178 printf(fmt2, "trap", type);
2179 if (type < TRAP_TYPES)
2180 printf(" #%s ",
2181 trap_type_mnemonic[type]);
2182 else
2183 switch (type) {
2184 case T_AST:
2185 printf(fmt3, "ast");
2186 break;
2187 default:
2188 printf(fmt3, "");
2189 break;
2190 }
2191 break;
2192
2193 default:
2194 break;
2195 }
2196
2197 sym = kobj_getsymname(rec->ttr_regs.r_pc, &off);
2198 if (sym != NULL)
2199 printf("%s+%lx\n", sym, off);
2200 else
2201 printf("%lx\n", rec->ttr_regs.r_pc);
2202
2203 if (ttrace_dump_nregs-- > 0) {
2204 int s;
2205
2206 if (rec->ttr_marker == TT_INTERRUPT)
2207 printf(
2208 "\t\tipl %x spl %x pri %x\n",
2209 rec->ttr_ipl,
2210 rec->ttr_spl,
2211 rec->ttr_pri);
2212
2213 dumpregs(&rec->ttr_regs);
2214
2215 printf("\t%3s: %p\n\n", " ct",
2216 (void *)rec->ttr_curthread);
2217
2218 /*
2219 * print out the pc stack that we recorded
2220 * at trap time (if any)
2221 */
2222 for (s = 0; s < rec->ttr_sdepth; s++) {
2223 uintptr_t fullpc;
2224
2225 if (s >= TTR_STACK_DEPTH) {
2226 printf("ttr_sdepth corrupt\n");
2227 break;
2228 }
2229
2230 fullpc = (uintptr_t)rec->ttr_stack[s];
2231
2232 sym = kobj_getsymname(fullpc, &off);
2233 if (sym != NULL)
2234 printf("-> %s+0x%lx()\n",
2235 sym, off);
2236 else
2237 printf("-> 0x%lx()\n", fullpc);
2238 }
2239 printf("\n");
2240 }
2241 current -= sizeof (trap_trace_rec_t);
2242 }
2243 }
2244 }
2245
2246 #endif /* TRAPTRACE */
2247
2248 void
2249 panic_showtrap(struct panic_trap_info *tip)
2250 {
2251 showregs(tip->trap_type, tip->trap_regs, tip->trap_addr);
2252
2253 #if defined(TRAPTRACE)
2254 dump_ttrace();
2255 #endif
2256
2257 #if !defined(__xpv)
2258 if (tip->trap_type == T_DBLFLT)
2259 dump_tss();
2260 #endif
2261 }
2262
2263 void
2264 panic_savetrap(panic_data_t *pdp, struct panic_trap_info *tip)
2265 {
2266 panic_saveregs(pdp, tip->trap_regs);
2267 }