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5291 x86 {high,low}bit rely on undefined behavior
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--- old/usr/src/uts/intel/ia32/ml/ia32.il
+++ new/usr/src/uts/intel/ia32/ml/ia32.il
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 27 /
28 28 / Inline functions for i386 kernels.
29 29 / Shared between all x86 platform variants.
30 30 /
31 31
32 32 /
33 33 / return current thread pointer
34 34 /
35 35 / NOTE: the "0x10" should be replaced by the computed value of the
36 36 / offset of "cpu_thread" from the beginning of the struct cpu.
37 37 / Including "assym.h" does not work, however, since that stuff
38 38 / is PSM-specific and is only visible to the 'unix' build anyway.
39 39 / Same with current cpu pointer, where "0xc" should be replaced
40 40 / by the computed value of the offset of "cpu_self".
41 41 / Ugh -- what a disaster.
42 42 /
43 43 .inline threadp,0
44 44 movl %gs:0x10, %eax
45 45 .end
46 46
47 47 /
48 48 / return current cpu pointer
49 49 /
50 50 .inline curcpup,0
51 51 movl %gs:0xc, %eax
52 52 .end
53 53
54 54 /
55 55 / return caller
56 56 /
57 57 .inline caller,0
58 58 movl 4(%ebp), %eax
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59 59 .end
60 60
61 61 /
62 62 / convert ipl to spl. This is the identity function for i86
63 63 /
64 64 .inline ipltospl,0
65 65 movl (%esp), %eax
66 66 .end
67 67
68 68 /
69 -/ find the low order bit in a word
70 -/
71 - .inline lowbit,4
72 - movl $-1, %eax
73 - bsfl (%esp), %eax
74 - incl %eax
75 - .end
76 -
77 -/
78 -/ find the high order bit in a word
79 -/
80 - .inline highbit,4
81 - movl $-1, %eax
82 - bsrl (%esp), %eax
83 - incl %eax
84 - .end
85 -
86 -/
87 69 / Networking byte order functions (too bad, Intel has the wrong byte order)
88 70 /
89 71 .inline htonll,4
90 72 movl (%esp), %edx
91 73 movl 4(%esp), %eax
92 74 bswap %edx
93 75 bswap %eax
94 76 .end
95 77
96 78 .inline ntohll,4
97 79 movl (%esp), %edx
98 80 movl 4(%esp), %eax
99 81 bswap %edx
100 82 bswap %eax
101 83 .end
102 84
103 85 .inline htonl,4
104 86 movl (%esp), %eax
105 87 bswap %eax
106 88 .end
107 89
108 90 .inline ntohl,4
109 91 movl (%esp), %eax
110 92 bswap %eax
111 93 .end
112 94
113 95 .inline htons,4
114 96 movl (%esp), %eax
115 97 bswap %eax
116 98 shrl $16, %eax
117 99 .end
118 100
119 101 .inline ntohs,4
120 102 movl (%esp), %eax
121 103 bswap %eax
122 104 shrl $16, %eax
123 105 .end
124 106
125 107 /*
126 108 * multiply two long numbers and yield a u_longlong_t result
127 109 * Provided to manipulate hrtime_t values.
128 110 */
129 111 .inline mul32, 8
130 112 movl 4(%esp), %eax
131 113 movl (%esp), %ecx
132 114 mull %ecx
133 115 .end
134 116
135 117 /*
136 118 * Unlock hres_lock and increment the count value. (See clock.h)
137 119 */
138 120 .inline unlock_hres_lock, 0
139 121 lock
140 122 incl hres_lock
141 123 .end
142 124
143 125 .inline atomic_orb,8
144 126 movl (%esp), %eax
145 127 movl 4(%esp), %edx
146 128 lock
147 129 orb %dl,(%eax)
148 130 .end
149 131
150 132 .inline atomic_andb,8
151 133 movl (%esp), %eax
152 134 movl 4(%esp), %edx
153 135 lock
154 136 andb %dl,(%eax)
155 137 .end
156 138
157 139 /*
158 140 * atomic inc/dec operations.
159 141 * void atomic_inc16(uint16_t *addr) { ++*addr; }
160 142 * void atomic_dec16(uint16_t *addr) { --*addr; }
161 143 */
162 144 .inline atomic_inc16,4
163 145 movl (%esp), %eax
164 146 lock
165 147 incw (%eax)
166 148 .end
167 149
168 150 .inline atomic_dec16,4
169 151 movl (%esp), %eax
170 152 lock
171 153 decw (%eax)
172 154 .end
173 155
174 156 /*
175 157 * Call the pause instruction. To the Pentium 4 Xeon processor, it acts as
176 158 * a hint that the code sequence is a busy spin-wait loop. Without a pause
177 159 * instruction in these loops, the P4 Xeon processor may suffer a severe
178 160 * penalty when exiting the loop because the processor detects a possible
179 161 * memory violation. Inserting the pause instruction significantly reduces
180 162 * the likelihood of a memory order violation, improving performance.
181 163 * The pause instruction is a NOP on all other IA-32 processors.
182 164 */
183 165 .inline ht_pause, 0
184 166 rep / our compiler doesn't support "pause" yet,
185 167 nop / so we're using "F3 90" opcode directly
186 168 .end
187 169
188 170 /*
189 171 * prefetch 64 bytes
190 172 *
191 173 * prefetch is an SSE extension which is not supported on older 32-bit processors
192 174 * so define this as a no-op for now
193 175 */
194 176
195 177 .inline prefetch_read_many,4
196 178 / movl (%esp), %eax
197 179 / prefetcht0 (%eax)
198 180 / prefetcht0 32(%eax)
199 181 .end
200 182
201 183 .inline prefetch_read_once,4
202 184 / movl (%esp), %eax
203 185 / prefetchnta (%eax)
204 186 / prefetchnta 32(%eax)
205 187 .end
206 188
207 189 .inline prefetch_write_many,4
208 190 / movl (%esp), %eax
209 191 / prefetcht0 (%eax)
210 192 / prefetcht0 32(%eax)
211 193 .end
212 194
213 195 .inline prefetch_write_once,4
214 196 / movl (%esp), %eax
215 197 / prefetcht0 (%eax)
216 198 / prefetcht0 32(%eax)
217 199 .end
218 200
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