16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 *
26 * Authors:
27 * Eric Anholt <eric@anholt.net>
28 *
29 */
30
31 /*
32 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
33 * Use is subject to license terms.
34 */
35
36 #include "drmP.h"
37 #include "drm.h"
38 #include "i915_drm.h"
39 #include "i915_drv.h"
40
41 /** @file i915_gem_tiling.c
42 *
43 * Support for managing tiling state of buffer objects.
44 *
45 * The idea behind tiling is to increase cache hit rates by rearranging
46 * pixel data so that a group of pixel accesses are in the same cacheline.
47 * Performance improvement from doing this on the back/depth buffer are on
48 * the order of 30%.
49 *
50 * Intel architectures make this somewhat more complicated, though, by
51 * adjustments made to addressing of data when the memory is in interleaved
52 * mode (matched pairs of DIMMS) to improve memory bandwidth.
53 * For interleaved memory, the CPU sends every sequential 64 bytes
54 * to an alternate memory channel so it can get the bandwidth from both.
55 *
229
230 if (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
231 tile_width = 128;
232 else
233 tile_width = 512;
234
235 if (stride == 0)
236 return 0;
237
238 /* 965+ just needs multiples of tile width */
239 if (IS_I965G(dev)) {
240 if (stride & (tile_width - 1))
241 return 0;
242 return 1;
243 }
244
245 /* Pre-965 needs power of two tile widths */
246 if (stride < tile_width)
247 return 0;
248
249 if (stride & (stride - 1))
250 return 0;
251
252 /* We don't handle the aperture area covered by the fence being bigger
253 * than the object size.
254 */
255 if (i915_get_fence_size(dev, size) != size)
256 return 0;
257
258 return 1;
259 }
260
261 /**
262 * Sets the tiling mode of an object, returning the required swizzling of
263 * bit 6 of addresses in the object.
264 */
265 /*ARGSUSED*/
266 int
267 i915_gem_set_tiling(DRM_IOCTL_ARGS)
268 {
269 DRM_DEVICE;
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16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 *
26 * Authors:
27 * Eric Anholt <eric@anholt.net>
28 *
29 */
30
31 /*
32 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
33 * Use is subject to license terms.
34 */
35
36 #include <sys/sysmacros.h>
37 #include "drmP.h"
38 #include "drm.h"
39 #include "i915_drm.h"
40 #include "i915_drv.h"
41
42 /** @file i915_gem_tiling.c
43 *
44 * Support for managing tiling state of buffer objects.
45 *
46 * The idea behind tiling is to increase cache hit rates by rearranging
47 * pixel data so that a group of pixel accesses are in the same cacheline.
48 * Performance improvement from doing this on the back/depth buffer are on
49 * the order of 30%.
50 *
51 * Intel architectures make this somewhat more complicated, though, by
52 * adjustments made to addressing of data when the memory is in interleaved
53 * mode (matched pairs of DIMMS) to improve memory bandwidth.
54 * For interleaved memory, the CPU sends every sequential 64 bytes
55 * to an alternate memory channel so it can get the bandwidth from both.
56 *
230
231 if (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
232 tile_width = 128;
233 else
234 tile_width = 512;
235
236 if (stride == 0)
237 return 0;
238
239 /* 965+ just needs multiples of tile width */
240 if (IS_I965G(dev)) {
241 if (stride & (tile_width - 1))
242 return 0;
243 return 1;
244 }
245
246 /* Pre-965 needs power of two tile widths */
247 if (stride < tile_width)
248 return 0;
249
250 if (!ISP2(stride))
251 return 0;
252
253 /* We don't handle the aperture area covered by the fence being bigger
254 * than the object size.
255 */
256 if (i915_get_fence_size(dev, size) != size)
257 return 0;
258
259 return 1;
260 }
261
262 /**
263 * Sets the tiling mode of an object, returning the required swizzling of
264 * bit 6 of addresses in the object.
265 */
266 /*ARGSUSED*/
267 int
268 i915_gem_set_tiling(DRM_IOCTL_ARGS)
269 {
270 DRM_DEVICE;
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