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5253 kmem_alloc/kmem_zalloc won't fail with KM_SLEEP
5254 getrbuf won't fail with KM_SLEEP
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--- old/usr/src/uts/sun4/io/px/px_mmu.c
+++ new/usr/src/uts/sun4/io/px/px_mmu.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright 2012 Garrett D'Amore <garrett@damore.org>. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * PX mmu initialization and configuration
28 28 */
29 29 #include <sys/types.h>
30 30 #include <sys/kmem.h>
31 31 #include <sys/async.h>
32 32 #include <sys/sysmacros.h>
33 33 #include <sys/sunddi.h>
34 34 #include <sys/ddi_impldefs.h>
35 35 #include <sys/vmem.h>
36 36 #include <sys/machsystm.h> /* lddphys() */
37 37 #include <sys/iommutsb.h>
38 38 #include "px_obj.h"
39 39
40 40 int
41 41 px_mmu_attach(px_t *px_p)
42 42 {
43 43 dev_info_t *dip = px_p->px_dip;
44 44 px_mmu_t *mmu_p;
45 45 uint32_t tsb_i = 0;
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46 46 char map_name[32];
47 47 px_dvma_range_prop_t *dvma_prop;
48 48 int dvma_prop_len;
49 49 uint32_t cache_size, tsb_entries;
50 50
51 51 /*
52 52 * Allocate mmu state structure and link it to the
53 53 * px state structure.
54 54 */
55 55 mmu_p = kmem_zalloc(sizeof (px_mmu_t), KM_SLEEP);
56 - if (mmu_p == NULL)
57 - return (DDI_FAILURE);
58 56
59 57 px_p->px_mmu_p = mmu_p;
60 58 mmu_p->mmu_px_p = px_p;
61 59 mmu_p->mmu_inst = ddi_get_instance(dip);
62 60
63 61 /*
64 62 * Check for "virtual-dma" property that specifies
65 63 * the DVMA range.
66 64 */
67 65 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
68 66 "virtual-dma", (caddr_t)&dvma_prop, &dvma_prop_len) !=
69 67 DDI_PROP_SUCCESS) {
70 68
71 69 DBG(DBG_ATTACH, dip, "Getting virtual-dma failed\n");
72 70
73 71 kmem_free(mmu_p, sizeof (px_mmu_t));
74 72 px_p->px_mmu_p = NULL;
75 73
76 74 return (DDI_FAILURE);
77 75 }
78 76
79 77 mmu_p->mmu_dvma_base = dvma_prop->dvma_base;
80 78 mmu_p->mmu_dvma_end = dvma_prop->dvma_base +
81 79 (dvma_prop->dvma_len - 1);
82 80 tsb_entries = MMU_BTOP(dvma_prop->dvma_len);
83 81
84 82 kmem_free(dvma_prop, dvma_prop_len);
85 83
86 84 /*
87 85 * Setup base and bounds for DVMA and bypass mappings.
88 86 */
89 87 mmu_p->mmu_dvma_cache_locks =
90 88 kmem_zalloc(px_dvma_page_cache_entries, KM_SLEEP);
91 89
92 90 mmu_p->dvma_base_pg = MMU_BTOP(mmu_p->mmu_dvma_base);
93 91 mmu_p->mmu_dvma_reserve = tsb_entries >> 1;
94 92 mmu_p->dvma_end_pg = MMU_BTOP(mmu_p->mmu_dvma_end);
95 93
96 94 /*
97 95 * Create a virtual memory map for dvma address space.
98 96 * Reserve 'size' bytes of low dvma space for fast track cache.
99 97 */
100 98 (void) snprintf(map_name, sizeof (map_name), "%s%d_dvma",
101 99 ddi_driver_name(dip), ddi_get_instance(dip));
102 100
103 101 cache_size = MMU_PTOB(px_dvma_page_cache_entries *
104 102 px_dvma_page_cache_clustsz);
105 103 mmu_p->mmu_dvma_fast_end = mmu_p->mmu_dvma_base +
106 104 cache_size - 1;
107 105
108 106 mmu_p->mmu_dvma_map = vmem_create(map_name,
109 107 (void *)(mmu_p->mmu_dvma_fast_end + 1),
110 108 MMU_PTOB(tsb_entries) - cache_size, MMU_PAGE_SIZE,
111 109 NULL, NULL, NULL, MMU_PAGE_SIZE, VM_SLEEP);
112 110
113 111 mutex_init(&mmu_p->dvma_debug_lock, NULL, MUTEX_DRIVER, NULL);
114 112
115 113 for (tsb_i = 0; tsb_i < tsb_entries; tsb_i++) {
116 114 r_addr_t ra = 0;
117 115 io_attributes_t attr;
118 116 caddr_t va;
119 117
120 118 if (px_lib_iommu_getmap(px_p->px_dip, PCI_TSBID(0, tsb_i),
121 119 &attr, &ra) != DDI_SUCCESS)
122 120 continue;
123 121
124 122 va = (caddr_t)(MMU_PTOB(mmu_p->dvma_base_pg + tsb_i));
125 123
126 124 if (va <= (caddr_t)mmu_p->mmu_dvma_fast_end) {
127 125 uint32_t cache_i;
128 126
129 127 /*
130 128 * the va is within the *fast* dvma range; therefore,
131 129 * lock its fast dvma page cache cluster in order to
132 130 * both preserve the TTE and prevent the use of this
133 131 * fast dvma page cache cluster by px_dvma_map_fast().
134 132 * the lock value 0xFF comes from ldstub().
135 133 */
136 134 cache_i = tsb_i / px_dvma_page_cache_clustsz;
137 135 ASSERT(cache_i < px_dvma_page_cache_entries);
138 136 mmu_p->mmu_dvma_cache_locks[cache_i] = 0xFF;
139 137 } else {
140 138 (void) vmem_xalloc(mmu_p->mmu_dvma_map, MMU_PAGE_SIZE,
141 139 MMU_PAGE_SIZE, 0, 0, va, va + MMU_PAGE_SIZE,
142 140 VM_NOSLEEP | VM_BESTFIT | VM_PANIC);
143 141 }
144 142 }
145 143
146 144 return (DDI_SUCCESS);
147 145 }
148 146
149 147 void
150 148 px_mmu_detach(px_t *px_p)
151 149 {
152 150 px_mmu_t *mmu_p = px_p->px_mmu_p;
153 151
154 152 (void) px_lib_iommu_detach(px_p);
155 153
156 154 /*
157 155 * Free the dvma resource map.
158 156 */
159 157 vmem_destroy(mmu_p->mmu_dvma_map);
160 158
161 159 kmem_free(mmu_p->mmu_dvma_cache_locks,
162 160 px_dvma_page_cache_entries);
163 161
164 162 if (PX_DVMA_DBG_ON(mmu_p))
165 163 px_dvma_debug_fini(mmu_p);
166 164
167 165 mutex_destroy(&mmu_p->dvma_debug_lock);
168 166
169 167 /*
170 168 * Free the mmu state structure.
171 169 */
172 170 kmem_free(mmu_p, sizeof (px_mmu_t));
173 171 px_p->px_mmu_p = NULL;
174 172 }
175 173
176 174 int
177 175 px_mmu_map_pages(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, px_dvma_addr_t dvma_pg,
178 176 size_t npages, size_t pfn_index)
179 177 {
180 178 dev_info_t *dip = mmu_p->mmu_px_p->px_dip;
181 179 px_dvma_addr_t pg_index = MMU_PAGE_INDEX(mmu_p, dvma_pg);
182 180 io_attributes_t attr = PX_GET_MP_TTE(mp->dmai_tte);
183 181
184 182 ASSERT(npages <= mp->dmai_ndvmapages);
185 183 DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages:%x+%x=%x "
186 184 "npages=0x%x pfn_index=0x%x\n", (uint_t)mmu_p->dvma_base_pg,
187 185 (uint_t)pg_index, dvma_pg, (uint_t)npages, (uint_t)pfn_index);
188 186
189 187 if (px_lib_iommu_map(dip, PCI_TSBID(0, pg_index), npages,
190 188 PX_ADD_ATTR_EXTNS(attr, mp->dmai_bdf), (void *)mp, pfn_index,
191 189 MMU_MAP_PFN) != DDI_SUCCESS) {
192 190 DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages: "
193 191 "px_lib_iommu_map failed\n");
194 192
195 193 return (DDI_FAILURE);
196 194 }
197 195
198 196 if (!PX_MAP_BUFZONE(mp))
199 197 goto done;
200 198
201 199 DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages: redzone pg=%x\n",
202 200 pg_index + npages);
203 201
204 202 ASSERT(PX_HAS_REDZONE(mp));
205 203
206 204 if (px_lib_iommu_map(dip, PCI_TSBID(0, pg_index + npages), 1,
207 205 PX_ADD_ATTR_EXTNS(attr, mp->dmai_bdf), (void *)mp,
208 206 pfn_index + npages - 1, MMU_MAP_PFN) != DDI_SUCCESS) {
209 207 DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages: mapping "
210 208 "REDZONE page failed\n");
211 209
212 210 if (px_lib_iommu_demap(dip, PCI_TSBID(0, pg_index), npages)
213 211 != DDI_SUCCESS) {
214 212 DBG(DBG_MAP_WIN, dip, "px_lib_iommu_demap: failed\n");
215 213 }
216 214 return (DDI_FAILURE);
217 215 }
218 216
219 217 done:
220 218 if (PX_DVMA_DBG_ON(mmu_p))
221 219 px_dvma_alloc_debug(mmu_p, (char *)mp->dmai_mapping,
222 220 mp->dmai_size, mp);
223 221
224 222 return (DDI_SUCCESS);
225 223 }
226 224
227 225 void
228 226 px_mmu_unmap_pages(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, px_dvma_addr_t dvma_pg,
229 227 uint_t npages)
230 228 {
231 229 px_dvma_addr_t pg_index = MMU_PAGE_INDEX(mmu_p, dvma_pg);
232 230
233 231 DBG(DBG_UNMAP_WIN, mmu_p->mmu_px_p->px_dip,
234 232 "px_mmu_unmap_pages:%x+%x=%x npages=0x%x\n",
235 233 (uint_t)mmu_p->dvma_base_pg, (uint_t)pg_index, dvma_pg,
236 234 (uint_t)npages);
237 235
238 236 if (px_lib_iommu_demap(mmu_p->mmu_px_p->px_dip,
239 237 PCI_TSBID(0, pg_index), npages) != DDI_SUCCESS) {
240 238 DBG(DBG_UNMAP_WIN, mmu_p->mmu_px_p->px_dip,
241 239 "px_lib_iommu_demap: failed\n");
242 240 }
243 241
244 242 if (!PX_MAP_BUFZONE(mp))
245 243 return;
246 244
247 245 DBG(DBG_UNMAP_WIN, mmu_p->mmu_px_p->px_dip, "px_mmu_unmap_pages: "
248 246 "redzone pg=%x\n", pg_index + npages);
249 247
250 248 ASSERT(PX_HAS_REDZONE(mp));
251 249
252 250 if (px_lib_iommu_demap(mmu_p->mmu_px_p->px_dip,
253 251 PCI_TSBID(0, pg_index + npages), 1) != DDI_SUCCESS) {
254 252 DBG(DBG_UNMAP_WIN, mmu_p->mmu_px_p->px_dip,
255 253 "px_lib_iommu_demap: failed\n");
256 254 }
257 255 }
258 256
259 257 /*
260 258 * px_mmu_map_window - map a dvma window into the mmu
261 259 * used by: px_dma_win()
262 260 * return value: none
263 261 */
264 262 /*ARGSUSED*/
265 263 int
266 264 px_mmu_map_window(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, px_window_t win_no)
267 265 {
268 266 uint32_t obj_pg0_off = mp->dmai_roffset;
269 267 uint32_t win_pg0_off = win_no ? 0 : obj_pg0_off;
270 268 size_t win_size = mp->dmai_winsize;
271 269 size_t pfn_index = win_size * win_no; /* temp value */
272 270 size_t obj_off = win_no ? pfn_index - obj_pg0_off : 0; /* xferred sz */
273 271 px_dvma_addr_t dvma_pg = MMU_BTOP(mp->dmai_mapping);
274 272 size_t res_size = mp->dmai_object.dmao_size - obj_off + win_pg0_off;
275 273 int ret = DDI_SUCCESS;
276 274
277 275 ASSERT(!(win_size & MMU_PAGE_OFFSET));
278 276 if (win_no >= mp->dmai_nwin)
279 277 return (ret);
280 278 if (res_size < win_size) /* last window */
281 279 win_size = res_size; /* mp->dmai_winsize unchanged */
282 280
283 281 mp->dmai_mapping = MMU_PTOB(dvma_pg) | win_pg0_off;
284 282 mp->dmai_size = win_size - win_pg0_off; /* cur win xferrable size */
285 283 mp->dmai_offset = obj_off; /* win offset into object */
286 284 pfn_index = MMU_BTOP(pfn_index); /* index into pfnlist */
287 285 ret = px_mmu_map_pages(mmu_p, mp, dvma_pg, MMU_BTOPR(win_size),
288 286 pfn_index);
289 287
290 288 return (ret);
291 289 }
292 290
293 291 /*
294 292 * px_mmu_unmap_window
295 293 * This routine is called to break down the mmu mappings to a dvma window.
296 294 * Non partial mappings are viewed as single window mapping.
297 295 * used by: px_dma_unbindhdl(), px_dma_window(),
298 296 * and px_dma_ctlops() - DDI_DMA_FREE, DDI_DMA_MOVWIN, DDI_DMA_NEXTWIN
299 297 * return value: none
300 298 */
301 299 /*ARGSUSED*/
302 300 void
303 301 px_mmu_unmap_window(px_mmu_t *mmu_p, ddi_dma_impl_t *mp)
304 302 {
305 303 px_dvma_addr_t dvma_pg = MMU_BTOP(mp->dmai_mapping);
306 304 uint_t npages = MMU_BTOP(mp->dmai_winsize);
307 305
308 306 px_mmu_unmap_pages(mmu_p, mp, dvma_pg, npages);
309 307
310 308 if (PX_DVMA_DBG_ON(mmu_p))
311 309 px_dvma_free_debug(mmu_p, (char *)mp->dmai_mapping,
312 310 mp->dmai_size, mp);
313 311 }
314 312
315 313
316 314 #if 0
317 315 /*
318 316 * The following table is for reference only. It denotes the
319 317 * the TSB table size measured in number of 8 byte entries.
320 318 * It is represented by bits 3:0 in the MMU TSB CTRL REG.
321 319 */
322 320 static int px_mmu_tsb_sizes[] = {
323 321 0x0, /* 1K */
324 322 0x1, /* 2K */
325 323 0x2, /* 4K */
326 324 0x3, /* 8K */
327 325 0x4, /* 16K */
328 326 0x5, /* 32K */
329 327 0x6, /* 64K */
330 328 0x7, /* 128K */
331 329 0x8 /* 256K */
332 330 };
333 331 #endif
334 332
335 333 static char *px_mmu_errsts[] = {
336 334 "Protection Error", "Invalid Error", "Timeout", "ECC Error(UE)"
337 335 };
338 336
339 337 /*ARGSUSED*/
340 338 static int
341 339 px_log_mmu_err(px_t *px_p)
342 340 {
343 341 /*
344 342 * Place holder, the correct eror bits need tobe logged.
345 343 */
346 344 return (0);
347 345 }
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