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5045 use atomic_{inc,dec}_* instead of atomic_add_*
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--- old/usr/src/uts/common/os/ddi_intr.c
+++ new/usr/src/uts/common/os/ddi_intr.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24
25 25 #include <sys/note.h>
26 26 #include <sys/sysmacros.h>
27 27 #include <sys/types.h>
28 28 #include <sys/param.h>
29 29 #include <sys/systm.h>
30 30 #include <sys/kmem.h>
31 31 #include <sys/cmn_err.h>
32 32 #include <sys/debug.h>
33 33 #include <sys/avintr.h>
34 34 #include <sys/autoconf.h>
35 35 #include <sys/sunndi.h>
36 36 #include <sys/ndi_impldefs.h> /* include prototypes */
37 37 #include <sys/atomic.h>
38 38
39 39 /*
40 40 * New DDI interrupt framework
41 41 */
42 42
43 43 /*
44 44 * ddi_intr_get_supported_types:
45 45 * Return, as a bit mask, the hardware interrupt types supported by
46 46 * both the device and by the host in the integer pointed
47 47 * to be the 'typesp' argument.
48 48 */
49 49 int
50 50 ddi_intr_get_supported_types(dev_info_t *dip, int *typesp)
51 51 {
52 52 int ret;
53 53 ddi_intr_handle_impl_t hdl;
54 54
55 55 if (dip == NULL)
56 56 return (DDI_EINVAL);
57 57
58 58 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_get_supported_types: dip %p\n",
59 59 (void *)dip));
60 60
61 61 if (*typesp = i_ddi_intr_get_supported_types(dip))
62 62 return (DDI_SUCCESS);
63 63
64 64 bzero(&hdl, sizeof (ddi_intr_handle_impl_t));
65 65 hdl.ih_dip = dip;
66 66
67 67 ret = i_ddi_intr_ops(dip, dip, DDI_INTROP_SUPPORTED_TYPES, &hdl,
68 68 (void *)typesp);
69 69
70 70 if (ret != DDI_SUCCESS)
71 71 return (DDI_INTR_NOTFOUND);
72 72
73 73 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_get_supported_types: types %x\n",
74 74 *typesp));
75 75
76 76 return (ret);
77 77 }
78 78
79 79 /*
80 80 * ddi_intr_get_nintrs:
81 81 * Return as an integer in the integer pointed to by the argument
82 82 * *nintrsp*, the number of interrupts the device supports for the
83 83 * given interrupt type.
84 84 */
85 85 int
86 86 ddi_intr_get_nintrs(dev_info_t *dip, int type, int *nintrsp)
87 87 {
88 88 int ret;
89 89 ddi_intr_handle_impl_t hdl;
90 90
91 91 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_get_nintrs: dip %p, type: %d\n",
92 92 (void *)dip, type));
93 93
94 94 if ((dip == NULL) || (nintrsp == NULL) ||
95 95 !DDI_INTR_TYPE_FLAG_VALID(type) ||
96 96 !(i_ddi_intr_get_supported_types(dip) & type)) {
97 97 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_get_nintrs: "
98 98 "Invalid input args\n"));
99 99 return (DDI_EINVAL);
100 100 }
101 101
102 102 if (*nintrsp = i_ddi_intr_get_supported_nintrs(dip, type))
103 103 return (DDI_SUCCESS);
104 104
105 105 bzero(&hdl, sizeof (ddi_intr_handle_impl_t));
106 106 hdl.ih_dip = dip;
107 107 hdl.ih_type = type;
108 108
109 109 ret = i_ddi_intr_ops(dip, dip, DDI_INTROP_NINTRS, &hdl,
110 110 (void *)nintrsp);
111 111
112 112 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_get_nintrs:: nintrs %x\n",
113 113 *nintrsp));
114 114
115 115 return (ret);
116 116 }
117 117
118 118 /*
119 119 * ddi_intr_get_navail:
120 120 * Bus nexus driver will return availble interrupt count value for
121 121 * a given interrupt type.
122 122 *
123 123 * Return as an integer in the integer pointed to by the argument
124 124 * *navailp*, the number of interrupts currently available for the
125 125 * given interrupt type.
126 126 */
127 127 int
128 128 ddi_intr_get_navail(dev_info_t *dip, int type, int *navailp)
129 129 {
130 130 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_get_navail: dip %p, type: %d\n",
131 131 (void *)dip, type));
132 132
133 133 if ((dip == NULL) || (navailp == NULL) ||
134 134 !DDI_INTR_TYPE_FLAG_VALID(type) ||
135 135 !(i_ddi_intr_get_supported_types(dip) & type)) {
136 136 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_get_navail: "
137 137 "Invalid input args\n"));
138 138 return (DDI_EINVAL);
139 139 }
140 140
141 141 if ((*navailp = i_ddi_intr_get_current_navail(dip, type)) == 0)
142 142 return (DDI_INTR_NOTFOUND);
143 143
144 144 return (DDI_SUCCESS);
145 145 }
146 146
147 147 /*
148 148 * Interrupt allocate/free functions
149 149 */
150 150 int
151 151 ddi_intr_alloc(dev_info_t *dip, ddi_intr_handle_t *h_array, int type, int inum,
152 152 int count, int *actualp, int behavior)
153 153 {
154 154 ddi_intr_handle_impl_t *hdlp, tmp_hdl;
155 155 int i, ret, cap = 0, curr_type, nintrs;
156 156 uint_t pri, navail, curr_nintrs = 0;
157 157
158 158 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: name %s dip 0x%p "
159 159 "type %x inum %x count %x behavior %x\n", ddi_driver_name(dip),
160 160 (void *)dip, type, inum, count, behavior));
161 161
162 162 /* Validate parameters */
163 163 if ((dip == NULL) || (h_array == NULL) || (inum < 0) || (count < 1) ||
164 164 (actualp == NULL) || !DDI_INTR_BEHAVIOR_FLAG_VALID(behavior)) {
165 165 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: "
166 166 "Invalid input args\n"));
167 167 return (DDI_EINVAL);
168 168 }
169 169
170 170 /* Validate interrupt type */
171 171 if (!DDI_INTR_TYPE_FLAG_VALID(type) ||
172 172 !(i_ddi_intr_get_supported_types(dip) & type)) {
173 173 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: type %x not "
174 174 "supported\n", type));
175 175 return (DDI_EINVAL);
176 176 }
177 177
178 178 /* Validate inum not previously allocated */
179 179 if ((type == DDI_INTR_TYPE_FIXED) &&
180 180 (i_ddi_get_intr_handle(dip, inum) != NULL)) {
181 181 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: inum %d is already "
182 182 "in use, cannot allocate again!!\n", inum));
183 183 return (DDI_EINVAL);
184 184 }
185 185
186 186 /* Get how many interrupts the device supports */
187 187 if ((nintrs = i_ddi_intr_get_supported_nintrs(dip, type)) == 0) {
188 188 if (ddi_intr_get_nintrs(dip, type, &nintrs) != DDI_SUCCESS) {
189 189 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: no "
190 190 "interrupts found of type %d\n", type));
191 191 return (DDI_INTR_NOTFOUND);
192 192 }
193 193 }
194 194
195 195 /* Get how many interrupts the device is already using */
196 196 if ((curr_type = i_ddi_intr_get_current_type(dip)) != 0) {
197 197 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: type %x "
198 198 "is already being used\n", curr_type));
199 199 curr_nintrs = i_ddi_intr_get_current_nintrs(dip);
200 200 }
201 201
202 202 /* Validate interrupt type consistency */
203 203 if ((curr_type != 0) && (type != curr_type)) {
204 204 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: Requested "
205 205 "interrupt type %x is different from interrupt type %x"
206 206 "already in use\n", type, curr_type));
207 207 return (DDI_EINVAL);
208 208 }
209 209
210 210 /* Validate count does not exceed what device supports */
211 211 if (count > nintrs) {
212 212 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: no of interrupts "
213 213 "requested %d is more than supported %d\n", count, nintrs));
214 214 return (DDI_EINVAL);
215 215 } else if ((count + curr_nintrs) > nintrs) {
216 216 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: count %d "
217 217 "+ intrs in use %d exceeds supported %d intrs\n",
218 218 count, curr_nintrs, nintrs));
219 219 return (DDI_EINVAL);
220 220 }
221 221
222 222 /* Validate power of 2 requirements for MSI */
223 223 if ((type == DDI_INTR_TYPE_MSI) && !ISP2(curr_nintrs + count)) {
224 224 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: "
225 225 "MSI count %d is not a power of two\n", count));
226 226 return (DDI_EINVAL);
227 227 }
228 228
229 229 /*
230 230 * Initialize the device's interrupt information structure,
231 231 * and establish an association with IRM if it is supported.
232 232 *
233 233 * NOTE: IRM checks minimum support, and can return DDI_EAGAIN.
234 234 */
235 235 if (curr_nintrs == 0) {
236 236 i_ddi_intr_devi_init(dip);
237 237 if (i_ddi_irm_insert(dip, type, count) == DDI_EAGAIN) {
238 238 cmn_err(CE_WARN, "ddi_intr_alloc: "
239 239 "cannot fit into interrupt pool\n");
240 240 return (DDI_EAGAIN);
241 241 }
242 242 }
243 243
244 244 /* Synchronously adjust IRM associations for non-IRM aware drivers */
245 245 if (curr_nintrs && (i_ddi_irm_supported(dip, type) != DDI_SUCCESS))
246 246 (void) i_ddi_irm_modify(dip, count + curr_nintrs);
247 247
248 248 /* Get how many interrupts are currently available */
249 249 navail = i_ddi_intr_get_current_navail(dip, type);
250 250
251 251 /* Validate that requested number of interrupts are available */
252 252 if (curr_nintrs == navail) {
253 253 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: max # of intrs %d "
254 254 "already allocated\n", navail));
255 255 return (DDI_EAGAIN);
256 256 }
257 257 if ((count + curr_nintrs) > navail) {
258 258 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: requested # of "
259 259 "intrs %d exceeds # of available intrs %d\n", count,
260 260 navail - curr_nintrs));
261 261 if (behavior == DDI_INTR_ALLOC_STRICT) {
262 262 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: "
263 263 "DDI_INTR_ALLOC_STRICT flag is passed, "
264 264 "return failure\n"));
265 265 if (curr_nintrs == 0)
266 266 i_ddi_intr_devi_fini(dip);
267 267 else if (i_ddi_irm_supported(dip, type) != DDI_SUCCESS)
268 268 (void) i_ddi_irm_modify(dip, curr_nintrs);
269 269 return (DDI_EAGAIN);
270 270 }
271 271 count = navail - curr_nintrs;
272 272 }
273 273
274 274 /* Now allocate required number of interrupts */
275 275 bzero(&tmp_hdl, sizeof (ddi_intr_handle_impl_t));
276 276 tmp_hdl.ih_type = type;
277 277 tmp_hdl.ih_inum = inum;
278 278 tmp_hdl.ih_scratch1 = count;
279 279 tmp_hdl.ih_scratch2 = (void *)(uintptr_t)behavior;
280 280 tmp_hdl.ih_dip = dip;
281 281
282 282 if (i_ddi_intr_ops(dip, dip, DDI_INTROP_ALLOC,
283 283 &tmp_hdl, (void *)actualp) != DDI_SUCCESS) {
284 284 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: allocation "
285 285 "failed\n"));
286 286 i_ddi_intr_devi_fini(dip);
287 287 return (*actualp ? DDI_EAGAIN : DDI_INTR_NOTFOUND);
288 288 }
289 289
290 290 if ((ret = i_ddi_intr_ops(dip, dip, DDI_INTROP_GETPRI,
291 291 &tmp_hdl, (void *)&pri)) != DDI_SUCCESS) {
292 292 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: get priority "
293 293 "failed\n"));
294 294 goto fail;
295 295 }
296 296
297 297 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: getting capability\n"));
298 298
299 299 if ((ret = i_ddi_intr_ops(dip, dip, DDI_INTROP_GETCAP,
300 300 &tmp_hdl, (void *)&cap)) != DDI_SUCCESS) {
301 301 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: get capability "
302 302 "failed\n"));
303 303 goto fail;
304 304 }
305 305
306 306 /*
307 307 * Save current interrupt type, supported and current intr count.
308 308 */
309 309 i_ddi_intr_set_current_type(dip, type);
310 310 i_ddi_intr_set_supported_nintrs(dip, nintrs);
311 311 i_ddi_intr_set_current_nintrs(dip,
312 312 i_ddi_intr_get_current_nintrs(dip) + *actualp);
313 313
314 314 /* Now, go and handle each "handle" */
315 315 for (i = inum; i < (inum + *actualp); i++) {
316 316 hdlp = (ddi_intr_handle_impl_t *)kmem_zalloc(
317 317 (sizeof (ddi_intr_handle_impl_t)), KM_SLEEP);
318 318 rw_init(&hdlp->ih_rwlock, NULL, RW_DRIVER, NULL);
319 319 h_array[i] = (struct __ddi_intr_handle *)hdlp;
320 320 hdlp->ih_type = type;
321 321 hdlp->ih_pri = pri;
322 322 hdlp->ih_cap = cap;
323 323 hdlp->ih_ver = DDI_INTR_VERSION;
324 324 hdlp->ih_state = DDI_IHDL_STATE_ALLOC;
325 325 hdlp->ih_dip = dip;
326 326 hdlp->ih_inum = i;
327 327 i_ddi_alloc_intr_phdl(hdlp);
328 328 if (type & DDI_INTR_TYPE_FIXED)
329 329 i_ddi_set_intr_handle(dip, hdlp->ih_inum,
330 330 (ddi_intr_handle_t)hdlp);
331 331
332 332 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_alloc: hdlp = 0x%p\n",
333 333 (void *)h_array[i]));
334 334 }
335 335
336 336 return (DDI_SUCCESS);
337 337
338 338 fail:
339 339 (void) i_ddi_intr_ops(tmp_hdl.ih_dip, tmp_hdl.ih_dip,
340 340 DDI_INTROP_FREE, &tmp_hdl, NULL);
341 341 i_ddi_intr_devi_fini(dip);
342 342
343 343 return (ret);
344 344 }
345 345
346 346 int
347 347 ddi_intr_free(ddi_intr_handle_t h)
348 348 {
349 349 ddi_intr_handle_impl_t *hdlp = (ddi_intr_handle_impl_t *)h;
350 350 int ret;
351 351
352 352 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_free: hdlp = %p\n", (void *)hdlp));
353 353
354 354 if (hdlp == NULL)
355 355 return (DDI_EINVAL);
356 356
357 357 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
358 358 if (((hdlp->ih_flags & DDI_INTR_MSIX_DUP) &&
359 359 (hdlp->ih_state != DDI_IHDL_STATE_ADDED)) ||
360 360 ((hdlp->ih_state != DDI_IHDL_STATE_ALLOC) &&
361 361 (!(hdlp->ih_flags & DDI_INTR_MSIX_DUP)))) {
362 362 rw_exit(&hdlp->ih_rwlock);
363 363 return (DDI_EINVAL);
364 364 }
365 365
366 366 /* Set the number of interrupts to free */
367 367 hdlp->ih_scratch1 = 1;
368 368
369 369 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
370 370 DDI_INTROP_FREE, hdlp, NULL);
371 371
372 372 rw_exit(&hdlp->ih_rwlock);
373 373 if (ret == DDI_SUCCESS) {
374 374 /* This would be the dup vector */
375 375 if (hdlp->ih_flags & DDI_INTR_MSIX_DUP)
376 376 atomic_dec_32(&hdlp->ih_main->ih_dup_cnt);
377 377 else {
378 378 int n, curr_type;
379 379
380 380 n = i_ddi_intr_get_current_nintrs(hdlp->ih_dip) - 1;
381 381 curr_type = i_ddi_intr_get_current_type(hdlp->ih_dip);
382 382
383 383 i_ddi_intr_set_current_nintrs(hdlp->ih_dip, n);
384 384
385 385 if ((i_ddi_irm_supported(hdlp->ih_dip, curr_type)
386 386 != DDI_SUCCESS) && (n > 0))
387 387 (void) i_ddi_irm_modify(hdlp->ih_dip, n);
388 388
389 389 if (hdlp->ih_type & DDI_INTR_TYPE_FIXED)
390 390 i_ddi_set_intr_handle(hdlp->ih_dip,
391 391 hdlp->ih_inum, NULL);
392 392
393 393 i_ddi_intr_devi_fini(hdlp->ih_dip);
394 394 i_ddi_free_intr_phdl(hdlp);
395 395 }
396 396 rw_destroy(&hdlp->ih_rwlock);
397 397 kmem_free(hdlp, sizeof (ddi_intr_handle_impl_t));
398 398 }
399 399
400 400 return (ret);
401 401 }
402 402
403 403 /*
404 404 * Interrupt get/set capacity functions
405 405 *
406 406 * The logic used to figure this out is shown here:
407 407 *
408 408 * Device level Platform level Intr source
409 409 * 1. Fixed interrupts
410 410 * (non-PCI)
411 411 * o Flags supported N/A Maskable/Pending/ rootnex
412 412 * No Block Enable
413 413 * o navail 1
414 414 *
415 415 * 2. PCI Fixed interrupts
416 416 * o Flags supported pending/Maskable Maskable/pending/ pci
417 417 * No Block enable
418 418 * o navail N/A 1
419 419 *
420 420 * 3. PCI MSI
421 421 * o Flags supported Maskable/Pending Maskable/Pending pci
422 422 * Block Enable (if drvr doesn't) Block Enable
423 423 * o navail N/A #vectors - #used N/A
424 424 *
425 425 * 4. PCI MSI-X
426 426 * o Flags supported Maskable/Pending Maskable/Pending pci
427 427 * Block Enable Block Enable
428 428 * o navail N/A #vectors - #used N/A
429 429 *
430 430 * where:
431 431 * #vectors - Total numbers of vectors available
432 432 * #used - Total numbers of vectors currently being used
433 433 *
434 434 * For devices complying to PCI2.3 or greater, see bit10 of Command Register
435 435 * 0 - enables assertion of INTx
436 436 * 1 - disables assertion of INTx
437 437 *
438 438 * For non MSI/X interrupts; if the IRQ is shared then all ddi_intr_set_*()
439 439 * operations return failure.
440 440 */
441 441 int
442 442 ddi_intr_get_cap(ddi_intr_handle_t h, int *flagsp)
443 443 {
444 444 ddi_intr_handle_impl_t *hdlp = (ddi_intr_handle_impl_t *)h;
445 445 int ret;
446 446
447 447 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_get_cap: hdlp = %p\n",
448 448 (void *)hdlp));
449 449
450 450 *flagsp = 0;
451 451 if (hdlp == NULL)
452 452 return (DDI_EINVAL);
453 453
454 454 rw_enter(&hdlp->ih_rwlock, RW_READER);
455 455
456 456 if (hdlp->ih_cap) {
457 457 *flagsp = hdlp->ih_cap & ~DDI_INTR_FLAG_MSI64;
458 458 rw_exit(&hdlp->ih_rwlock);
459 459 return (DDI_SUCCESS);
460 460 }
461 461
462 462 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
463 463 DDI_INTROP_GETCAP, hdlp, (void *)flagsp);
464 464
465 465 if (ret == DDI_SUCCESS) {
466 466 hdlp->ih_cap = *flagsp;
467 467
468 468 /* Mask out MSI/X 64-bit support to the consumer */
469 469 *flagsp &= ~DDI_INTR_FLAG_MSI64;
470 470 }
471 471
472 472 rw_exit(&hdlp->ih_rwlock);
473 473 return (ret);
474 474 }
475 475
476 476 int
477 477 ddi_intr_set_cap(ddi_intr_handle_t h, int flags)
478 478 {
479 479 ddi_intr_handle_impl_t *hdlp = (ddi_intr_handle_impl_t *)h;
480 480 int ret;
481 481
482 482 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_set_cap: hdlp = %p", (void *)hdlp));
483 483
484 484 if (hdlp == NULL)
485 485 return (DDI_EINVAL);
486 486
487 487 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
488 488 if (hdlp->ih_state != DDI_IHDL_STATE_ALLOC) {
489 489 rw_exit(&hdlp->ih_rwlock);
490 490 return (DDI_EINVAL);
491 491 }
492 492
493 493 /* Only DDI_INTR_FLAG_LEVEL or DDI_INTR_FLAG_EDGE are allowed */
494 494 if (!(flags & (DDI_INTR_FLAG_EDGE | DDI_INTR_FLAG_LEVEL))) {
495 495 DDI_INTR_APIDBG((CE_CONT, "%s%d: only LEVEL or EDGE capability "
496 496 "can be set\n", ddi_driver_name(hdlp->ih_dip),
497 497 ddi_get_instance(hdlp->ih_dip)));
498 498 rw_exit(&hdlp->ih_rwlock);
499 499 return (DDI_EINVAL);
500 500 }
501 501
502 502 /* Both level/edge flags must be currently supported */
503 503 if (!(hdlp->ih_cap & (DDI_INTR_FLAG_EDGE | DDI_INTR_FLAG_LEVEL))) {
504 504 DDI_INTR_APIDBG((CE_CONT, "%s%d: Both LEVEL and EDGE capability"
505 505 " must be supported\n", ddi_driver_name(hdlp->ih_dip),
506 506 ddi_get_instance(hdlp->ih_dip)));
507 507 rw_exit(&hdlp->ih_rwlock);
508 508 return (DDI_ENOTSUP);
509 509 }
510 510
511 511 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
512 512 DDI_INTROP_SETCAP, hdlp, &flags);
513 513
514 514 rw_exit(&hdlp->ih_rwlock);
515 515 return (ret);
516 516 }
517 517
518 518 /*
519 519 * Priority related functions
520 520 */
521 521
522 522 /*
523 523 * ddi_intr_get_hilevel_pri:
524 524 * Returns the minimum priority level for a
525 525 * high-level interrupt on a platform.
526 526 */
527 527 uint_t
528 528 ddi_intr_get_hilevel_pri(void)
529 529 {
530 530 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_get_hilevel_pri:\n"));
531 531 return (LOCK_LEVEL + 1);
532 532 }
533 533
534 534 int
535 535 ddi_intr_get_pri(ddi_intr_handle_t h, uint_t *prip)
536 536 {
537 537 ddi_intr_handle_impl_t *hdlp = (ddi_intr_handle_impl_t *)h;
538 538 int ret;
539 539
540 540 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_get_pri: hdlp = %p\n",
541 541 (void *)hdlp));
542 542
543 543 *prip = 0;
544 544 if (hdlp == NULL)
545 545 return (DDI_EINVAL);
546 546
547 547 rw_enter(&hdlp->ih_rwlock, RW_READER);
548 548 /* Already initialized, just return that */
549 549 if (hdlp->ih_pri) {
550 550 *prip = hdlp->ih_pri;
551 551 rw_exit(&hdlp->ih_rwlock);
552 552 return (DDI_SUCCESS);
553 553 }
554 554
555 555 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
556 556 DDI_INTROP_GETPRI, hdlp, (void *)prip);
557 557
558 558 if (ret == DDI_SUCCESS)
559 559 hdlp->ih_pri = *prip;
560 560
561 561 rw_exit(&hdlp->ih_rwlock);
562 562 return (ret);
563 563 }
564 564
565 565 int
566 566 ddi_intr_set_pri(ddi_intr_handle_t h, uint_t pri)
567 567 {
568 568 ddi_intr_handle_impl_t *hdlp = (ddi_intr_handle_impl_t *)h;
569 569 int ret;
570 570
571 571 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_set_pri: hdlp = %p", (void *)hdlp));
572 572
573 573 if (hdlp == NULL)
574 574 return (DDI_EINVAL);
575 575
576 576 /* Validate priority argument */
577 577 if (pri < DDI_INTR_PRI_MIN || pri > DDI_INTR_PRI_MAX) {
578 578 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_set_pri: invalid priority "
579 579 "specified = %x\n", pri));
580 580 return (DDI_EINVAL);
581 581 }
582 582
583 583 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
584 584 if (hdlp->ih_state != DDI_IHDL_STATE_ALLOC) {
585 585 rw_exit(&hdlp->ih_rwlock);
586 586 return (DDI_EINVAL);
587 587 }
588 588
589 589 /* If the passed priority is same as existing priority; do nothing */
590 590 if (pri == hdlp->ih_pri) {
591 591 rw_exit(&hdlp->ih_rwlock);
592 592 return (DDI_SUCCESS);
593 593 }
594 594
595 595 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
596 596 DDI_INTROP_SETPRI, hdlp, &pri);
597 597
598 598 if (ret == DDI_SUCCESS)
599 599 hdlp->ih_pri = pri;
600 600
601 601 rw_exit(&hdlp->ih_rwlock);
602 602 return (ret);
603 603 }
604 604
605 605 /*
606 606 * Interrupt add/duplicate/remove handlers
607 607 */
608 608 int
609 609 ddi_intr_add_handler(ddi_intr_handle_t h, ddi_intr_handler_t inthandler,
610 610 void *arg1, void *arg2)
611 611 {
612 612 ddi_intr_handle_impl_t *hdlp = (ddi_intr_handle_impl_t *)h;
613 613 int ret;
614 614
615 615 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_add_handler: hdlp = 0x%p\n",
616 616 (void *)hdlp));
617 617
618 618 if ((hdlp == NULL) || (inthandler == NULL))
619 619 return (DDI_EINVAL);
620 620
621 621 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
622 622 if (hdlp->ih_state != DDI_IHDL_STATE_ALLOC) {
623 623 rw_exit(&hdlp->ih_rwlock);
624 624 return (DDI_EINVAL);
625 625 }
626 626
627 627 hdlp->ih_cb_func = inthandler;
628 628 hdlp->ih_cb_arg1 = arg1;
629 629 hdlp->ih_cb_arg2 = arg2;
630 630
631 631 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
632 632 DDI_INTROP_ADDISR, hdlp, NULL);
633 633
634 634 if (ret != DDI_SUCCESS) {
635 635 hdlp->ih_cb_func = NULL;
636 636 hdlp->ih_cb_arg1 = NULL;
637 637 hdlp->ih_cb_arg2 = NULL;
638 638 } else
639 639 hdlp->ih_state = DDI_IHDL_STATE_ADDED;
640 640
641 641 rw_exit(&hdlp->ih_rwlock);
642 642 return (ret);
643 643 }
644 644
645 645 int
646 646 ddi_intr_dup_handler(ddi_intr_handle_t org, int dup_inum,
647 647 ddi_intr_handle_t *dup)
648 648 {
649 649 ddi_intr_handle_impl_t *hdlp = (ddi_intr_handle_impl_t *)org;
650 650 ddi_intr_handle_impl_t *dup_hdlp;
651 651 int ret;
652 652
653 653 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_dup_handler: hdlp = 0x%p\n",
654 654 (void *)hdlp));
655 655
656 656 /* Do some input argument checking ("dup" handle is not allocated) */
657 657 if ((hdlp == NULL) || (*dup != NULL) || (dup_inum < 0)) {
658 658 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_dup_handler: Invalid "
659 659 "input args\n"));
660 660 return (DDI_EINVAL);
661 661 }
662 662
663 663 rw_enter(&hdlp->ih_rwlock, RW_READER);
664 664
665 665 /* Do some input argument checking */
666 666 if ((hdlp->ih_state == DDI_IHDL_STATE_ALLOC) || /* intr handle alloc? */
667 667 (hdlp->ih_type != DDI_INTR_TYPE_MSIX) || /* only MSI-X allowed */
668 668 (hdlp->ih_flags & DDI_INTR_MSIX_DUP)) { /* only dup original */
669 669 rw_exit(&hdlp->ih_rwlock);
670 670 return (DDI_EINVAL);
↓ open down ↓ |
670 lines elided |
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671 671 }
672 672
673 673 hdlp->ih_scratch1 = dup_inum;
674 674 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
675 675 DDI_INTROP_DUPVEC, hdlp, NULL);
676 676
677 677 if (ret == DDI_SUCCESS) {
678 678 dup_hdlp = (ddi_intr_handle_impl_t *)
679 679 kmem_alloc(sizeof (ddi_intr_handle_impl_t), KM_SLEEP);
680 680
681 - atomic_add_32(&hdlp->ih_dup_cnt, 1);
681 + atomic_inc_32(&hdlp->ih_dup_cnt);
682 682
683 683 *dup = (ddi_intr_handle_t)dup_hdlp;
684 684 bcopy(hdlp, dup_hdlp, sizeof (ddi_intr_handle_impl_t));
685 685
686 686 /* These fields are unique to each dupped msi-x vector */
687 687 rw_init(&dup_hdlp->ih_rwlock, NULL, RW_DRIVER, NULL);
688 688 dup_hdlp->ih_state = DDI_IHDL_STATE_ADDED;
689 689 dup_hdlp->ih_inum = dup_inum;
690 690 dup_hdlp->ih_flags |= DDI_INTR_MSIX_DUP;
691 691 dup_hdlp->ih_dup_cnt = 0;
692 692
693 693 /* Point back to original vector */
694 694 dup_hdlp->ih_main = hdlp;
695 695 }
696 696
697 697 rw_exit(&hdlp->ih_rwlock);
698 698 return (ret);
699 699 }
700 700
701 701 int
702 702 ddi_intr_remove_handler(ddi_intr_handle_t h)
703 703 {
704 704 ddi_intr_handle_impl_t *hdlp = (ddi_intr_handle_impl_t *)h;
705 705 int ret = DDI_SUCCESS;
706 706
707 707 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_remove_handler: hdlp = %p\n",
708 708 (void *)hdlp));
709 709
710 710 if (hdlp == NULL)
711 711 return (DDI_EINVAL);
712 712
713 713 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
714 714
715 715 if (hdlp->ih_state != DDI_IHDL_STATE_ADDED) {
716 716 ret = DDI_EINVAL;
717 717 goto done;
718 718 } else if (hdlp->ih_flags & DDI_INTR_MSIX_DUP)
719 719 goto done;
720 720
721 721 ASSERT(hdlp->ih_dup_cnt == 0);
722 722 if (hdlp->ih_dup_cnt > 0) {
723 723 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_remove_handler: MSI-X "
724 724 "dup_cnt %d is not 0\n", hdlp->ih_dup_cnt));
725 725 ret = DDI_FAILURE;
726 726 goto done;
727 727 }
728 728
729 729 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
730 730 DDI_INTROP_REMISR, hdlp, NULL);
731 731
732 732 if (ret == DDI_SUCCESS) {
733 733 hdlp->ih_state = DDI_IHDL_STATE_ALLOC;
734 734 hdlp->ih_cb_func = NULL;
735 735 hdlp->ih_cb_arg1 = NULL;
736 736 hdlp->ih_cb_arg2 = NULL;
737 737 }
738 738
739 739 done:
740 740 rw_exit(&hdlp->ih_rwlock);
741 741 return (ret);
742 742 }
743 743
744 744
745 745 /*
746 746 * Interrupt enable/disable/block_enable/block_disable handlers
747 747 */
748 748 int
749 749 ddi_intr_enable(ddi_intr_handle_t h)
750 750 {
751 751 ddi_intr_handle_impl_t *hdlp = (ddi_intr_handle_impl_t *)h;
752 752 int ret;
753 753
754 754 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_enable: hdlp = %p\n",
755 755 (void *)hdlp));
756 756
757 757 if (hdlp == NULL)
758 758 return (DDI_EINVAL);
759 759
760 760 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
761 761 if ((hdlp->ih_state != DDI_IHDL_STATE_ADDED) ||
762 762 ((hdlp->ih_type == DDI_INTR_TYPE_MSI) &&
763 763 (hdlp->ih_cap & DDI_INTR_FLAG_BLOCK))) {
764 764 rw_exit(&hdlp->ih_rwlock);
765 765 return (DDI_EINVAL);
766 766 }
767 767
768 768 I_DDI_VERIFY_MSIX_HANDLE(hdlp);
769 769
770 770 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
771 771 DDI_INTROP_ENABLE, hdlp, NULL);
772 772
773 773 if (ret == DDI_SUCCESS) {
774 774 hdlp->ih_state = DDI_IHDL_STATE_ENABLE;
775 775 i_ddi_intr_set_current_nenables(hdlp->ih_dip,
776 776 i_ddi_intr_get_current_nenables(hdlp->ih_dip) + 1);
777 777 }
778 778
779 779 rw_exit(&hdlp->ih_rwlock);
780 780 return (ret);
781 781 }
782 782
783 783 int
784 784 ddi_intr_disable(ddi_intr_handle_t h)
785 785 {
786 786 ddi_intr_handle_impl_t *hdlp = (ddi_intr_handle_impl_t *)h;
787 787 int ret;
788 788
789 789 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_disable: hdlp = %p\n",
790 790 (void *)hdlp));
791 791
792 792 if (hdlp == NULL)
793 793 return (DDI_EINVAL);
794 794
795 795 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
796 796 if ((hdlp->ih_state != DDI_IHDL_STATE_ENABLE) ||
797 797 ((hdlp->ih_type == DDI_INTR_TYPE_MSI) &&
798 798 (hdlp->ih_cap & DDI_INTR_FLAG_BLOCK))) {
799 799 rw_exit(&hdlp->ih_rwlock);
800 800 return (DDI_EINVAL);
801 801 }
802 802
803 803 I_DDI_VERIFY_MSIX_HANDLE(hdlp);
804 804
805 805 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
806 806 DDI_INTROP_DISABLE, hdlp, NULL);
807 807
808 808 if (ret == DDI_SUCCESS) {
809 809 hdlp->ih_state = DDI_IHDL_STATE_ADDED;
810 810 i_ddi_intr_set_current_nenables(hdlp->ih_dip,
811 811 i_ddi_intr_get_current_nenables(hdlp->ih_dip) - 1);
812 812 }
813 813
814 814 rw_exit(&hdlp->ih_rwlock);
815 815 return (ret);
816 816 }
817 817
818 818 int
819 819 ddi_intr_block_enable(ddi_intr_handle_t *h_array, int count)
820 820 {
821 821 ddi_intr_handle_impl_t *hdlp;
822 822 int i, ret;
823 823
824 824 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_block_enable: h_array = %p\n",
825 825 (void *)h_array));
826 826
827 827 if (h_array == NULL)
828 828 return (DDI_EINVAL);
829 829
830 830 for (i = 0; i < count; i++) {
831 831 hdlp = (ddi_intr_handle_impl_t *)h_array[i];
832 832 rw_enter(&hdlp->ih_rwlock, RW_READER);
833 833
834 834 if (hdlp->ih_state != DDI_IHDL_STATE_ADDED ||
835 835 hdlp->ih_type != DDI_INTR_TYPE_MSI ||
836 836 !(hdlp->ih_cap & DDI_INTR_FLAG_BLOCK)) {
837 837 rw_exit(&hdlp->ih_rwlock);
838 838 return (DDI_EINVAL);
839 839 }
840 840 rw_exit(&hdlp->ih_rwlock);
841 841 }
842 842
843 843 hdlp = (ddi_intr_handle_impl_t *)h_array[0];
844 844 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
845 845 hdlp->ih_scratch1 = count;
846 846 hdlp->ih_scratch2 = (void *)h_array;
847 847
848 848 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
849 849 DDI_INTROP_BLOCKENABLE, hdlp, NULL);
850 850
851 851 rw_exit(&hdlp->ih_rwlock);
852 852
853 853 if (ret == DDI_SUCCESS) {
854 854 for (i = 0; i < count; i++) {
855 855 hdlp = (ddi_intr_handle_impl_t *)h_array[i];
856 856 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
857 857 hdlp->ih_state = DDI_IHDL_STATE_ENABLE;
858 858 rw_exit(&hdlp->ih_rwlock);
859 859 }
860 860 i_ddi_intr_set_current_nenables(hdlp->ih_dip, 1);
861 861 }
862 862
863 863 return (ret);
864 864 }
865 865
866 866 int
867 867 ddi_intr_block_disable(ddi_intr_handle_t *h_array, int count)
868 868 {
869 869 ddi_intr_handle_impl_t *hdlp;
870 870 int i, ret;
871 871
872 872 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_block_disable: h_array = %p\n",
873 873 (void *)h_array));
874 874
875 875 if (h_array == NULL)
876 876 return (DDI_EINVAL);
877 877
878 878 for (i = 0; i < count; i++) {
879 879 hdlp = (ddi_intr_handle_impl_t *)h_array[i];
880 880 rw_enter(&hdlp->ih_rwlock, RW_READER);
881 881 if (hdlp->ih_state != DDI_IHDL_STATE_ENABLE ||
882 882 hdlp->ih_type != DDI_INTR_TYPE_MSI ||
883 883 !(hdlp->ih_cap & DDI_INTR_FLAG_BLOCK)) {
884 884 rw_exit(&hdlp->ih_rwlock);
885 885 return (DDI_EINVAL);
886 886 }
887 887 rw_exit(&hdlp->ih_rwlock);
888 888 }
889 889
890 890 hdlp = (ddi_intr_handle_impl_t *)h_array[0];
891 891 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
892 892 hdlp->ih_scratch1 = count;
893 893 hdlp->ih_scratch2 = (void *)h_array;
894 894
895 895 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
896 896 DDI_INTROP_BLOCKDISABLE, hdlp, NULL);
897 897
898 898 rw_exit(&hdlp->ih_rwlock);
899 899
900 900 if (ret == DDI_SUCCESS) {
901 901 for (i = 0; i < count; i++) {
902 902 hdlp = (ddi_intr_handle_impl_t *)h_array[i];
903 903 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
904 904 hdlp->ih_state = DDI_IHDL_STATE_ADDED;
905 905 rw_exit(&hdlp->ih_rwlock);
906 906 }
907 907 i_ddi_intr_set_current_nenables(hdlp->ih_dip, 0);
908 908 }
909 909
910 910 return (ret);
911 911 }
912 912
913 913 /*
914 914 * Interrupt set/clr mask handlers
915 915 */
916 916 int
917 917 ddi_intr_set_mask(ddi_intr_handle_t h)
918 918 {
919 919 ddi_intr_handle_impl_t *hdlp = (ddi_intr_handle_impl_t *)h;
920 920 int ret;
921 921
922 922 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_set_mask: hdlp = %p\n",
923 923 (void *)hdlp));
924 924
925 925 if (hdlp == NULL)
926 926 return (DDI_EINVAL);
927 927
928 928 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
929 929 if ((hdlp->ih_state != DDI_IHDL_STATE_ENABLE) ||
930 930 (!(hdlp->ih_cap & DDI_INTR_FLAG_MASKABLE))) {
931 931 rw_exit(&hdlp->ih_rwlock);
932 932 return (DDI_EINVAL);
933 933 }
934 934
935 935 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
936 936 DDI_INTROP_SETMASK, hdlp, NULL);
937 937
938 938 rw_exit(&hdlp->ih_rwlock);
939 939 return (ret);
940 940 }
941 941
942 942 int
943 943 ddi_intr_clr_mask(ddi_intr_handle_t h)
944 944 {
945 945 ddi_intr_handle_impl_t *hdlp = (ddi_intr_handle_impl_t *)h;
946 946 int ret;
947 947
948 948 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_clr_mask: hdlp = %p\n",
949 949 (void *)hdlp));
950 950
951 951 if (hdlp == NULL)
952 952 return (DDI_EINVAL);
953 953
954 954 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
955 955 if ((hdlp->ih_state != DDI_IHDL_STATE_ENABLE) ||
956 956 (!(hdlp->ih_cap & DDI_INTR_FLAG_MASKABLE))) {
957 957 rw_exit(&hdlp->ih_rwlock);
958 958 return (DDI_EINVAL);
959 959 }
960 960
961 961 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
962 962 DDI_INTROP_CLRMASK, hdlp, NULL);
963 963
964 964 rw_exit(&hdlp->ih_rwlock);
965 965 return (ret);
966 966 }
967 967
968 968 /*
969 969 * Interrupt get_pending handler
970 970 */
971 971 int
972 972 ddi_intr_get_pending(ddi_intr_handle_t h, int *pendingp)
973 973 {
974 974 ddi_intr_handle_impl_t *hdlp = (ddi_intr_handle_impl_t *)h;
975 975 int ret;
976 976
977 977 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_get_pending: hdlp = %p\n",
978 978 (void *)hdlp));
979 979
980 980 if (hdlp == NULL)
981 981 return (DDI_EINVAL);
982 982
983 983 rw_enter(&hdlp->ih_rwlock, RW_READER);
984 984 if (!(hdlp->ih_cap & DDI_INTR_FLAG_PENDING)) {
985 985 rw_exit(&hdlp->ih_rwlock);
986 986 return (DDI_EINVAL);
987 987 }
988 988
989 989 ret = i_ddi_intr_ops(hdlp->ih_dip, hdlp->ih_dip,
990 990 DDI_INTROP_GETPENDING, hdlp, (void *)pendingp);
991 991
992 992 rw_exit(&hdlp->ih_rwlock);
993 993 return (ret);
994 994 }
995 995
996 996 /*
997 997 * Set the number of interrupts requested from IRM
998 998 */
999 999 int
1000 1000 ddi_intr_set_nreq(dev_info_t *dip, int nreq)
1001 1001 {
1002 1002 int curr_type, nintrs;
1003 1003
1004 1004 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_set_nreq: dip %p, nreq %d\n",
1005 1005 (void *)dip, nreq));
1006 1006
1007 1007 ASSERT(dip != NULL);
1008 1008 ASSERT(nreq > 0);
1009 1009
1010 1010 /* Sanity check inputs */
1011 1011 if ((dip == NULL) || (nreq < 1))
1012 1012 return (DDI_EINVAL);
1013 1013
1014 1014 curr_type = i_ddi_intr_get_current_type(dip);
1015 1015
1016 1016 /* Only valid for IRM drivers actively using interrupts */
1017 1017 if ((curr_type == 0) ||
1018 1018 (i_ddi_irm_supported(dip, curr_type) != DDI_SUCCESS))
1019 1019 return (DDI_ENOTSUP);
1020 1020
1021 1021 /* Range check */
1022 1022 if (ddi_intr_get_nintrs(dip, curr_type, &nintrs) != DDI_SUCCESS)
1023 1023 return (DDI_FAILURE);
1024 1024 if (nreq > nintrs)
1025 1025 return (DDI_EINVAL);
1026 1026
1027 1027 return (i_ddi_irm_modify(dip, nreq));
1028 1028 }
1029 1029
1030 1030 /*
1031 1031 * Soft interrupt handlers
1032 1032 */
1033 1033 /*
1034 1034 * Add a soft interrupt and register its handler
1035 1035 */
1036 1036 /* ARGSUSED */
1037 1037 int
1038 1038 ddi_intr_add_softint(dev_info_t *dip, ddi_softint_handle_t *h_p, int soft_pri,
1039 1039 ddi_intr_handler_t handler, void *arg1)
1040 1040 {
1041 1041 ddi_softint_hdl_impl_t *hdlp;
1042 1042 int ret;
1043 1043
1044 1044 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_add_softint: dip = %p, "
1045 1045 "softpri = 0x%x\n", (void *)dip, soft_pri));
1046 1046
1047 1047 if ((dip == NULL) || (h_p == NULL) || (handler == NULL)) {
1048 1048 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_add_softint: "
1049 1049 "invalid arguments"));
1050 1050
1051 1051 return (DDI_EINVAL);
1052 1052 }
1053 1053
1054 1054 /* Validate input arguments */
1055 1055 if (soft_pri < DDI_INTR_SOFTPRI_MIN ||
1056 1056 soft_pri > DDI_INTR_SOFTPRI_MAX) {
1057 1057 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_add_softint: invalid "
1058 1058 "soft_pri input given = %x\n", soft_pri));
1059 1059 return (DDI_EINVAL);
1060 1060 }
1061 1061
1062 1062 hdlp = (ddi_softint_hdl_impl_t *)kmem_zalloc(
1063 1063 sizeof (ddi_softint_hdl_impl_t), KM_SLEEP);
1064 1064
1065 1065 /* fill up internally */
1066 1066 rw_init(&hdlp->ih_rwlock, NULL, RW_DRIVER, NULL);
1067 1067 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
1068 1068 hdlp->ih_pri = soft_pri;
1069 1069 hdlp->ih_dip = dip;
1070 1070 hdlp->ih_cb_func = handler;
1071 1071 hdlp->ih_cb_arg1 = arg1;
1072 1072 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_add_softint: hdlp = %p\n",
1073 1073 (void *)hdlp));
1074 1074
1075 1075 /* do the platform specific calls */
1076 1076 if ((ret = i_ddi_add_softint(hdlp)) != DDI_SUCCESS) {
1077 1077 rw_exit(&hdlp->ih_rwlock);
1078 1078 rw_destroy(&hdlp->ih_rwlock);
1079 1079 kmem_free(hdlp, sizeof (ddi_softint_hdl_impl_t));
1080 1080 return (ret);
1081 1081 }
1082 1082
1083 1083 *h_p = (ddi_softint_handle_t)hdlp;
1084 1084 rw_exit(&hdlp->ih_rwlock);
1085 1085 return (ret);
1086 1086 }
1087 1087
1088 1088 /*
1089 1089 * Remove the soft interrupt
1090 1090 */
1091 1091 int
1092 1092 ddi_intr_remove_softint(ddi_softint_handle_t h)
1093 1093 {
1094 1094 ddi_softint_hdl_impl_t *hdlp = (ddi_softint_hdl_impl_t *)h;
1095 1095
1096 1096 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_remove_softint: hdlp = %p\n",
1097 1097 (void *)hdlp));
1098 1098
1099 1099 if (hdlp == NULL)
1100 1100 return (DDI_EINVAL);
1101 1101
1102 1102 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
1103 1103 i_ddi_remove_softint(hdlp);
1104 1104 rw_exit(&hdlp->ih_rwlock);
1105 1105 rw_destroy(&hdlp->ih_rwlock);
1106 1106
1107 1107 /* kmem_free the hdl impl_t structure allocated earlier */
1108 1108 kmem_free(hdlp, sizeof (ddi_softint_hdl_impl_t));
1109 1109 return (DDI_SUCCESS);
1110 1110 }
1111 1111
1112 1112 /*
1113 1113 * Trigger a soft interrupt
1114 1114 */
1115 1115 int
1116 1116 ddi_intr_trigger_softint(ddi_softint_handle_t h, void *arg2)
1117 1117 {
1118 1118 ddi_softint_hdl_impl_t *hdlp = (ddi_softint_hdl_impl_t *)h;
1119 1119 int ret;
1120 1120
1121 1121 if (hdlp == NULL)
1122 1122 return (DDI_EINVAL);
1123 1123
1124 1124 if ((ret = i_ddi_trigger_softint(hdlp, arg2)) != DDI_SUCCESS) {
1125 1125 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_trigger_softint: failed, "
1126 1126 " ret 0%x\n", ret));
1127 1127
1128 1128 return (ret);
1129 1129 }
1130 1130
1131 1131 hdlp->ih_cb_arg2 = arg2;
1132 1132 return (DDI_SUCCESS);
1133 1133 }
1134 1134
1135 1135 /*
1136 1136 * Get the soft interrupt priority
1137 1137 */
1138 1138 int
1139 1139 ddi_intr_get_softint_pri(ddi_softint_handle_t h, uint_t *soft_prip)
1140 1140 {
1141 1141 ddi_softint_hdl_impl_t *hdlp = (ddi_softint_hdl_impl_t *)h;
1142 1142
1143 1143 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_get_softint_pri: h = %p\n",
1144 1144 (void *)h));
1145 1145
1146 1146 if (hdlp == NULL)
1147 1147 return (DDI_EINVAL);
1148 1148
1149 1149 rw_enter(&hdlp->ih_rwlock, RW_READER);
1150 1150 *soft_prip = hdlp->ih_pri;
1151 1151 rw_exit(&hdlp->ih_rwlock);
1152 1152 return (DDI_SUCCESS);
1153 1153 }
1154 1154
1155 1155 /*
1156 1156 * Set the soft interrupt priority
1157 1157 */
1158 1158 int
1159 1159 ddi_intr_set_softint_pri(ddi_softint_handle_t h, uint_t soft_pri)
1160 1160 {
1161 1161 ddi_softint_hdl_impl_t *hdlp = (ddi_softint_hdl_impl_t *)h;
1162 1162 int ret;
1163 1163 uint_t orig_soft_pri;
1164 1164
1165 1165 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_set_softint_pri: h = %p\n",
1166 1166 (void *)h));
1167 1167
1168 1168 if (hdlp == NULL)
1169 1169 return (DDI_EINVAL);
1170 1170
1171 1171 /* Validate priority argument */
1172 1172 if (soft_pri < DDI_INTR_SOFTPRI_MIN ||
1173 1173 soft_pri > DDI_INTR_SOFTPRI_MAX) {
1174 1174 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_set_softint_pri: invalid "
1175 1175 "soft_pri input given = %x\n", soft_pri));
1176 1176 return (DDI_EINVAL);
1177 1177 }
1178 1178
1179 1179 rw_enter(&hdlp->ih_rwlock, RW_WRITER);
1180 1180 orig_soft_pri = hdlp->ih_pri;
1181 1181 hdlp->ih_pri = soft_pri;
1182 1182
1183 1183 if ((ret = i_ddi_set_softint_pri(hdlp, orig_soft_pri)) != DDI_SUCCESS) {
1184 1184 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_set_softint_pri: failed, "
1185 1185 " ret 0%x\n", ret));
1186 1186 hdlp->ih_pri = orig_soft_pri;
1187 1187 }
1188 1188
1189 1189 rw_exit(&hdlp->ih_rwlock);
1190 1190 return (ret);
1191 1191 }
1192 1192
1193 1193 /*
1194 1194 * Old DDI interrupt framework
1195 1195 *
1196 1196 * The following DDI interrupt interfaces are obsolete.
1197 1197 * Use the above new DDI interrupt interfaces instead.
1198 1198 */
1199 1199
1200 1200 int
1201 1201 ddi_intr_hilevel(dev_info_t *dip, uint_t inumber)
1202 1202 {
1203 1203 ddi_intr_handle_t hdl;
1204 1204 ddi_intr_handle_t *hdl_p;
1205 1205 size_t hdl_sz = 0;
1206 1206 int actual, ret;
1207 1207 uint_t high_pri, pri;
1208 1208
1209 1209 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_hilevel: name=%s%d dip=0x%p "
1210 1210 "inum=0x%x\n", ddi_driver_name(dip), ddi_get_instance(dip),
1211 1211 (void *)dip, inumber));
1212 1212
1213 1213 /*
1214 1214 * The device driver may have already registed with the
1215 1215 * framework. If so, first try to get the existing interrupt handle
1216 1216 * for that given inumber and use that handle.
1217 1217 */
1218 1218 if ((hdl = i_ddi_get_intr_handle(dip, inumber)) == NULL) {
1219 1219 hdl_sz = sizeof (ddi_intr_handle_t) * (inumber + 1);
1220 1220 hdl_p = kmem_zalloc(hdl_sz, KM_SLEEP);
1221 1221 if ((ret = ddi_intr_alloc(dip, hdl_p, DDI_INTR_TYPE_FIXED,
1222 1222 inumber, 1, &actual,
1223 1223 DDI_INTR_ALLOC_NORMAL)) != DDI_SUCCESS) {
1224 1224 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_hilevel: "
1225 1225 "ddi_intr_alloc failed, ret 0x%x\n", ret));
1226 1226 kmem_free(hdl_p, hdl_sz);
1227 1227 return (0);
1228 1228 }
1229 1229 hdl = hdl_p[inumber];
1230 1230 }
1231 1231
1232 1232 if ((ret = ddi_intr_get_pri(hdl, &pri)) != DDI_SUCCESS) {
1233 1233 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_hilevel: "
1234 1234 "ddi_intr_get_pri failed, ret 0x%x\n", ret));
1235 1235 (void) ddi_intr_free(hdl);
1236 1236 if (hdl_sz)
1237 1237 kmem_free(hdl_p, hdl_sz);
1238 1238 return (0);
1239 1239 }
1240 1240
1241 1241 high_pri = ddi_intr_get_hilevel_pri();
1242 1242
1243 1243 DDI_INTR_APIDBG((CE_CONT, "ddi_intr_hilevel: pri = %x, "
1244 1244 "high_pri = %x\n", pri, high_pri));
1245 1245
1246 1246 /* Free the handle allocated here only if no existing handle exists */
1247 1247 if (hdl_sz) {
1248 1248 (void) ddi_intr_free(hdl);
1249 1249 kmem_free(hdl_p, hdl_sz);
1250 1250 }
1251 1251
1252 1252 return (pri >= high_pri);
1253 1253 }
1254 1254
1255 1255 int
1256 1256 ddi_dev_nintrs(dev_info_t *dip, int *result)
1257 1257 {
1258 1258 DDI_INTR_APIDBG((CE_CONT, "ddi_dev_nintrs: name=%s%d dip=0x%p\n",
1259 1259 ddi_driver_name(dip), ddi_get_instance(dip), (void *)dip));
1260 1260
1261 1261 if (ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED,
1262 1262 result) != DDI_SUCCESS) {
1263 1263 DDI_INTR_APIDBG((CE_CONT, "ddi_dev_nintrs: "
1264 1264 "ddi_intr_get_nintrs failed\n"));
1265 1265 *result = 0;
1266 1266 }
1267 1267
1268 1268 return (DDI_SUCCESS);
1269 1269 }
1270 1270
1271 1271 int
1272 1272 ddi_get_iblock_cookie(dev_info_t *dip, uint_t inumber,
1273 1273 ddi_iblock_cookie_t *iblock_cookiep)
1274 1274 {
1275 1275 ddi_intr_handle_t hdl;
1276 1276 ddi_intr_handle_t *hdl_p;
1277 1277 size_t hdl_sz = 0;
1278 1278 int actual, ret;
1279 1279 uint_t pri;
1280 1280
1281 1281 DDI_INTR_APIDBG((CE_CONT, "ddi_get_iblock_cookie: name=%s%d dip=0x%p "
1282 1282 "inum=0x%x\n", ddi_driver_name(dip), ddi_get_instance(dip),
1283 1283 (void *)dip, inumber));
1284 1284
1285 1285 ASSERT(iblock_cookiep != NULL);
1286 1286
1287 1287 /*
1288 1288 * The device driver may have already registed with the
1289 1289 * framework. If so, first try to get the existing interrupt handle
1290 1290 * for that given inumber and use that handle.
1291 1291 */
1292 1292 if ((hdl = i_ddi_get_intr_handle(dip, inumber)) == NULL) {
1293 1293 hdl_sz = sizeof (ddi_intr_handle_t) * (inumber + 1);
1294 1294 hdl_p = kmem_zalloc(hdl_sz, KM_SLEEP);
1295 1295 if ((ret = ddi_intr_alloc(dip, hdl_p,
1296 1296 DDI_INTR_TYPE_FIXED, inumber, 1, &actual,
1297 1297 DDI_INTR_ALLOC_NORMAL)) != DDI_SUCCESS) {
1298 1298 DDI_INTR_APIDBG((CE_CONT, "ddi_get_iblock_cookie: "
1299 1299 "ddi_intr_alloc failed, ret 0x%x\n", ret));
1300 1300 kmem_free(hdl_p, hdl_sz);
1301 1301 return (DDI_INTR_NOTFOUND);
1302 1302 }
1303 1303 hdl = hdl_p[inumber];
1304 1304 }
1305 1305
1306 1306 if ((ret = ddi_intr_get_pri(hdl, &pri)) != DDI_SUCCESS) {
1307 1307 DDI_INTR_APIDBG((CE_CONT, "ddi_get_iblock_cookie: "
1308 1308 "ddi_intr_get_pri failed, ret 0x%x\n", ret));
1309 1309 (void) ddi_intr_free(hdl);
1310 1310 if (hdl_sz)
1311 1311 kmem_free(hdl_p, hdl_sz);
1312 1312 return (DDI_FAILURE);
1313 1313 }
1314 1314
1315 1315 *iblock_cookiep = (ddi_iblock_cookie_t)(uintptr_t)pri;
1316 1316 /* Free the handle allocated here only if no existing handle exists */
1317 1317 if (hdl_sz) {
1318 1318 (void) ddi_intr_free(hdl);
1319 1319 kmem_free(hdl_p, hdl_sz);
1320 1320 }
1321 1321
1322 1322 return (DDI_SUCCESS);
1323 1323 }
1324 1324
1325 1325 int
1326 1326 ddi_add_intr(dev_info_t *dip, uint_t inumber,
1327 1327 ddi_iblock_cookie_t *iblock_cookiep,
1328 1328 ddi_idevice_cookie_t *idevice_cookiep,
1329 1329 uint_t (*int_handler)(caddr_t int_handler_arg),
1330 1330 caddr_t int_handler_arg)
1331 1331 {
1332 1332 ddi_intr_handle_t *hdl_p;
1333 1333 size_t hdl_sz;
1334 1334 int actual, ret;
1335 1335 uint_t pri;
1336 1336
1337 1337 DDI_INTR_APIDBG((CE_CONT, "ddi_add_intr: name=%s%d dip=0x%p "
1338 1338 "inum=0x%x\n", ddi_driver_name(dip), ddi_get_instance(dip),
1339 1339 (void *)dip, inumber));
1340 1340
1341 1341 hdl_sz = sizeof (ddi_intr_handle_t) * (inumber + 1);
1342 1342 hdl_p = kmem_zalloc(hdl_sz, KM_SLEEP);
1343 1343
1344 1344 if ((ret = ddi_intr_alloc(dip, hdl_p, DDI_INTR_TYPE_FIXED,
1345 1345 inumber, 1, &actual, DDI_INTR_ALLOC_NORMAL)) != DDI_SUCCESS) {
1346 1346 DDI_INTR_APIDBG((CE_CONT, "ddi_add_intr: "
1347 1347 "ddi_intr_alloc failed, ret 0x%x\n", ret));
1348 1348 kmem_free(hdl_p, hdl_sz);
1349 1349 return (DDI_INTR_NOTFOUND);
1350 1350 }
1351 1351
1352 1352 if ((ret = ddi_intr_get_pri(hdl_p[inumber], &pri)) != DDI_SUCCESS) {
1353 1353 DDI_INTR_APIDBG((CE_CONT, "ddi_add_intr: "
1354 1354 "ddi_intr_get_pri failed, ret 0x%x\n", ret));
1355 1355 (void) ddi_intr_free(hdl_p[inumber]);
1356 1356 kmem_free(hdl_p, hdl_sz);
1357 1357 return (DDI_FAILURE);
1358 1358 }
1359 1359
1360 1360 if ((ret = ddi_intr_add_handler(hdl_p[inumber], (ddi_intr_handler_t *)
1361 1361 int_handler, int_handler_arg, NULL)) != DDI_SUCCESS) {
1362 1362 DDI_INTR_APIDBG((CE_CONT, "ddi_add_intr: "
1363 1363 "ddi_intr_add_handler failed, ret 0x%x\n", ret));
1364 1364 (void) ddi_intr_free(hdl_p[inumber]);
1365 1365 kmem_free(hdl_p, hdl_sz);
1366 1366 return (DDI_FAILURE);
1367 1367 }
1368 1368
1369 1369 if ((ret = ddi_intr_enable(hdl_p[inumber])) != DDI_SUCCESS) {
1370 1370 DDI_INTR_APIDBG((CE_CONT, "ddi_add_intr: "
1371 1371 "ddi_intr_enable failed, ret 0x%x\n", ret));
1372 1372 (void) ddi_intr_remove_handler(hdl_p[inumber]);
1373 1373 (void) ddi_intr_free(hdl_p[inumber]);
1374 1374 kmem_free(hdl_p, hdl_sz);
1375 1375 return (DDI_FAILURE);
1376 1376 }
1377 1377
1378 1378 if (iblock_cookiep)
1379 1379 *iblock_cookiep = (ddi_iblock_cookie_t)(uintptr_t)pri;
1380 1380
1381 1381 if (idevice_cookiep) {
1382 1382 idevice_cookiep->idev_vector = 0;
1383 1383 idevice_cookiep->idev_priority = pri;
1384 1384 }
1385 1385
1386 1386 kmem_free(hdl_p, hdl_sz);
1387 1387
1388 1388 return (DDI_SUCCESS);
1389 1389 }
1390 1390
1391 1391 /* ARGSUSED */
1392 1392 int
1393 1393 ddi_add_fastintr(dev_info_t *dip, uint_t inumber,
1394 1394 ddi_iblock_cookie_t *iblock_cookiep,
1395 1395 ddi_idevice_cookie_t *idevice_cookiep,
1396 1396 uint_t (*hi_int_handler)(void))
1397 1397 {
1398 1398 DDI_INTR_APIDBG((CE_CONT, "ddi_add_fastintr: name=%s%d dip=0x%p "
1399 1399 "inum=0x%x: Not supported, return failure\n", ddi_driver_name(dip),
1400 1400 ddi_get_instance(dip), (void *)dip, inumber));
1401 1401
1402 1402 return (DDI_FAILURE);
1403 1403 }
1404 1404
1405 1405 /* ARGSUSED */
1406 1406 void
1407 1407 ddi_remove_intr(dev_info_t *dip, uint_t inum, ddi_iblock_cookie_t iblock_cookie)
1408 1408 {
1409 1409 ddi_intr_handle_t hdl;
1410 1410 int ret;
1411 1411
1412 1412 DDI_INTR_APIDBG((CE_CONT, "ddi_remove_intr: name=%s%d dip=0x%p "
1413 1413 "inum=0x%x\n", ddi_driver_name(dip), ddi_get_instance(dip),
1414 1414 (void *)dip, inum));
1415 1415
1416 1416 if ((hdl = i_ddi_get_intr_handle(dip, inum)) == NULL) {
1417 1417 DDI_INTR_APIDBG((CE_CONT, "ddi_remove_intr: no handle "
1418 1418 "found\n"));
1419 1419 return;
1420 1420 }
1421 1421
1422 1422 if ((ret = ddi_intr_disable(hdl)) != DDI_SUCCESS) {
1423 1423 DDI_INTR_APIDBG((CE_CONT, "ddi_remove_intr: "
1424 1424 "ddi_intr_disable failed, ret 0x%x\n", ret));
1425 1425 return;
1426 1426 }
1427 1427
1428 1428 if ((ret = ddi_intr_remove_handler(hdl)) != DDI_SUCCESS) {
1429 1429 DDI_INTR_APIDBG((CE_CONT, "ddi_remove_intr: "
1430 1430 "ddi_intr_remove_handler failed, ret 0x%x\n", ret));
1431 1431 return;
1432 1432 }
1433 1433
1434 1434 if ((ret = ddi_intr_free(hdl)) != DDI_SUCCESS) {
1435 1435 DDI_INTR_APIDBG((CE_CONT, "ddi_remove_intr: "
1436 1436 "ddi_intr_free failed, ret 0x%x\n", ret));
1437 1437 return;
1438 1438 }
1439 1439 }
1440 1440
1441 1441 /* ARGSUSED */
1442 1442 int
1443 1443 ddi_get_soft_iblock_cookie(dev_info_t *dip, int preference,
1444 1444 ddi_iblock_cookie_t *iblock_cookiep)
1445 1445 {
1446 1446 DDI_INTR_APIDBG((CE_CONT, "ddi_get_soft_iblock_cookie: name=%s%d "
1447 1447 "dip=0x%p pref=0x%x\n", ddi_driver_name(dip), ddi_get_instance(dip),
1448 1448 (void *)dip, preference));
1449 1449
1450 1450 ASSERT(iblock_cookiep != NULL);
1451 1451
1452 1452 if (preference == DDI_SOFTINT_FIXED)
1453 1453 return (DDI_FAILURE);
1454 1454
1455 1455 *iblock_cookiep = (ddi_iblock_cookie_t)((uintptr_t)
1456 1456 ((preference > DDI_SOFTINT_MED) ? DDI_SOFT_INTR_PRI_H :
1457 1457 DDI_SOFT_INTR_PRI_M));
1458 1458
1459 1459 return (DDI_SUCCESS);
1460 1460 }
1461 1461
1462 1462 int
1463 1463 ddi_add_softintr(dev_info_t *dip, int preference, ddi_softintr_t *idp,
1464 1464 ddi_iblock_cookie_t *iblock_cookiep,
1465 1465 ddi_idevice_cookie_t *idevice_cookiep,
1466 1466 uint_t (*int_handler)(caddr_t int_handler_arg),
1467 1467 caddr_t int_handler_arg)
1468 1468 {
1469 1469 ddi_softint_handle_t *hdl_p;
1470 1470 uint64_t softpri;
1471 1471 int ret;
1472 1472
1473 1473 DDI_INTR_APIDBG((CE_CONT, "ddi_add_softintr: name=%s%d dip=0x%p "
1474 1474 "pref=0x%x\n", ddi_driver_name(dip), ddi_get_instance(dip),
1475 1475 (void *)dip, preference));
1476 1476
1477 1477 if ((idp == NULL) || ((preference == DDI_SOFTINT_FIXED) &&
1478 1478 (iblock_cookiep == NULL)))
1479 1479 return (DDI_FAILURE);
1480 1480
1481 1481 /* Translate the priority preference */
1482 1482 if (preference == DDI_SOFTINT_FIXED) {
1483 1483 softpri = (uint64_t)(uintptr_t)*iblock_cookiep;
1484 1484 softpri = MIN(softpri, DDI_SOFT_INTR_PRI_H);
1485 1485 } else {
1486 1486 softpri = (uint64_t)((preference > DDI_SOFTINT_MED) ?
1487 1487 DDI_SOFT_INTR_PRI_H : DDI_SOFT_INTR_PRI_M);
1488 1488 }
1489 1489
1490 1490 DDI_INTR_APIDBG((CE_CONT, "ddi_add_softintr: preference 0x%x "
1491 1491 "softpri 0x%lx\n", preference, (long)softpri));
1492 1492
1493 1493 hdl_p = kmem_zalloc(sizeof (ddi_softint_handle_t), KM_SLEEP);
1494 1494 if ((ret = ddi_intr_add_softint(dip, hdl_p, softpri,
1495 1495 (ddi_intr_handler_t *)int_handler, int_handler_arg)) !=
1496 1496 DDI_SUCCESS) {
1497 1497 DDI_INTR_APIDBG((CE_CONT, "ddi_add_softintr: "
1498 1498 "ddi_intr_add_softint failed, ret 0x%x\n", ret));
1499 1499
1500 1500 kmem_free(hdl_p, sizeof (ddi_softint_handle_t));
1501 1501 return (DDI_FAILURE);
1502 1502 }
1503 1503
1504 1504 if (iblock_cookiep)
1505 1505 *iblock_cookiep = (ddi_iblock_cookie_t)(uintptr_t)softpri;
1506 1506
1507 1507 if (idevice_cookiep) {
1508 1508 idevice_cookiep->idev_vector = 0;
1509 1509 idevice_cookiep->idev_priority = softpri;
1510 1510 }
1511 1511
1512 1512 *idp = (ddi_softintr_t)hdl_p;
1513 1513
1514 1514 DDI_INTR_APIDBG((CE_CONT, "ddi_add_softintr: dip = 0x%p, "
1515 1515 "idp = 0x%p, ret = %x\n", (void *)dip, (void *)*idp, ret));
1516 1516
1517 1517 return (DDI_SUCCESS);
1518 1518 }
1519 1519
1520 1520 void
1521 1521 ddi_remove_softintr(ddi_softintr_t id)
1522 1522 {
1523 1523 ddi_softint_handle_t *h_p = (ddi_softint_handle_t *)id;
1524 1524
1525 1525 DDI_INTR_APIDBG((CE_CONT, "ddi_remove_softintr: id=0x%p\n",
1526 1526 (void *)id));
1527 1527
1528 1528 if (h_p == NULL)
1529 1529 return;
1530 1530
1531 1531 DDI_INTR_APIDBG((CE_CONT, "ddi_remove_softintr: handle 0x%p\n",
1532 1532 (void *)h_p));
1533 1533
1534 1534 (void) ddi_intr_remove_softint(*h_p);
1535 1535 kmem_free(h_p, sizeof (ddi_softint_handle_t));
1536 1536 }
1537 1537
1538 1538 void
1539 1539 ddi_trigger_softintr(ddi_softintr_t id)
1540 1540 {
1541 1541 ddi_softint_handle_t *h_p = (ddi_softint_handle_t *)id;
1542 1542 int ret;
1543 1543
1544 1544 if (h_p == NULL)
1545 1545 return;
1546 1546
1547 1547 if ((ret = ddi_intr_trigger_softint(*h_p, NULL)) != DDI_SUCCESS) {
1548 1548 DDI_INTR_APIDBG((CE_CONT, "ddi_trigger_softintr: "
1549 1549 "ddi_intr_trigger_softint failed, hdlp 0x%p "
1550 1550 "ret 0x%x\n", (void *)h_p, ret));
1551 1551 }
1552 1552 }
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