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5042 stop using deprecated atomic functions

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          --- old/usr/src/uts/i86pc/vm/hat_pte.h
          +++ new/usr/src/uts/i86pc/vm/hat_pte.h
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  19   19   * CDDL HEADER END
  20   20   */
  21   21  /*
  22   22   * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  23   23   * Use is subject to license terms.
  24   24   */
  25   25  
  26   26  #ifndef _VM_HAT_PTE_H
  27   27  #define _VM_HAT_PTE_H
  28   28  
  29      -#pragma ident   "%Z%%M% %I%     %E% SMI"
  30      -
  31   29  #ifdef  __cplusplus
  32   30  extern "C" {
  33   31  #endif
  34   32  
  35   33  #include <sys/types.h>
  36   34  #include <sys/mach_mmu.h>
  37   35  
  38   36  /*
  39   37   * macros to get/set/clear the PTE fields
  40   38   */
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 228  226  #define PWIN_TABLE(cpuid)       ((cpuid) * 2)
 229  227  #define PWIN_SRC(cpuid)         ((cpuid) * 2 + 1)       /* for x86pte_copy() */
 230  228  #define PWIN_VA(x)              (mmu.pwin_base + ((x) << MMU_PAGESHIFT))
 231  229  #define PWIN_PTE_VA(x)          (mmu.pwin_pte_va + ((x) << mmu.pte_size_shift))
 232  230  #define PWIN_PTE_PA(x)          (mmu.pwin_pte_pa + ((x) << mmu.pte_size_shift))
 233  231  
 234  232  /*
 235  233   * The concept of a VA hole exists in AMD64. This might need to be made
 236  234   * model specific eventually.
 237  235   *
 238      - * In the 64 bit kernel PTE loads are atomic, but need cas64 on 32 bit kernel.
      236 + * In the 64 bit kernel PTE loads are atomic, but need atomic_cas_64 on 32
      237 + * bit kernel.
 239  238   */
 240  239  #if defined(__amd64)
 241  240  
 242  241  #ifdef lint
 243  242  #define IN_VA_HOLE(va)  (__lintzero)
 244  243  #else
 245  244  #define IN_VA_HOLE(va)  (mmu.hole_start <= (va) && (va) < mmu.hole_end)
 246  245  #endif
 247  246  
 248  247  #define FMT_PTE "0x%lx"
 249  248  #define GET_PTE(ptr)            (*(x86pte_t *)(ptr))
 250  249  #define SET_PTE(ptr, pte)       (*(x86pte_t *)(ptr) = pte)
 251      -#define CAS_PTE(ptr, x, y)      cas64(ptr, x, y)
      250 +#define CAS_PTE(ptr, x, y)      atomic_cas_64(ptr, x, y)
 252  251  
 253  252  #elif defined(__i386)
 254  253  
 255  254  #define IN_VA_HOLE(va)  (__lintzero)
 256  255  
 257  256  #define FMT_PTE "0x%llx"
 258  257  
 259  258  /* on 32 bit kernels, 64 bit loads aren't atomic, use get_pte64() */
 260  259  extern x86pte_t get_pte64(x86pte_t *ptr);
 261  260  #define GET_PTE(ptr)    (mmu.pae_hat ? get_pte64(ptr) : *(x86pte32_t *)(ptr))
 262  261  #define SET_PTE(ptr, pte)                                               \
 263  262          ((mmu.pae_hat ? ((x86pte32_t *)(ptr))[1] = (pte >> 32) : 0),    \
 264  263          *(x86pte32_t *)(ptr) = pte)
 265  264  #define CAS_PTE(ptr, x, y)                      \
 266      -        (mmu.pae_hat ? cas64(ptr, x, y) :       \
 267      -        cas32((uint32_t *)(ptr), (uint32_t)(x), (uint32_t)(y)))
      265 +        (mmu.pae_hat ? atomic_cas_64(ptr, x, y) :       \
      266 +        atomic_cas_32((uint32_t *)(ptr), (uint32_t)(x), (uint32_t)(y)))
 268  267  
 269  268  #endif  /* __i386 */
 270  269  
 271  270  /*
 272  271   * Return a pointer to the pte entry at the given index within a page table.
 273  272   */
 274  273  #define PT_INDEX_PTR(p, x) \
 275  274          ((x86pte_t *)((uintptr_t)(p) + ((x) << mmu.pte_size_shift)))
 276  275  
 277  276  /*
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