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4778 iprb shouldn't abuse ddi_get_time(9f)
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Garrett D'Amore <garrett@damore.org>
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--- old/usr/src/uts/common/io/iprb/iprb.h
+++ new/usr/src/uts/common/io/iprb/iprb.h
1 1 /*
2 2 * This file and its contents are supplied under the terms of the
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3 3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 4 * You may only use this file in accordance with the terms of version
5 5 * 1.0 of the CDDL.
6 6 *
7 7 * A full copy of the text of the CDDL should have accompanied this
8 8 * source. A copy of the CDDL is also available via the Internet at
9 9 * http://www.illumos.org/license/CDDL.
10 10 */
11 11
12 12 /*
13 - * Copyright 2010 Nexenta Systems, Inc. All rights reserved.
13 + * Copyright 2014 Nexenta Systems, Inc. All rights reserved.
14 14 */
15 15
16 16 #ifndef _IPRB_H
17 17 #define _IPRB_H
18 18
19 19 /*
20 20 * iprb - Intel Pro/100B Ethernet Driver
21 21 */
22 22
23 23 /*
24 24 * Tunables.
25 25 */
26 26 #define NUM_TX 128 /* outstanding tx queue */
27 27 #define NUM_RX 128 /* outstanding rx queue */
28 28
29 -#define RX_WATCHDOG 15 /* timeout for rx watchdog (sec) */
30 -#define TX_WATCHDOG 15 /* timeout for tx watchdog (sec) */
29 +/* timeouts for the rx and tx watchdogs (nsec) */
30 +#define RX_WATCHDOG (15 * NANOSEC)
31 +#define TX_WATCHDOG (15 * NANOSEC)
31 32
32 33 /*
33 34 * Driver structures.
34 35 */
35 36 typedef struct {
36 37 ddi_acc_handle_t acch;
37 38 ddi_dma_handle_t dmah;
38 39 caddr_t vaddr;
39 40 uint32_t paddr;
40 41 } iprb_dma_t;
41 42
42 43 typedef struct iprb_mcast {
43 44 list_node_t node;
44 45 uint8_t addr[6];
45 46 } iprb_mcast_t;
46 47
47 48 typedef struct iprb {
48 49 dev_info_t *dip;
49 50 ddi_acc_handle_t pcih;
50 51 ddi_acc_handle_t regsh;
51 52 caddr_t regs;
52 53
53 54 uint16_t devid;
54 55 uint8_t revid;
55 56
56 57 mac_handle_t mach;
57 58 mii_handle_t miih;
58 59
59 60 ddi_intr_handle_t intrh;
60 61
61 62 ddi_periodic_t perh;
62 63
63 64 kmutex_t culock;
64 65 kmutex_t rulock;
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65 66
66 67 uint8_t factaddr[6];
67 68 uint8_t curraddr[6];
68 69
69 70 int nmcast;
70 71 list_t mcast;
71 72 boolean_t promisc;
72 73 iprb_dma_t cmds[NUM_TX];
73 74 iprb_dma_t rxb[NUM_RX];
74 75 iprb_dma_t stats;
75 - time_t stats_time;
76 + hrtime_t stats_time;
76 77
77 78 uint16_t cmd_head;
78 79 uint16_t cmd_last;
79 80 uint16_t cmd_tail;
80 81 uint16_t cmd_count;
81 82
82 83 uint16_t rx_index;
83 84 uint16_t rx_last;
84 - time_t rx_wdog;
85 - time_t rx_timeout;
86 - time_t tx_wdog;
87 - time_t tx_timeout;
85 + hrtime_t rx_wdog;
86 + hrtime_t rx_timeout;
87 + hrtime_t tx_wdog;
88 + hrtime_t tx_timeout;
88 89
89 90 uint16_t eeprom_bits;
90 91
91 92 boolean_t running;
92 93 boolean_t suspended;
93 94 boolean_t wantw;
94 95 boolean_t rxhangbug;
95 96 boolean_t resumebug;
96 97 boolean_t is557;
97 98 boolean_t canpause;
98 99 boolean_t canmwi;
99 100
100 101 /*
101 102 * Statistics
102 103 */
103 104 uint64_t ipackets;
104 105 uint64_t rbytes;
105 106 uint64_t multircv;
106 107 uint64_t brdcstrcv;
107 108 uint64_t opackets;
108 109 uint64_t obytes;
109 110 uint64_t multixmt;
110 111 uint64_t brdcstxmt;
111 112 uint64_t ex_coll;
112 113 uint64_t late_coll;
113 114 uint64_t uflo;
114 115 uint64_t defer_xmt;
115 116 uint64_t one_coll;
116 117 uint64_t multi_coll;
117 118 uint64_t collisions;
118 119 uint64_t fcs_errs;
119 120 uint64_t align_errs;
120 121 uint64_t norcvbuf;
121 122 uint64_t oflo;
122 123 uint64_t runt;
123 124 uint64_t nocarrier;
124 125 uint64_t toolong;
125 126 uint64_t macxmt_errs;
126 127 uint64_t macrcv_errs;
127 128 } iprb_t;
128 129
129 130 /*
130 131 * Idenfication values.
131 132 */
132 133 #define REV_82557 1
133 134 #define REV_82558_A4 4
134 135 #define REV_82558_B0 5
135 136 #define REV_82559_A0 8
136 137 #define REV_82559S_A 9
137 138 #define REV_82550 12
138 139 #define REV_82550_C 13
139 140 #define REV_82551_E 14
140 141 #define REV_82551_F 15
141 142 #define REV_82551_10 16
142 143
143 144 /*
144 145 * Device registers.
145 146 */
146 147 #define CSR_STATE 0x00
147 148 #define CSR_STS 0x01
148 149 #define CSR_CMD 0x02
149 150 #define CSR_INTCTL 0x03
150 151 #define CSR_GEN_PTR 0x04
151 152 #define CSR_PORT 0x08
152 153 #define CSR_EECTL 0x0e
153 154 #define CSR_MDICTL 0x10
154 155
155 156 #define STATE_CUS 0xc0 /* CU state (mask) */
156 157 #define STATE_CUS_IDLE 0x00 /* CU idle */
157 158 #define STATE_CUS_SUSP 0x40 /* CU suspended */
158 159 #define STATE_CUS_LPQA 0x80 /* LPQ active */
159 160 #define STATE_CUS_HQPA 0xc0 /* HQP active */
160 161 #define STATE_RUS 0x3c /* RU state (mask) */
161 162 #define STATE_RUS_IDLE 0x00 /* RU idle */
162 163 #define STATE_RUS_SUSP 0x04 /* RU suspended */
163 164 #define STATE_RUS_NORES 0x08 /* RU no resources */
164 165 #define STATE_RUS_READY 0x10 /* RU ready */
165 166
166 167 #define STS_FCP 0x01 /* flow control pause */
167 168 #define STS_RSVD 0x02 /* reserved bit */
168 169 #define STS_SWI 0x04 /* software interrupt */
169 170 #define STS_MDI 0x08 /* MDI read/write done */
170 171 #define STS_RNR 0x10 /* RU not ready */
171 172 #define STS_CNA 0x20 /* CU state change */
172 173 #define STS_FR 0x40 /* frame receive */
173 174 #define STS_CX 0x80 /* cmd exec done */
174 175
175 176 #define CMD_CUC 0xf0 /* CU command (mask) */
176 177 #define CUC_NOP 0x00 /* no operation */
177 178 #define CUC_START 0x10 /* start CU */
178 179 #define CUC_RESUME 0x20 /* resume CU */
179 180 #define CUC_STATSBASE 0x40 /* load statistics address */
180 181 #define CUC_STATS 0x50 /* dump statistics */
181 182 #define CUC_CUBASE 0x60 /* load CU base address */
182 183 #define CUC_STATS_RST 0x70 /* dump statistics and reset */
183 184 #define CUC_SRES 0xa0 /* static resume CU */
184 185 #define CMD_RUC 0x07 /* RU command (mask) */
185 186 #define RUC_NOP 0x00 /* no operation */
186 187 #define RUC_START 0x01 /* start RU */
187 188 #define RUC_RESUME 0x02 /* resume RU */
188 189 #define RUC_DMAREDIR 0x03 /* receive DMA redirect */
189 190 #define RUC_ABORT 0x40 /* abort RU */
190 191 #define RUC_HDRSZ 0x50 /* load header data size */
191 192 #define RUC_RUBASE 0x60 /* load RU base address */
192 193
193 194 #define INTCTL_MASK 0x01 /* disable all interrupts */
194 195 #define INTCTL_SI 0x02 /* generate software interrupt */
195 196 #define INTCTL_FCP 0x04 /* flow control pause */
196 197 #define INTCTL_ER 0x08 /* early receive */
197 198 #define INTCTL_RNR 0x10 /* RU not ready */
198 199 #define INTCTL_CNA 0x20 /* CU state change */
199 200 #define INTCTL_FR 0x40 /* frame receive */
200 201 #define INTCTL_CX 0x80 /* cmd exec done */
201 202
202 203 #define PORT_SW_RESET 0x00
203 204 #define PORT_SELF_TEST 0x01
204 205 #define PORT_SEL_RESET 0x02
205 206
206 207 #define EEPROM_EEDO 0x0008 /* data out */
207 208 #define EEPROM_EEDI 0x0004 /* data in */
208 209 #define EEPROM_EECS 0x0002 /* chip select */
209 210 #define EEPROM_EESK 0x0001 /* clock */
210 211
211 212 #define EEPROM_OP_RD 0x06
212 213 #define EEPROM_OP_WR 0x05
213 214 #define EEPROM_OP_WE 0x13 /* write enable */
214 215 #define EEPROM_OP_WD 0x13 /* write disable */
215 216
216 217 #define MDI_IE 0x20000000 /* interrupt enable */
217 218 #define MDI_R 0x10000000 /* ready */
218 219 #define MDI_OP_RD 0x08000000 /* read */
219 220 #define MDI_OP_WR 0x04000000 /* write */
220 221 #define MDI_PHYAD_SHIFT 21
221 222 #define MDI_REGAD_SHIFT 16
222 223
223 224 #define GET8(ip, offset) \
224 225 ddi_get8(ip->regsh, (void *)(ip->regs + (offset)))
225 226 #define GET16(ip, offset) \
226 227 ddi_get16(ip->regsh, (void *)(ip->regs + (offset)))
227 228 #define GET32(ip, offset) \
228 229 ddi_get32(ip->regsh, (void *)(ip->regs + (offset)))
229 230 #define PUT8(ip, offset, val) \
230 231 ddi_put8(ip->regsh, (void *)(ip->regs + (offset)), (val))
231 232 #define PUT16(ip, offset, val) \
232 233 ddi_put16(ip->regsh, (void *)(ip->regs + (offset)), (val))
233 234 #define PUT32(ip, offset, val) \
234 235 ddi_put32(ip->regsh, (void *)(ip->regs + (offset)), (val))
235 236
236 237
237 238 #define PUTDMA8(d, off, val) \
238 239 ddi_put8(d->acch, (void *)(d->vaddr + (off)), LE_8(val))
239 240 #define PUTDMA16(d, off, val) \
240 241 ddi_put16(d->acch, (void *)(d->vaddr + (off)), LE_16(val))
241 242 #define PUTDMA32(d, off, val) \
242 243 ddi_put32(d->acch, (void *)(d->vaddr + (off)), LE_32(val))
243 244 #define GETDMA8(d, off) \
244 245 LE_8(ddi_get8(d->acch, (void *)(d->vaddr + (off))))
245 246 #define GETDMA16(d, off) \
246 247 LE_16(ddi_get16(d->acch, (void *)(d->vaddr + (off))))
247 248 #define GETDMA32(d, off) \
248 249 LE_32(ddi_get32(d->acch, (void *)(d->vaddr + (off))))
249 250 #define SYNCDMA(d, off, size, dir) \
250 251 (void) ddi_dma_sync(d->dmah, off, size, dir)
251 252
252 253 /*
253 254 * Command block offsets.
254 255 */
255 256 #define CB_STS_OFFSET 0
256 257 #define CB_CMD_OFFSET 2
257 258 #define CB_LNK_OFFSET 4
258 259 #define CB_SIZE 2048 /* size of cmd blk */
259 260
260 261 #define CB_IAS_ADR_OFFSET 8
261 262
262 263 #define CB_MCS_CNT_OFFSET 8
263 264 #define CB_MCS_ADR_OFFSET 10
264 265 #define CB_MCS_CNT_MAX ((CB_SIZE - CB_MCS_ADR_OFFSET) / 6)
265 266
266 267 #define CB_UCODE_OFFSET 8
267 268
268 269 #define CB_CONFIG_OFFSET 8
269 270
270 271 #define CB_TX_TBD_OFFSET 8
271 272 #define CB_TX_COUNT_OFFSET 12
272 273 #define CB_TX_EOF 0x8000
273 274 #define CB_TX_THRESH_OFFSET 14
274 275 #define CB_TX_NUMBER_OFFSET 15
275 276 #define CB_TX_DATA_OFFSET 16
276 277
277 278 #define PUTCB8(cb, o, v) PUTDMA8(cb, o, v)
278 279 #define PUTCB16(cb, o, v) PUTDMA16(cb, o, v)
279 280 #define PUTCB32(cb, o, v) PUTDMA32(cb, o, v)
280 281 #define PUTCBEA(cb, o, enet) \
281 282 ddi_rep_put8(cb->acch, enet, (void *)(cb->vaddr + (o)), 6, \
282 283 DDI_DEV_AUTOINCR);
283 284 #define GETCB8(cb, o) GETDMA8(cb, o)
284 285 #define GETCB16(cb, o) GETDMA16(cb, o)
285 286 #define GETCB32(cb, o) GETDMA32(cb, o)
286 287 #define SYNCCB(cb, o, s, dir) SYNCDMA(cb, o, s, dir)
287 288 /*
288 289 * CB status bits.
289 290 */
290 291 #define CB_STS_OK 0x2000
291 292 #define CB_STS_C 0x8000
292 293
293 294 /*
294 295 * Commands.
295 296 */
296 297 #define CB_CMD_NOP 0x0
297 298 #define CB_CMD_IAS 0x1
298 299 #define CB_CMD_CONFIG 0x2
299 300 #define CB_CMD_MCS 0x3
300 301 #define CB_CMD_TX 0x4
301 302 #define CB_CMD_UCODE 0x5
302 303 /* and flags to go with */
303 304 #define CB_CMD_SF 0x0008 /* simple/flex */
304 305 #define CB_CMD_I 0x2000 /* generate an interrupt */
305 306 #define CB_CMD_S 0x4000 /* suspend on completion */
306 307 #define CB_CMD_EL 0x8000 /* end of list */
307 308
308 309 /*
309 310 * RFD offsets.
310 311 */
311 312 #define GETRFD16(r, o) GETDMA16(r, o)
312 313 #define PUTRFD16(r, o, v) PUTDMA16(r, o, v)
313 314 #define PUTRFD32(r, o, v) PUTDMA32(r, o, v)
314 315 #define SYNCRFD(r, o, s, dir) SYNCDMA(r, o, s, dir)
315 316
316 317 #define RFD_STS_OFFSET 0x00
317 318 #define RFD_CTL_OFFSET 0x02
318 319 #define RFD_LNK_OFFSET 0x04
319 320 #define RFD_CNT_OFFSET 0x0c /* bytes received */
320 321 #define RFD_SIZ_OFFSET 0x0e /* size of packet area */
321 322 #define RFD_PKT_OFFSET 0x10
322 323 #define RFD_SIZE 2048
323 324
324 325 #define RFD_CTL_EL 0x8000
325 326 #define RFD_CTL_S 0x4000
326 327 #define RFD_CTL_H 0x0010
327 328 #define RFD_CTL_SF 0x0008
328 329
329 330 #define RFD_STS_C 0x8000
330 331 #define RFD_STS_OK 0x2000
331 332 #define RFD_STS_FCS 0x0800
332 333 #define RFD_STS_ALIGN 0x0400
333 334 #define RFD_STS_TOOBIG 0x0200
334 335 #define RFD_STS_DMAOFLO 0x0100
335 336 #define RFD_STS_TOOSHORT 0x0080
336 337 #define RFD_STS_802 0x0020
337 338 #define RFD_STS_RXERR 0x0010
338 339 #define RFD_STS_NOMATCH 0x0004
339 340 #define RFD_STS_IAMATCH 0x0002
340 341 #define RFD_STS_COLL_TCO 0x0001
341 342 #define RFD_STS_ERRS 0x0d90
342 343
343 344 #define RFD_CNT_EOF 0x8000
344 345 #define RFD_CNT_F 0x4000
345 346
346 347 /*
347 348 * Stats offsets.
348 349 */
349 350 #define STATS_TX_GOOD_OFFSET 0
350 351 #define STATS_TX_MAXCOL_OFFSET 4
351 352 #define STATS_TX_LATECOL_OFFSET 8
352 353 #define STATS_TX_UFLO_OFFSET 16
353 354 #define STATS_TX_DEFER_OFFSET 20
354 355 #define STATS_TX_ONECOL_OFFSET 24
355 356 #define STATS_TX_MULTCOL_OFFSET 28
356 357 #define STATS_TX_TOTCOL_OFFSET 32
357 358 #define STATS_RX_GOOD_OFFSET 36
358 359 #define STATS_RX_FCS_OFFSET 40
359 360 #define STATS_RX_ALIGN_OFFSET 44
360 361 #define STATS_RX_NOBUF_OFFSET 48
361 362 #define STATS_RX_OFLO_OFFSET 52
362 363 #define STATS_RX_COL_OFFSET 56
363 364 #define STATS_RX_SHORT_OFFSET 60
364 365 #define STATS_DONE_OFFSET 64
365 366 #define STATS_SIZE 68
366 367 #define STATS_DONE 0xa005
367 368 #define STATS_RST_DONE 0xa007
368 369
369 370 #define SYNCSTATS(sp, o, s, dir) SYNCDMA(sp, o, s, dir)
370 371 #define PUTSTAT(sp, o, v) PUTDMA32(sp, o, v)
371 372 #define GETSTAT(sp, o) GETDMA32(sp, o)
372 373
373 374 #endif /* _IPRB_H */
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