1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2012 Gary Mills
23 *
24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
25 * Copyright (c) 2011 by Delphix. All rights reserved.
26 */
27 /*
28 * Copyright (c) 2010, Intel Corporation.
29 * All rights reserved.
30 */
31
32 #include <sys/types.h>
33 #include <sys/sysmacros.h>
34 #include <sys/disp.h>
35 #include <sys/promif.h>
36 #include <sys/clock.h>
37 #include <sys/cpuvar.h>
38 #include <sys/stack.h>
39 #include <vm/as.h>
40 #include <vm/hat.h>
41 #include <sys/reboot.h>
42 #include <sys/avintr.h>
43 #include <sys/vtrace.h>
44 #include <sys/proc.h>
45 #include <sys/thread.h>
46 #include <sys/cpupart.h>
47 #include <sys/pset.h>
48 #include <sys/copyops.h>
49 #include <sys/pg.h>
50 #include <sys/disp.h>
51 #include <sys/debug.h>
52 #include <sys/sunddi.h>
53 #include <sys/x86_archext.h>
54 #include <sys/privregs.h>
55 #include <sys/machsystm.h>
56 #include <sys/ontrap.h>
57 #include <sys/bootconf.h>
58 #include <sys/boot_console.h>
59 #include <sys/kdi_machimpl.h>
60 #include <sys/archsystm.h>
61 #include <sys/promif.h>
62 #include <sys/pci_cfgspace.h>
63 #ifdef __xpv
64 #include <sys/hypervisor.h>
65 #else
66 #include <sys/xpv_support.h>
67 #endif
68
69 /*
70 * some globals for patching the result of cpuid
71 * to solve problems w/ creative cpu vendors
72 */
73
74 extern uint32_t cpuid_feature_ecx_include;
75 extern uint32_t cpuid_feature_ecx_exclude;
76 extern uint32_t cpuid_feature_edx_include;
77 extern uint32_t cpuid_feature_edx_exclude;
78
79 /*
80 * Set console mode
81 */
82 static void
83 set_console_mode(uint8_t val)
84 {
85 struct bop_regs rp = {0};
86
87 rp.eax.byte.ah = 0x0;
88 rp.eax.byte.al = val;
89 rp.ebx.word.bx = 0x0;
90
91 BOP_DOINT(bootops, 0x10, &rp);
92 }
93
94
95 /*
96 * Setup routine called right before main(). Interposing this function
97 * before main() allows us to call it in a machine-independent fashion.
98 */
99 void
100 mlsetup(struct regs *rp)
101 {
102 u_longlong_t prop_value;
103 extern struct classfuncs sys_classfuncs;
104 extern disp_t cpu0_disp;
105 extern char t0stack[];
106 extern int post_fastreboot;
107 extern uint64_t plat_dr_options;
108
109 ASSERT_STACK_ALIGNED();
110
111 /*
112 * initialize cpu_self
113 */
114 cpu[0]->cpu_self = cpu[0];
115
116 #if defined(__xpv)
117 /*
118 * Point at the hypervisor's virtual cpu structure
119 */
120 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0];
121 #endif
122
123 /*
124 * check if we've got special bits to clear or set
125 * when checking cpu features
126 */
127
128 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0)
129 cpuid_feature_ecx_include = 0;
130 else
131 cpuid_feature_ecx_include = (uint32_t)prop_value;
132
133 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0)
134 cpuid_feature_ecx_exclude = 0;
135 else
136 cpuid_feature_ecx_exclude = (uint32_t)prop_value;
137
138 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0)
139 cpuid_feature_edx_include = 0;
140 else
141 cpuid_feature_edx_include = (uint32_t)prop_value;
142
143 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0)
144 cpuid_feature_edx_exclude = 0;
145 else
146 cpuid_feature_edx_exclude = (uint32_t)prop_value;
147
148 /*
149 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss.
150 */
151 init_desctbls();
152
153 /*
154 * lgrp_init() and possibly cpuid_pass1() need PCI config
155 * space access
156 */
157 #if defined(__xpv)
158 if (DOMAIN_IS_INITDOMAIN(xen_info))
159 pci_cfgspace_init();
160 #else
161 pci_cfgspace_init();
162 /*
163 * Initialize the platform type from CPU 0 to ensure that
164 * determine_platform() is only ever called once.
165 */
166 determine_platform();
167 #endif
168
169 /*
170 * The first lightweight pass (pass0) through the cpuid data
171 * was done in locore before mlsetup was called. Do the next
172 * pass in C code.
173 *
174 * The x86_featureset is initialized here based on the capabilities
175 * of the boot CPU. Note that if we choose to support CPUs that have
176 * different feature sets (at which point we would almost certainly
177 * want to set the feature bits to correspond to the feature
178 * minimum) this value may be altered.
179 */
180 cpuid_pass1(cpu[0], x86_featureset);
181
182 #if !defined(__xpv)
183 if ((get_hwenv() & HW_XEN_HVM) != 0)
184 xen_hvm_init();
185
186 /*
187 * Patch the tsc_read routine with appropriate set of instructions,
188 * depending on the processor family and architecure, to read the
189 * time-stamp counter while ensuring no out-of-order execution.
190 * Patch it while the kernel text is still writable.
191 *
192 * Note: tsc_read is not patched for intel processors whose family
193 * is >6 and for amd whose family >f (in case they don't support rdtscp
194 * instruction, unlikely). By default tsc_read will use cpuid for
195 * serialization in such cases. The following code needs to be
196 * revisited if intel processors of family >= f retains the
197 * instruction serialization nature of mfence instruction.
198 * Note: tsc_read is not patched for x86 processors which do
199 * not support "mfence". By default tsc_read will use cpuid for
200 * serialization in such cases.
201 *
202 * The Xen hypervisor does not correctly report whether rdtscp is
203 * supported or not, so we must assume that it is not.
204 */
205 if ((get_hwenv() & HW_XEN_HVM) == 0 &&
206 is_x86_feature(x86_featureset, X86FSET_TSCP))
207 patch_tsc_read(X86_HAVE_TSCP);
208 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD &&
209 cpuid_getfamily(CPU) <= 0xf &&
210 is_x86_feature(x86_featureset, X86FSET_SSE2))
211 patch_tsc_read(X86_TSC_MFENCE);
212 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
213 cpuid_getfamily(CPU) <= 6 &&
214 is_x86_feature(x86_featureset, X86FSET_SSE2))
215 patch_tsc_read(X86_TSC_LFENCE);
216
217 #endif /* !__xpv */
218
219 #if defined(__i386) && !defined(__xpv)
220 /*
221 * Some i386 processors do not implement the rdtsc instruction,
222 * or at least they do not implement it correctly. Patch them to
223 * return 0.
224 */
225 if (!is_x86_feature(x86_featureset, X86FSET_TSC))
226 patch_tsc_read(X86_NO_TSC);
227 #endif /* __i386 && !__xpv */
228
229 #if defined(__amd64) && !defined(__xpv)
230 patch_memops(cpuid_getvendor(CPU));
231 #endif /* __amd64 && !__xpv */
232
233 #if !defined(__xpv)
234 /* XXPV what, if anything, should be dorked with here under xen? */
235
236 /*
237 * While we're thinking about the TSC, let's set up %cr4 so that
238 * userland can issue rdtsc, and initialize the TSC_AUX value
239 * (the cpuid) for the rdtscp instruction on appropriately
240 * capable hardware.
241 */
242 if (is_x86_feature(x86_featureset, X86FSET_TSC))
243 setcr4(getcr4() & ~CR4_TSD);
244
245 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
246 (void) wrmsr(MSR_AMD_TSCAUX, 0);
247
248 if (is_x86_feature(x86_featureset, X86FSET_DE))
249 setcr4(getcr4() | CR4_DE);
250 #endif /* __xpv */
251
252 /*
253 * initialize t0
254 */
255 t0.t_stk = (caddr_t)rp - MINFRAME;
256 t0.t_stkbase = t0stack;
257 t0.t_pri = maxclsyspri - 3;
258 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP;
259 t0.t_procp = &p0;
260 t0.t_plockp = &p0lock.pl_lock;
261 t0.t_lwp = &lwp0;
262 t0.t_forw = &t0;
263 t0.t_back = &t0;
264 t0.t_next = &t0;
265 t0.t_prev = &t0;
266 t0.t_cpu = cpu[0];
267 t0.t_disp_queue = &cpu0_disp;
268 t0.t_bind_cpu = PBIND_NONE;
269 t0.t_bind_pset = PS_NONE;
270 t0.t_bindflag = (uchar_t)default_binding_mode;
271 t0.t_cpupart = &cp_default;
272 t0.t_clfuncs = &sys_classfuncs.thread;
273 t0.t_copyops = NULL;
274 THREAD_ONPROC(&t0, CPU);
275
276 lwp0.lwp_thread = &t0;
277 lwp0.lwp_regs = (void *)rp;
278 lwp0.lwp_procp = &p0;
279 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1;
280
281 p0.p_exec = NULL;
282 p0.p_stat = SRUN;
283 p0.p_flag = SSYS;
284 p0.p_tlist = &t0;
285 p0.p_stksize = 2*PAGESIZE;
286 p0.p_stkpageszc = 0;
287 p0.p_as = &kas;
288 p0.p_lockp = &p0lock;
289 p0.p_brkpageszc = 0;
290 p0.p_t1_lgrpid = LGRP_NONE;
291 p0.p_tr_lgrpid = LGRP_NONE;
292 sigorset(&p0.p_ignore, &ignoredefault);
293
294 CPU->cpu_thread = &t0;
295 bzero(&cpu0_disp, sizeof (disp_t));
296 CPU->cpu_disp = &cpu0_disp;
297 CPU->cpu_disp->disp_cpu = CPU;
298 CPU->cpu_dispthread = &t0;
299 CPU->cpu_idle_thread = &t0;
300 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE;
301 CPU->cpu_dispatch_pri = t0.t_pri;
302
303 CPU->cpu_id = 0;
304
305 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */
306
307 /*
308 * The kernel doesn't use LDTs unless a process explicitly requests one.
309 */
310 p0.p_ldt_desc = null_sdesc;
311
312 /*
313 * Initialize thread/cpu microstate accounting
314 */
315 init_mstate(&t0, LMS_SYSTEM);
316 init_cpu_mstate(CPU, CMS_SYSTEM);
317
318 /*
319 * Initialize lists of available and active CPUs.
320 */
321 cpu_list_init(CPU);
322
323 pg_cpu_bootstrap(CPU);
324
325 /*
326 * Now that we have taken over the GDT, IDT and have initialized
327 * active CPU list it's time to inform kmdb if present.
328 */
329 if (boothowto & RB_DEBUG)
330 kdi_idt_sync();
331
332 /*
333 * Explicitly set console to text mode (0x3) if this is a boot
334 * post Fast Reboot, and the console is set to CONS_SCREEN_TEXT.
335 */
336 if (post_fastreboot && boot_console_type(NULL) == CONS_SCREEN_TEXT)
337 set_console_mode(0x3);
338
339 /*
340 * If requested (boot -d) drop into kmdb.
341 *
342 * This must be done after cpu_list_init() on the 64-bit kernel
343 * since taking a trap requires that we re-compute gsbase based
344 * on the cpu list.
345 */
346 if (boothowto & RB_DEBUGENTER)
347 kmdb_enter();
348
349 cpu_vm_data_init(CPU);
350
351 rp->r_fp = 0; /* terminate kernel stack traces! */
352
353 prom_init("kernel", (void *)NULL);
354
355 /* User-set option overrides firmware value. */
356 if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) {
357 plat_dr_options = (uint64_t)prop_value;
358 }
359 #if defined(__xpv)
360 /* No support of DR operations on xpv */
361 plat_dr_options = 0;
362 #else /* __xpv */
363 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */
364 plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED;
365 #ifndef __amd64
366 /* Only enable CPU/memory DR on 64 bits kernel. */
367 plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY;
368 plat_dr_options &= ~PLAT_DR_FEATURE_CPU;
369 #endif /* __amd64 */
370 #endif /* __xpv */
371
372 /*
373 * Get value of "plat_dr_physmax" boot option.
374 * It overrides values calculated from MSCT or SRAT table.
375 */
376 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) {
377 plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT;
378 }
379
380 /* Get value of boot_ncpus. */
381 if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) {
382 boot_ncpus = NCPU;
383 } else {
384 boot_ncpus = (int)prop_value;
385 if (boot_ncpus <= 0 || boot_ncpus > NCPU)
386 boot_ncpus = NCPU;
387 }
388
389 /*
390 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't
391 * support CPU DR operations.
392 */
393 if (plat_dr_support_cpu() == 0) {
394 max_ncpus = boot_max_ncpus = boot_ncpus;
395 } else {
396 if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) {
397 max_ncpus = NCPU;
398 } else {
399 max_ncpus = (int)prop_value;
400 if (max_ncpus <= 0 || max_ncpus > NCPU) {
401 max_ncpus = NCPU;
402 }
403 if (boot_ncpus > max_ncpus) {
404 boot_ncpus = max_ncpus;
405 }
406 }
407
408 if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) {
409 boot_max_ncpus = boot_ncpus;
410 } else {
411 boot_max_ncpus = (int)prop_value;
412 if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) {
413 boot_max_ncpus = boot_ncpus;
414 } else if (boot_max_ncpus > max_ncpus) {
415 boot_max_ncpus = max_ncpus;
416 }
417 }
418 }
419
420 /*
421 * Initialize the lgrp framework
422 */
423 lgrp_init(LGRP_INIT_STAGE1);
424
425 if (boothowto & RB_HALT) {
426 prom_printf("unix: kernel halted by -h flag\n");
427 prom_enter_mon();
428 }
429
430 ASSERT_STACK_ALIGNED();
431
432 /*
433 * Fill out cpu_ucode_info. Update microcode if necessary.
434 */
435 ucode_check(CPU);
436
437 if (workaround_errata(CPU) != 0)
438 panic("critical workaround(s) missing for boot cpu");
439 }
440
441
442 void
443 mach_modpath(char *path, const char *filename)
444 {
445 /*
446 * Construct the directory path from the filename.
447 */
448
449 int len;
450 char *p;
451 const char isastr[] = "/amd64";
452 size_t isalen = strlen(isastr);
453
454 if ((p = strrchr(filename, '/')) == NULL)
455 return;
456
457 while (p > filename && *(p - 1) == '/')
458 p--; /* remove trailing '/' characters */
459 if (p == filename)
460 p++; /* so "/" -is- the modpath in this case */
461
462 /*
463 * Remove optional isa-dependent directory name - the module
464 * subsystem will put this back again (!)
465 */
466 len = p - filename;
467 if (len > isalen &&
468 strncmp(&filename[len - isalen], isastr, isalen) == 0)
469 p -= isalen;
470
471 /*
472 * "/platform/mumblefrotz" + " " + MOD_DEFPATH
473 */
474 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1;
475 (void) strncpy(path, filename, p - filename);
476 }