1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
31 */
32
33 /*
34 * To understand how the pcplusmp module interacts with the interrupt subsystem
35 * read the theory statement in uts/i86pc/os/intr.c.
36 */
37
38 /*
39 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
40 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
42 * PSMI 1.5 extensions are supported in Solaris Nevada.
43 * PSMI 1.6 extensions are supported in Solaris Nevada.
44 * PSMI 1.7 extensions are supported in Solaris Nevada.
45 */
46 #define PSMI_1_7
47
48 #include <sys/processor.h>
49 #include <sys/time.h>
50 #include <sys/psm.h>
51 #include <sys/smp_impldefs.h>
52 #include <sys/cram.h>
53 #include <sys/acpi/acpi.h>
54 #include <sys/acpica.h>
55 #include <sys/psm_common.h>
56 #include <sys/apic.h>
57 #include <sys/pit.h>
58 #include <sys/ddi.h>
59 #include <sys/sunddi.h>
60 #include <sys/ddi_impldefs.h>
61 #include <sys/pci.h>
62 #include <sys/promif.h>
63 #include <sys/x86_archext.h>
64 #include <sys/cpc_impl.h>
65 #include <sys/uadmin.h>
66 #include <sys/panic.h>
67 #include <sys/debug.h>
68 #include <sys/archsystm.h>
69 #include <sys/trap.h>
70 #include <sys/machsystm.h>
71 #include <sys/sysmacros.h>
72 #include <sys/cpuvar.h>
73 #include <sys/rm_platter.h>
74 #include <sys/privregs.h>
75 #include <sys/note.h>
76 #include <sys/pci_intr_lib.h>
77 #include <sys/spl.h>
78 #include <sys/clock.h>
79 #include <sys/cyclic.h>
80 #include <sys/dditypes.h>
81 #include <sys/sunddi.h>
82 #include <sys/x_call.h>
83 #include <sys/reboot.h>
84 #include <sys/hpet.h>
85 #include <sys/apic_common.h>
86 #include <sys/apic_timer.h>
87
88 /*
89 * Local Function Prototypes
90 */
91 static void apic_init_intr(void);
92
93 /*
94 * standard MP entries
95 */
96 static int apic_probe(void);
97 static int apic_getclkirq(int ipl);
98 static void apic_init(void);
99 static void apic_picinit(void);
100 static int apic_post_cpu_start(void);
101 static int apic_intr_enter(int ipl, int *vect);
102 static void apic_setspl(int ipl);
103 static void x2apic_setspl(int ipl);
104 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
105 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
106 static int apic_disable_intr(processorid_t cpun);
107 static void apic_enable_intr(processorid_t cpun);
108 static int apic_get_ipivect(int ipl, int type);
109 static void apic_post_cyclic_setup(void *arg);
110
111 /*
112 * The following vector assignments influence the value of ipltopri and
113 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
114 * idle to 0 and IPL 0 to 0xf to differentiate idle in case
115 * we care to do so in future. Note some IPLs which are rarely used
116 * will share the vector ranges and heavily used IPLs (5 and 6) have
117 * a wide range.
118 *
119 * This array is used to initialize apic_ipls[] (in apic_init()).
120 *
121 * IPL Vector range. as passed to intr_enter
122 * 0 none.
123 * 1,2,3 0x20-0x2f 0x0-0xf
124 * 4 0x30-0x3f 0x10-0x1f
125 * 5 0x40-0x5f 0x20-0x3f
126 * 6 0x60-0x7f 0x40-0x5f
127 * 7,8,9 0x80-0x8f 0x60-0x6f
128 * 10 0x90-0x9f 0x70-0x7f
129 * 11 0xa0-0xaf 0x80-0x8f
130 * ... ...
131 * 15 0xe0-0xef 0xc0-0xcf
132 * 15 0xf0-0xff 0xd0-0xdf
133 */
134 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
135 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
136 };
137 /*
138 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
139 * NOTE that this is vector as passed into intr_enter which is
140 * programmed vector - 0x20 (APIC_BASE_VECT)
141 */
142
143 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
144 /* The taskpri to be programmed into apic to mask given ipl */
145
146 #if defined(__amd64)
147 static unsigned char dummy_cpu_pri[MAXIPL + 1];
148 #endif
149
150 /*
151 * Correlation of the hardware vector to the IPL in use, initialized
152 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
153 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
154 * connected to errata-stricken IOAPICs
155 */
156 uchar_t apic_ipls[APIC_AVAIL_VECTOR];
157
158 /*
159 * Patchable global variables.
160 */
161 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
162 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
163
164 /*
165 * Local static data
166 */
167 static struct psm_ops apic_ops = {
168 apic_probe,
169
170 apic_init,
171 apic_picinit,
172 apic_intr_enter,
173 apic_intr_exit,
174 apic_setspl,
175 apic_addspl,
176 apic_delspl,
177 apic_disable_intr,
178 apic_enable_intr,
179 (int (*)(int))NULL, /* psm_softlvl_to_irq */
180 (void (*)(int))NULL, /* psm_set_softintr */
181
182 apic_set_idlecpu,
183 apic_unset_idlecpu,
184
185 apic_clkinit,
186 apic_getclkirq,
187 (void (*)(void))NULL, /* psm_hrtimeinit */
188 apic_gethrtime,
189
190 apic_get_next_processorid,
191 apic_cpu_start,
192 apic_post_cpu_start,
193 apic_shutdown,
194 apic_get_ipivect,
195 apic_send_ipi,
196
197 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
198 (void (*)(int, char *))NULL, /* psm_notify_error */
199 (void (*)(int))NULL, /* psm_notify_func */
200 apic_timer_reprogram,
201 apic_timer_enable,
202 apic_timer_disable,
203 apic_post_cyclic_setup,
204 apic_preshutdown,
205 apic_intr_ops, /* Advanced DDI Interrupt framework */
206 apic_state, /* save, restore apic state for S3 */
207 apic_cpu_ops, /* CPU control interface. */
208 };
209
210 struct psm_ops *psmops = &apic_ops;
211
212 static struct psm_info apic_psm_info = {
213 PSM_INFO_VER01_7, /* version */
214 PSM_OWN_EXCLUSIVE, /* ownership */
215 (struct psm_ops *)&apic_ops, /* operation */
216 APIC_PCPLUSMP_NAME, /* machine name */
217 "pcplusmp v1.4 compatible",
218 };
219
220 static void *apic_hdlp;
221
222 /*
223 * apic_let_idle_redistribute can have the following values:
224 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute.
225 * apic_redistribute_lock prevents multiple idle cpus from redistributing
226 */
227 int apic_num_idle_redistributions = 0;
228 static int apic_let_idle_redistribute = 0;
229
230 /* to gather intr data and redistribute */
231 static void apic_redistribute_compute(void);
232
233 /*
234 * This is the loadable module wrapper
235 */
236
237 int
238 _init(void)
239 {
240 if (apic_coarse_hrtime)
241 apic_ops.psm_gethrtime = &apic_gettime;
242 return (psm_mod_init(&apic_hdlp, &apic_psm_info));
243 }
244
245 int
246 _fini(void)
247 {
248 return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
249 }
250
251 int
252 _info(struct modinfo *modinfop)
253 {
254 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
255 }
256
257 static int
258 apic_probe(void)
259 {
260 /* check if apix is initialized */
261 if (apix_enable && apix_loaded())
262 return (PSM_FAILURE);
263 else
264 apix_enable = 0; /* continue using pcplusmp PSM */
265
266 return (apic_probe_common(apic_psm_info.p_mach_idstring));
267 }
268
269 static uchar_t
270 apic_xlate_vector_by_irq(uchar_t irq)
271 {
272 if (apic_irq_table[irq] == NULL)
273 return (0);
274
275 return (apic_irq_table[irq]->airq_vector);
276 }
277
278 void
279 apic_init(void)
280 {
281 int i;
282 int j = 1;
283
284 psm_get_ioapicid = apic_get_ioapicid;
285 psm_get_localapicid = apic_get_localapicid;
286 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
287
288 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
289 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
290 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
291 (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
292 /* get to highest vector at the same ipl */
293 continue;
294 for (; j <= apic_vectortoipl[i]; j++) {
295 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
296 APIC_BASE_VECT;
297 }
298 }
299 for (; j < MAXIPL + 1; j++)
300 /* fill up any empty ipltopri slots */
301 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
302 apic_init_common();
303 #if defined(__amd64)
304 CPU->cpu_pri_data = dummy_cpu_pri;
305 #else
306 if (cpuid_have_cr8access(CPU))
307 apic_have_32bit_cr8 = 1;
308 #endif /* __amd64 */
309 }
310
311 static void
312 apic_init_intr(void)
313 {
314 processorid_t cpun = psm_get_cpu_id();
315 uint_t nlvt;
316 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
317
318 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
319
320 if (apic_mode == LOCAL_APIC) {
321 /*
322 * We are running APIC in MMIO mode.
323 */
324 if (apic_flat_model) {
325 apic_reg_ops->apic_write(APIC_FORMAT_REG,
326 APIC_FLAT_MODEL);
327 } else {
328 apic_reg_ops->apic_write(APIC_FORMAT_REG,
329 APIC_CLUSTER_MODEL);
330 }
331
332 apic_reg_ops->apic_write(APIC_DEST_REG,
333 AV_HIGH_ORDER >> cpun);
334 }
335
336 if (apic_directed_EOI_supported()) {
337 /*
338 * Setting the 12th bit in the Spurious Interrupt Vector
339 * Register suppresses broadcast EOIs generated by the local
340 * APIC. The suppression of broadcast EOIs happens only when
341 * interrupts are level-triggered.
342 */
343 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
344 }
345
346 /* need to enable APIC before unmasking NMI */
347 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
348
349 /*
350 * Presence of an invalid vector with delivery mode AV_FIXED can
351 * cause an error interrupt, even if the entry is masked...so
352 * write a valid vector to LVT entries along with the mask bit
353 */
354
355 /* All APICs have timer and LINT0/1 */
356 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
357 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
358 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
359
360 /*
361 * On integrated APICs, the number of LVT entries is
362 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
363 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
364 */
365
366 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
367 nlvt = 3;
368 } else {
369 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
370 0xFF) + 1;
371 }
372
373 if (nlvt >= 5) {
374 /* Enable performance counter overflow interrupt */
375
376 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
377 apic_enable_cpcovf_intr = 0;
378 if (apic_enable_cpcovf_intr) {
379 if (apic_cpcovf_vect == 0) {
380 int ipl = APIC_PCINT_IPL;
381 int irq = apic_get_ipivect(ipl, -1);
382
383 ASSERT(irq != -1);
384 apic_cpcovf_vect =
385 apic_irq_table[irq]->airq_vector;
386 ASSERT(apic_cpcovf_vect);
387 (void) add_avintr(NULL, ipl,
388 (avfunc)kcpc_hw_overflow_intr,
389 "apic pcint", irq, NULL, NULL, NULL, NULL);
390 kcpc_hw_overflow_intr_installed = 1;
391 kcpc_hw_enable_cpc_intr =
392 apic_cpcovf_mask_clear;
393 }
394 apic_reg_ops->apic_write(APIC_PCINT_VECT,
395 apic_cpcovf_vect);
396 }
397 }
398
399 if (nlvt >= 6) {
400 /* Only mask TM intr if the BIOS apparently doesn't use it */
401
402 uint32_t lvtval;
403
404 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
405 if (((lvtval & AV_MASK) == AV_MASK) ||
406 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
407 apic_reg_ops->apic_write(APIC_THERM_VECT,
408 AV_MASK|APIC_RESV_IRQ);
409 }
410 }
411
412 /* Enable error interrupt */
413
414 if (nlvt >= 4 && apic_enable_error_intr) {
415 if (apic_errvect == 0) {
416 int ipl = 0xf; /* get highest priority intr */
417 int irq = apic_get_ipivect(ipl, -1);
418
419 ASSERT(irq != -1);
420 apic_errvect = apic_irq_table[irq]->airq_vector;
421 ASSERT(apic_errvect);
422 /*
423 * Not PSMI compliant, but we are going to merge
424 * with ON anyway
425 */
426 (void) add_avintr((void *)NULL, ipl,
427 (avfunc)apic_error_intr, "apic error intr",
428 irq, NULL, NULL, NULL, NULL);
429 }
430 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
431 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
432 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
433 }
434
435 /* Enable CMCI interrupt */
436 if (cmi_enable_cmci) {
437
438 mutex_enter(&cmci_cpu_setup_lock);
439 if (cmci_cpu_setup_registered == 0) {
440 mutex_enter(&cpu_lock);
441 register_cpu_setup_func(cmci_cpu_setup, NULL);
442 mutex_exit(&cpu_lock);
443 cmci_cpu_setup_registered = 1;
444 }
445 mutex_exit(&cmci_cpu_setup_lock);
446
447 if (apic_cmci_vect == 0) {
448 int ipl = 0x2;
449 int irq = apic_get_ipivect(ipl, -1);
450
451 ASSERT(irq != -1);
452 apic_cmci_vect = apic_irq_table[irq]->airq_vector;
453 ASSERT(apic_cmci_vect);
454
455 (void) add_avintr(NULL, ipl,
456 (avfunc)cmi_cmci_trap,
457 "apic cmci intr", irq, NULL, NULL, NULL, NULL);
458 }
459 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect);
460 }
461 }
462
463 static void
464 apic_picinit(void)
465 {
466 int i, j;
467 uint_t isr;
468
469 /*
470 * Initialize and enable interrupt remapping before apic
471 * hardware initialization
472 */
473 apic_intrmap_init(apic_mode);
474
475 /*
476 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
477 * bit on without clearing it with EOI. Since softint
478 * uses vector 0x20 to interrupt itself, so softint will
479 * not work on this machine. In order to fix this problem
480 * a check is made to verify all the isr bits are clear.
481 * If not, EOIs are issued to clear the bits.
482 */
483 for (i = 7; i >= 1; i--) {
484 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
485 if (isr != 0)
486 for (j = 0; ((j < 32) && (isr != 0)); j++)
487 if (isr & (1 << j)) {
488 apic_reg_ops->apic_write(
489 APIC_EOI_REG, 0);
490 isr &= ~(1 << j);
491 apic_error |= APIC_ERR_BOOT_EOI;
492 }
493 }
494
495 /* set a flag so we know we have run apic_picinit() */
496 apic_picinit_called = 1;
497 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
498 LOCK_INIT_CLEAR(&apic_ioapic_lock);
499 LOCK_INIT_CLEAR(&apic_error_lock);
500 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
501
502 picsetup(); /* initialise the 8259 */
503
504 /* add nmi handler - least priority nmi handler */
505 LOCK_INIT_CLEAR(&apic_nmi_lock);
506
507 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
508 "pcplusmp NMI handler", (caddr_t)NULL))
509 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
510
511 /*
512 * Check for directed-EOI capability in the local APIC.
513 */
514 if (apic_directed_EOI_supported() == 1) {
515 apic_set_directed_EOI_handler();
516 }
517
518 apic_init_intr();
519
520 /* enable apic mode if imcr present */
521 if (apic_imcrp) {
522 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
523 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
524 }
525
526 ioapic_init_intr(IOAPIC_MASK);
527 }
528
529 #ifdef DEBUG
530 void
531 apic_break(void)
532 {
533 }
534 #endif /* DEBUG */
535
536 /*
537 * platform_intr_enter
538 *
539 * Called at the beginning of the interrupt service routine to
540 * mask all level equal to and below the interrupt priority
541 * of the interrupting vector. An EOI should be given to
542 * the interrupt controller to enable other HW interrupts.
543 *
544 * Return -1 for spurious interrupts
545 *
546 */
547 /*ARGSUSED*/
548 static int
549 apic_intr_enter(int ipl, int *vectorp)
550 {
551 uchar_t vector;
552 int nipl;
553 int irq;
554 ulong_t iflag;
555 apic_cpus_info_t *cpu_infop;
556
557 /*
558 * The real vector delivered is (*vectorp + 0x20), but our caller
559 * subtracts 0x20 from the vector before passing it to us.
560 * (That's why APIC_BASE_VECT is 0x20.)
561 */
562 vector = (uchar_t)*vectorp;
563
564 /* if interrupted by the clock, increment apic_nsec_since_boot */
565 if (vector == apic_clkvect) {
566 if (!apic_oneshot) {
567 /* NOTE: this is not MT aware */
568 apic_hrtime_stamp++;
569 apic_nsec_since_boot += apic_nsec_per_intr;
570 apic_hrtime_stamp++;
571 last_count_read = apic_hertz_count;
572 apic_redistribute_compute();
573 }
574
575 /* We will avoid all the book keeping overhead for clock */
576 nipl = apic_ipls[vector];
577
578 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
579 if (apic_mode == LOCAL_APIC) {
580 #if defined(__amd64)
581 setcr8((ulong_t)(apic_ipltopri[nipl] >>
582 APIC_IPL_SHIFT));
583 #else
584 if (apic_have_32bit_cr8)
585 setcr8((ulong_t)(apic_ipltopri[nipl] >>
586 APIC_IPL_SHIFT));
587 else
588 LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
589 (uint32_t)apic_ipltopri[nipl]);
590 #endif
591 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
592 } else {
593 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
594 X2APIC_WRITE(APIC_EOI_REG, 0);
595 }
596
597 return (nipl);
598 }
599
600 cpu_infop = &apic_cpus[psm_get_cpu_id()];
601
602 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
603 cpu_infop->aci_spur_cnt++;
604 return (APIC_INT_SPURIOUS);
605 }
606
607 /* Check if the vector we got is really what we need */
608 if (apic_revector_pending) {
609 /*
610 * Disable interrupts for the duration of
611 * the vector translation to prevent a self-race for
612 * the apic_revector_lock. This cannot be done
613 * in apic_xlate_vector because it is recursive and
614 * we want the vector translation to be atomic with
615 * respect to other (higher-priority) interrupts.
616 */
617 iflag = intr_clear();
618 vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
619 APIC_BASE_VECT;
620 intr_restore(iflag);
621 }
622
623 nipl = apic_ipls[vector];
624 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
625
626 if (apic_mode == LOCAL_APIC) {
627 #if defined(__amd64)
628 setcr8((ulong_t)(apic_ipltopri[nipl] >> APIC_IPL_SHIFT));
629 #else
630 if (apic_have_32bit_cr8)
631 setcr8((ulong_t)(apic_ipltopri[nipl] >>
632 APIC_IPL_SHIFT));
633 else
634 LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
635 (uint32_t)apic_ipltopri[nipl]);
636 #endif
637 } else {
638 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
639 }
640
641 cpu_infop->aci_current[nipl] = (uchar_t)irq;
642 cpu_infop->aci_curipl = (uchar_t)nipl;
643 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
644
645 /*
646 * apic_level_intr could have been assimilated into the irq struct.
647 * but, having it as a character array is more efficient in terms of
648 * cache usage. So, we leave it as is.
649 */
650 if (!apic_level_intr[irq]) {
651 if (apic_mode == LOCAL_APIC) {
652 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
653 } else {
654 X2APIC_WRITE(APIC_EOI_REG, 0);
655 }
656 }
657
658 #ifdef DEBUG
659 APIC_DEBUG_BUF_PUT(vector);
660 APIC_DEBUG_BUF_PUT(irq);
661 APIC_DEBUG_BUF_PUT(nipl);
662 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
663 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
664 drv_usecwait(apic_stretch_interrupts);
665
666 if (apic_break_on_cpu == psm_get_cpu_id())
667 apic_break();
668 #endif /* DEBUG */
669 return (nipl);
670 }
671
672 /*
673 * This macro is a common code used by MMIO local apic and X2APIC
674 * local apic.
675 */
676 #define APIC_INTR_EXIT() \
677 { \
678 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \
679 if (apic_level_intr[irq]) \
680 apic_reg_ops->apic_send_eoi(irq); \
681 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \
682 /* ISR above current pri could not be in progress */ \
683 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \
684 }
685
686 /*
687 * Any changes made to this function must also change X2APIC
688 * version of intr_exit.
689 */
690 void
691 apic_intr_exit(int prev_ipl, int irq)
692 {
693 apic_cpus_info_t *cpu_infop;
694
695 #if defined(__amd64)
696 setcr8((ulong_t)(apic_ipltopri[prev_ipl] >> APIC_IPL_SHIFT));
697 #else
698 if (apic_have_32bit_cr8)
699 setcr8((ulong_t)(apic_ipltopri[prev_ipl] >> APIC_IPL_SHIFT));
700 else
701 apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl];
702 #endif
703
704 APIC_INTR_EXIT();
705 }
706
707 /*
708 * Same as apic_intr_exit() except it uses MSR rather than MMIO
709 * to access local apic registers.
710 */
711 void
712 x2apic_intr_exit(int prev_ipl, int irq)
713 {
714 apic_cpus_info_t *cpu_infop;
715
716 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]);
717 APIC_INTR_EXIT();
718 }
719
720 intr_exit_fn_t
721 psm_intr_exit_fn(void)
722 {
723 if (apic_mode == LOCAL_X2APIC)
724 return (x2apic_intr_exit);
725
726 return (apic_intr_exit);
727 }
728
729 /*
730 * Mask all interrupts below or equal to the given IPL.
731 * Any changes made to this function must also change X2APIC
732 * version of setspl.
733 */
734 static void
735 apic_setspl(int ipl)
736 {
737 #if defined(__amd64)
738 setcr8((ulong_t)(apic_ipltopri[ipl] >> APIC_IPL_SHIFT));
739 #else
740 if (apic_have_32bit_cr8)
741 setcr8((ulong_t)(apic_ipltopri[ipl] >> APIC_IPL_SHIFT));
742 else
743 apicadr[APIC_TASK_REG] = apic_ipltopri[ipl];
744 #endif
745
746 /* interrupts at ipl above this cannot be in progress */
747 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
748 /*
749 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
750 * have enough time to come in before the priority is raised again
751 * during the idle() loop.
752 */
753 if (apic_setspl_delay)
754 (void) apic_reg_ops->apic_get_pri();
755 }
756
757 /*
758 * X2APIC version of setspl.
759 * Mask all interrupts below or equal to the given IPL
760 */
761 static void
762 x2apic_setspl(int ipl)
763 {
764 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]);
765
766 /* interrupts at ipl above this cannot be in progress */
767 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
768 }
769
770 /*ARGSUSED*/
771 static int
772 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
773 {
774 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
775 }
776
777 static int
778 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
779 {
780 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
781 }
782
783 static int
784 apic_post_cpu_start(void)
785 {
786 int cpun;
787 static int cpus_started = 1;
788
789 /* We know this CPU + BSP started successfully. */
790 cpus_started++;
791
792 /*
793 * On BSP we would have enabled X2APIC, if supported by processor,
794 * in acpi_probe(), but on AP we do it here.
795 *
796 * We enable X2APIC mode only if BSP is running in X2APIC & the
797 * local APIC mode of the current CPU is MMIO (xAPIC).
798 */
799 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
800 apic_local_mode() == LOCAL_APIC) {
801 apic_enable_x2apic();
802 }
803
804 /*
805 * Switch back to x2apic IPI sending method for performance when target
806 * CPU has entered x2apic mode.
807 */
808 if (apic_mode == LOCAL_X2APIC) {
809 apic_switch_ipi_callback(B_FALSE);
810 }
811
812 splx(ipltospl(LOCK_LEVEL));
813 apic_init_intr();
814
815 /*
816 * since some systems don't enable the internal cache on the non-boot
817 * cpus, so we have to enable them here
818 */
819 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
820
821 #ifdef DEBUG
822 APIC_AV_PENDING_SET();
823 #else
824 if (apic_mode == LOCAL_APIC)
825 APIC_AV_PENDING_SET();
826 #endif /* DEBUG */
827
828 /*
829 * We may be booting, or resuming from suspend; aci_status will
830 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
831 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
832 */
833 cpun = psm_get_cpu_id();
834 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
835
836 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
837 return (PSM_SUCCESS);
838 }
839
840 /*
841 * type == -1 indicates it is an internal request. Do not change
842 * resv_vector for these requests
843 */
844 static int
845 apic_get_ipivect(int ipl, int type)
846 {
847 uchar_t vector;
848 int irq;
849
850 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
851 if (vector = apic_allocate_vector(ipl, irq, 1)) {
852 apic_irq_table[irq]->airq_mps_intr_index =
853 RESERVE_INDEX;
854 apic_irq_table[irq]->airq_vector = vector;
855 if (type != -1) {
856 apic_resv_vector[ipl] = vector;
857 }
858 return (irq);
859 }
860 }
861 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
862 return (-1); /* shouldn't happen */
863 }
864
865 static int
866 apic_getclkirq(int ipl)
867 {
868 int irq;
869
870 if ((irq = apic_get_ipivect(ipl, -1)) == -1)
871 return (-1);
872 /*
873 * Note the vector in apic_clkvect for per clock handling.
874 */
875 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
876 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
877 apic_clkvect));
878 return (irq);
879 }
880
881 /*
882 * Try and disable all interrupts. We just assign interrupts to other
883 * processors based on policy. If any were bound by user request, we
884 * let them continue and return failure. We do not bother to check
885 * for cache affinity while rebinding.
886 */
887
888 static int
889 apic_disable_intr(processorid_t cpun)
890 {
891 int bind_cpu = 0, i, hardbound = 0;
892 apic_irq_t *irq_ptr;
893 ulong_t iflag;
894
895 iflag = intr_clear();
896 lock_set(&apic_ioapic_lock);
897
898 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
899 if (apic_reprogram_info[i].done == B_FALSE) {
900 if (apic_reprogram_info[i].bindcpu == cpun) {
901 /*
902 * CPU is busy -- it's the target of
903 * a pending reprogramming attempt
904 */
905 lock_clear(&apic_ioapic_lock);
906 intr_restore(iflag);
907 return (PSM_FAILURE);
908 }
909 }
910 }
911
912 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
913
914 apic_cpus[cpun].aci_curipl = 0;
915
916 i = apic_min_device_irq;
917 for (; i <= apic_max_device_irq; i++) {
918 /*
919 * If there are bound interrupts on this cpu, then
920 * rebind them to other processors.
921 */
922 if ((irq_ptr = apic_irq_table[i]) != NULL) {
923 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
924 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
925 (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
926
927 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
928 hardbound = 1;
929 continue;
930 }
931
932 if (irq_ptr->airq_temp_cpu == cpun) {
933 do {
934 bind_cpu =
935 apic_find_cpu(APIC_CPU_INTR_ENABLE);
936 } while (apic_rebind_all(irq_ptr, bind_cpu));
937 }
938 }
939 }
940
941 lock_clear(&apic_ioapic_lock);
942 intr_restore(iflag);
943
944 if (hardbound) {
945 cmn_err(CE_WARN, "Could not disable interrupts on %d"
946 "due to user bound interrupts", cpun);
947 return (PSM_FAILURE);
948 }
949 else
950 return (PSM_SUCCESS);
951 }
952
953 /*
954 * Bind interrupts to the CPU's local APIC.
955 * Interrupts should not be bound to a CPU's local APIC until the CPU
956 * is ready to receive interrupts.
957 */
958 static void
959 apic_enable_intr(processorid_t cpun)
960 {
961 int i;
962 apic_irq_t *irq_ptr;
963 ulong_t iflag;
964
965 iflag = intr_clear();
966 lock_set(&apic_ioapic_lock);
967
968 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
969
970 i = apic_min_device_irq;
971 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
972 if ((irq_ptr = apic_irq_table[i]) != NULL) {
973 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
974 (void) apic_rebind_all(irq_ptr,
975 irq_ptr->airq_cpu);
976 }
977 }
978 }
979
980 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
981 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
982
983 lock_clear(&apic_ioapic_lock);
984 intr_restore(iflag);
985 }
986
987 /*
988 * If this module needs a periodic handler for the interrupt distribution, it
989 * can be added here. The argument to the periodic handler is not currently
990 * used, but is reserved for future.
991 */
992 static void
993 apic_post_cyclic_setup(void *arg)
994 {
995 _NOTE(ARGUNUSED(arg))
996
997 cyc_handler_t cyh;
998 cyc_time_t cyt;
999
1000 /* cpu_lock is held */
1001 /* set up a periodic handler for intr redistribution */
1002
1003 /*
1004 * In peridoc mode intr redistribution processing is done in
1005 * apic_intr_enter during clk intr processing
1006 */
1007 if (!apic_oneshot)
1008 return;
1009
1010 /*
1011 * Register a periodical handler for the redistribution processing.
1012 * Though we would generally prefer to use the DDI interface for
1013 * periodic handler invocation, ddi_periodic_add(9F), we are
1014 * unfortunately already holding cpu_lock, which ddi_periodic_add will
1015 * attempt to take for us. Thus, we add our own cyclic directly:
1016 */
1017 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
1018 cyh.cyh_arg = NULL;
1019 cyh.cyh_level = CY_LOW_LEVEL;
1020
1021 cyt.cyt_when = 0;
1022 cyt.cyt_interval = apic_redistribute_sample_interval;
1023
1024 apic_cyclic_id = cyclic_add(&cyh, &cyt);
1025 }
1026
1027 static void
1028 apic_redistribute_compute(void)
1029 {
1030 int i, j, max_busy;
1031
1032 if (apic_enable_dynamic_migration) {
1033 if (++apic_nticks == apic_sample_factor_redistribution) {
1034 /*
1035 * Time to call apic_intr_redistribute().
1036 * reset apic_nticks. This will cause max_busy
1037 * to be calculated below and if it is more than
1038 * apic_int_busy, we will do the whole thing
1039 */
1040 apic_nticks = 0;
1041 }
1042 max_busy = 0;
1043 for (i = 0; i < apic_nproc; i++) {
1044 if (!apic_cpu_in_range(i))
1045 continue;
1046
1047 /*
1048 * Check if curipl is non zero & if ISR is in
1049 * progress
1050 */
1051 if (((j = apic_cpus[i].aci_curipl) != 0) &&
1052 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1053
1054 int irq;
1055 apic_cpus[i].aci_busy++;
1056 irq = apic_cpus[i].aci_current[j];
1057 apic_irq_table[irq]->airq_busy++;
1058 }
1059
1060 if (!apic_nticks &&
1061 (apic_cpus[i].aci_busy > max_busy))
1062 max_busy = apic_cpus[i].aci_busy;
1063 }
1064 if (!apic_nticks) {
1065 if (max_busy > apic_int_busy_mark) {
1066 /*
1067 * We could make the following check be
1068 * skipped > 1 in which case, we get a
1069 * redistribution at half the busy mark (due to
1070 * double interval). Need to be able to collect
1071 * more empirical data to decide if that is a
1072 * good strategy. Punt for now.
1073 */
1074 if (apic_skipped_redistribute) {
1075 apic_cleanup_busy();
1076 apic_skipped_redistribute = 0;
1077 } else {
1078 apic_intr_redistribute();
1079 }
1080 } else
1081 apic_skipped_redistribute++;
1082 }
1083 }
1084 }
1085
1086
1087 /*
1088 * The following functions are in the platform specific file so that they
1089 * can be different functions depending on whether we are running on
1090 * bare metal or a hypervisor.
1091 */
1092
1093 /*
1094 * Check to make sure there are enough irq slots
1095 */
1096 int
1097 apic_check_free_irqs(int count)
1098 {
1099 int i, avail;
1100
1101 avail = 0;
1102 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1103 if ((apic_irq_table[i] == NULL) ||
1104 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
1105 if (++avail >= count)
1106 return (PSM_SUCCESS);
1107 }
1108 }
1109 return (PSM_FAILURE);
1110 }
1111
1112 /*
1113 * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
1114 */
1115 int
1116 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
1117 int behavior)
1118 {
1119 int rcount, i;
1120 uchar_t start, irqno;
1121 uint32_t cpu;
1122 major_t major;
1123 apic_irq_t *irqptr;
1124
1125 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
1126 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1127 (void *)dip, inum, pri, count, behavior));
1128
1129 if (count > 1) {
1130 if (behavior == DDI_INTR_ALLOC_STRICT &&
1131 apic_multi_msi_enable == 0)
1132 return (0);
1133 if (apic_multi_msi_enable == 0)
1134 count = 1;
1135 }
1136
1137 if ((rcount = apic_navail_vector(dip, pri)) > count)
1138 rcount = count;
1139 else if (rcount == 0 || (rcount < count &&
1140 behavior == DDI_INTR_ALLOC_STRICT))
1141 return (0);
1142
1143 /* if not ISP2, then round it down */
1144 if (!ISP2(rcount))
1145 rcount = 1 << (highbit(rcount) - 1);
1146
1147 mutex_enter(&airq_mutex);
1148
1149 for (start = 0; rcount > 0; rcount >>= 1) {
1150 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1151 behavior == DDI_INTR_ALLOC_STRICT)
1152 break;
1153 }
1154
1155 if (start == 0) {
1156 /* no vector available */
1157 mutex_exit(&airq_mutex);
1158 return (0);
1159 }
1160
1161 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1162 /* not enough free irq slots available */
1163 mutex_exit(&airq_mutex);
1164 return (0);
1165 }
1166
1167 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1168 for (i = 0; i < rcount; i++) {
1169 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1170 (uchar_t)-1) {
1171 /*
1172 * shouldn't happen because of the
1173 * apic_check_free_irqs() check earlier
1174 */
1175 mutex_exit(&airq_mutex);
1176 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1177 "apic_allocate_irq failed\n"));
1178 return (i);
1179 }
1180 apic_max_device_irq = max(irqno, apic_max_device_irq);
1181 apic_min_device_irq = min(irqno, apic_min_device_irq);
1182 irqptr = apic_irq_table[irqno];
1183 #ifdef DEBUG
1184 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1185 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1186 "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1187 #endif
1188 apic_vector_to_irq[start + i] = (uchar_t)irqno;
1189
1190 irqptr->airq_vector = (uchar_t)(start + i);
1191 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1192 irqptr->airq_intin_no = (uchar_t)rcount;
1193 irqptr->airq_ipl = pri;
1194 irqptr->airq_vector = start + i;
1195 irqptr->airq_origirq = (uchar_t)(inum + i);
1196 irqptr->airq_share_id = 0;
1197 irqptr->airq_mps_intr_index = MSI_INDEX;
1198 irqptr->airq_dip = dip;
1199 irqptr->airq_major = major;
1200 if (i == 0) /* they all bound to the same cpu */
1201 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
1202 0xff, 0xff);
1203 else
1204 irqptr->airq_cpu = cpu;
1205 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1206 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1207 (void *)irqptr->airq_dip, irqptr->airq_vector,
1208 irqptr->airq_origirq, pri));
1209 }
1210 mutex_exit(&airq_mutex);
1211 return (rcount);
1212 }
1213
1214 /*
1215 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1216 */
1217 int
1218 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1219 int behavior)
1220 {
1221 int rcount, i;
1222 major_t major;
1223
1224 mutex_enter(&airq_mutex);
1225
1226 if ((rcount = apic_navail_vector(dip, pri)) > count)
1227 rcount = count;
1228 else if (rcount == 0 || (rcount < count &&
1229 behavior == DDI_INTR_ALLOC_STRICT)) {
1230 rcount = 0;
1231 goto out;
1232 }
1233
1234 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1235 /* not enough free irq slots available */
1236 rcount = 0;
1237 goto out;
1238 }
1239
1240 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1241 for (i = 0; i < rcount; i++) {
1242 uchar_t vector, irqno;
1243 apic_irq_t *irqptr;
1244
1245 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1246 (uchar_t)-1) {
1247 /*
1248 * shouldn't happen because of the
1249 * apic_check_free_irqs() check earlier
1250 */
1251 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1252 "apic_allocate_irq failed\n"));
1253 rcount = i;
1254 goto out;
1255 }
1256 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1257 /*
1258 * shouldn't happen because of the
1259 * apic_navail_vector() call earlier
1260 */
1261 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1262 "apic_allocate_vector failed\n"));
1263 rcount = i;
1264 goto out;
1265 }
1266 apic_max_device_irq = max(irqno, apic_max_device_irq);
1267 apic_min_device_irq = min(irqno, apic_min_device_irq);
1268 irqptr = apic_irq_table[irqno];
1269 irqptr->airq_vector = (uchar_t)vector;
1270 irqptr->airq_ipl = pri;
1271 irqptr->airq_origirq = (uchar_t)(inum + i);
1272 irqptr->airq_share_id = 0;
1273 irqptr->airq_mps_intr_index = MSIX_INDEX;
1274 irqptr->airq_dip = dip;
1275 irqptr->airq_major = major;
1276 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1277 }
1278 out:
1279 mutex_exit(&airq_mutex);
1280 return (rcount);
1281 }
1282
1283 /*
1284 * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1285 * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1286 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1287 * requests and allocated only when pri is set.
1288 */
1289 uchar_t
1290 apic_allocate_vector(int ipl, int irq, int pri)
1291 {
1292 int lowest, highest, i;
1293
1294 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1295 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1296
1297 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1298 lowest -= APIC_VECTOR_PER_IPL;
1299
1300 #ifdef DEBUG
1301 if (apic_restrict_vector) /* for testing shared interrupt logic */
1302 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1303 #endif /* DEBUG */
1304 if (pri == 0)
1305 highest -= APIC_HI_PRI_VECTS;
1306
1307 for (i = lowest; i <= highest; i++) {
1308 if (APIC_CHECK_RESERVE_VECTORS(i))
1309 continue;
1310 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1311 apic_vector_to_irq[i] = (uchar_t)irq;
1312 return (i);
1313 }
1314 }
1315
1316 return (0);
1317 }
1318
1319 /* Mark vector as not being used by any irq */
1320 void
1321 apic_free_vector(uchar_t vector)
1322 {
1323 apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1324 }
1325
1326 /*
1327 * Call rebind to do the actual programming.
1328 * Must be called with interrupts disabled and apic_ioapic_lock held
1329 * 'p' is polymorphic -- if this function is called to process a deferred
1330 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1331 * the irq pointer is retrieved. If not doing deferred reprogramming,
1332 * p is of the type 'apic_irq_t *'.
1333 *
1334 * apic_ioapic_lock must be held across this call, as it protects apic_rebind
1335 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1336 * taken offline after a cpu is selected, but before apic_rebind is called to
1337 * bind interrupts to it.
1338 */
1339 int
1340 apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1341 {
1342 apic_irq_t *irqptr;
1343 struct ioapic_reprogram_data *drep = NULL;
1344 int rv;
1345
1346 if (deferred) {
1347 drep = (struct ioapic_reprogram_data *)p;
1348 ASSERT(drep != NULL);
1349 irqptr = drep->irqp;
1350 } else
1351 irqptr = (apic_irq_t *)p;
1352
1353 ASSERT(irqptr != NULL);
1354
1355 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1356 if (rv) {
1357 /*
1358 * CPU is not up or interrupts are disabled. Fall back to
1359 * the first available CPU
1360 */
1361 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1362 drep);
1363 }
1364
1365 return (rv);
1366 }
1367
1368
1369 uchar_t
1370 apic_modify_vector(uchar_t vector, int irq)
1371 {
1372 apic_vector_to_irq[vector] = (uchar_t)irq;
1373 return (vector);
1374 }
1375
1376 char *
1377 apic_get_apic_type(void)
1378 {
1379 return (apic_psm_info.p_mach_idstring);
1380 }
1381
1382 void
1383 x2apic_update_psm(void)
1384 {
1385 struct psm_ops *pops = &apic_ops;
1386
1387 ASSERT(pops != NULL);
1388
1389 pops->psm_intr_exit = x2apic_intr_exit;
1390 pops->psm_setspl = x2apic_setspl;
1391
1392 pops->psm_send_ipi = x2apic_send_ipi;
1393 send_dirintf = pops->psm_send_ipi;
1394
1395 apic_mode = LOCAL_X2APIC;
1396 apic_change_ops();
1397 }