Print this page
4663 apic_cr8pri complicates pcplusmp
Split |
Close |
Expand all |
Collapse all |
--- old/usr/src/uts/i86pc/io/apix/apix.c
+++ new/usr/src/uts/i86pc/io/apix/apix.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
31 31 */
32 32
33 33 /*
34 34 * To understand how the apix module interacts with the interrupt subsystem read
35 35 * the theory statement in uts/i86pc/os/intr.c.
36 36 */
37 37
38 38 /*
39 39 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
40 40 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
41 41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
42 42 * PSMI 1.5 extensions are supported in Solaris Nevada.
43 43 * PSMI 1.6 extensions are supported in Solaris Nevada.
44 44 * PSMI 1.7 extensions are supported in Solaris Nevada.
45 45 */
46 46 #define PSMI_1_7
47 47
48 48 #include <sys/processor.h>
49 49 #include <sys/time.h>
50 50 #include <sys/psm.h>
51 51 #include <sys/smp_impldefs.h>
52 52 #include <sys/cram.h>
53 53 #include <sys/acpi/acpi.h>
54 54 #include <sys/acpica.h>
55 55 #include <sys/psm_common.h>
56 56 #include <sys/pit.h>
57 57 #include <sys/ddi.h>
58 58 #include <sys/sunddi.h>
59 59 #include <sys/ddi_impldefs.h>
60 60 #include <sys/pci.h>
61 61 #include <sys/promif.h>
62 62 #include <sys/x86_archext.h>
63 63 #include <sys/cpc_impl.h>
64 64 #include <sys/uadmin.h>
65 65 #include <sys/panic.h>
66 66 #include <sys/debug.h>
67 67 #include <sys/archsystm.h>
68 68 #include <sys/trap.h>
69 69 #include <sys/machsystm.h>
70 70 #include <sys/sysmacros.h>
71 71 #include <sys/cpuvar.h>
72 72 #include <sys/rm_platter.h>
73 73 #include <sys/privregs.h>
74 74 #include <sys/note.h>
75 75 #include <sys/pci_intr_lib.h>
76 76 #include <sys/spl.h>
77 77 #include <sys/clock.h>
78 78 #include <sys/cyclic.h>
79 79 #include <sys/dditypes.h>
80 80 #include <sys/sunddi.h>
81 81 #include <sys/x_call.h>
82 82 #include <sys/reboot.h>
83 83 #include <sys/mach_intr.h>
84 84 #include <sys/apix.h>
85 85 #include <sys/apix_irm_impl.h>
86 86
87 87 static int apix_probe();
88 88 static void apix_init();
89 89 static void apix_picinit(void);
90 90 static int apix_intr_enter(int, int *);
91 91 static void apix_intr_exit(int, int);
92 92 static void apix_setspl(int);
93 93 static int apix_disable_intr(processorid_t);
94 94 static void apix_enable_intr(processorid_t);
95 95 static int apix_get_clkvect(int);
96 96 static int apix_get_ipivect(int, int);
97 97 static void apix_post_cyclic_setup(void *);
98 98 static int apix_post_cpu_start();
99 99 static int apix_intr_ops(dev_info_t *, ddi_intr_handle_impl_t *,
100 100 psm_intr_op_t, int *);
101 101
102 102 /*
103 103 * Helper functions for apix_intr_ops()
104 104 */
105 105 static void apix_redistribute_compute(void);
106 106 static int apix_get_pending(apix_vector_t *);
107 107 static apix_vector_t *apix_get_req_vector(ddi_intr_handle_impl_t *, ushort_t);
108 108 static int apix_get_intr_info(ddi_intr_handle_impl_t *, apic_get_intr_t *);
109 109 static char *apix_get_apic_type(void);
110 110 static int apix_intx_get_pending(int);
111 111 static void apix_intx_set_mask(int irqno);
112 112 static void apix_intx_clear_mask(int irqno);
113 113 static int apix_intx_get_shared(int irqno);
114 114 static void apix_intx_set_shared(int irqno, int delta);
115 115 static apix_vector_t *apix_intx_xlate_vector(dev_info_t *, int,
116 116 struct intrspec *);
117 117 static int apix_intx_alloc_vector(dev_info_t *, int, struct intrspec *);
118 118
119 119 extern int apic_clkinit(int);
120 120
121 121 /* IRM initialization for APIX PSM module */
122 122 extern void apix_irm_init(void);
123 123
124 124 extern int irm_enable;
125 125
126 126 /*
127 127 * Local static data
128 128 */
129 129 static struct psm_ops apix_ops = {
130 130 apix_probe,
131 131
132 132 apix_init,
133 133 apix_picinit,
134 134 apix_intr_enter,
135 135 apix_intr_exit,
136 136 apix_setspl,
137 137 apix_addspl,
138 138 apix_delspl,
139 139 apix_disable_intr,
140 140 apix_enable_intr,
141 141 NULL, /* psm_softlvl_to_irq */
142 142 NULL, /* psm_set_softintr */
143 143
144 144 apic_set_idlecpu,
145 145 apic_unset_idlecpu,
146 146
147 147 apic_clkinit,
148 148 apix_get_clkvect,
149 149 NULL, /* psm_hrtimeinit */
150 150 apic_gethrtime,
151 151
152 152 apic_get_next_processorid,
153 153 apic_cpu_start,
154 154 apix_post_cpu_start,
155 155 apic_shutdown,
156 156 apix_get_ipivect,
157 157 apic_send_ipi,
158 158
159 159 NULL, /* psm_translate_irq */
160 160 NULL, /* psm_notify_error */
161 161 NULL, /* psm_notify_func */
162 162 apic_timer_reprogram,
163 163 apic_timer_enable,
164 164 apic_timer_disable,
165 165 apix_post_cyclic_setup,
166 166 apic_preshutdown,
167 167 apix_intr_ops, /* Advanced DDI Interrupt framework */
168 168 apic_state, /* save, restore apic state for S3 */
169 169 apic_cpu_ops, /* CPU control interface. */
170 170 };
171 171
172 172 struct psm_ops *psmops = &apix_ops;
173 173
174 174 static struct psm_info apix_psm_info = {
175 175 PSM_INFO_VER01_7, /* version */
176 176 PSM_OWN_EXCLUSIVE, /* ownership */
177 177 &apix_ops, /* operation */
178 178 APIX_NAME, /* machine name */
179 179 "apix MPv1.4 compatible",
180 180 };
181 181
182 182 static void *apix_hdlp;
183 183
184 184 static int apix_is_enabled = 0;
185 185
186 186 /*
187 187 * Flag to indicate if APIX is to be enabled only for platforms
188 188 * with specific hw feature(s).
189 189 */
190 190 int apix_hw_chk_enable = 1;
191 191
192 192 /*
193 193 * Hw features that are checked for enabling APIX support.
194 194 */
195 195 #define APIX_SUPPORT_X2APIC 0x00000001
196 196 uint_t apix_supported_hw = APIX_SUPPORT_X2APIC;
197 197
198 198 /*
199 199 * apix_lock is used for cpu selection and vector re-binding
200 200 */
201 201 lock_t apix_lock;
202 202 apix_impl_t *apixs[NCPU];
203 203 /*
204 204 * Mapping between device interrupt and the allocated vector. Indexed
205 205 * by major number.
206 206 */
207 207 apix_dev_vector_t **apix_dev_vector;
208 208 /*
209 209 * Mapping between device major number and cpu id. It gets used
210 210 * when interrupt binding policy round robin with affinity is
211 211 * applied. With that policy, devices with the same major number
212 212 * will be bound to the same CPU.
213 213 */
214 214 processorid_t *apix_major_to_cpu; /* major to cpu mapping */
215 215 kmutex_t apix_mutex; /* for apix_dev_vector & apix_major_to_cpu */
216 216
217 217 int apix_nipis = 16; /* Maximum number of IPIs */
218 218 /*
219 219 * Maximum number of vectors in a CPU that can be used for interrupt
220 220 * allocation (including IPIs and the reserved vectors).
221 221 */
222 222 int apix_cpu_nvectors = APIX_NVECTOR;
223 223
224 224 /* gcpu.h */
225 225
226 226 extern void apic_do_interrupt(struct regs *rp, trap_trace_rec_t *ttp);
227 227 extern void apic_change_eoi();
228 228
229 229 /*
230 230 * This is the loadable module wrapper
231 231 */
232 232
233 233 int
234 234 _init(void)
235 235 {
236 236 if (apic_coarse_hrtime)
237 237 apix_ops.psm_gethrtime = &apic_gettime;
238 238 return (psm_mod_init(&apix_hdlp, &apix_psm_info));
239 239 }
240 240
241 241 int
242 242 _fini(void)
243 243 {
244 244 return (psm_mod_fini(&apix_hdlp, &apix_psm_info));
245 245 }
246 246
247 247 int
248 248 _info(struct modinfo *modinfop)
249 249 {
250 250 return (psm_mod_info(&apix_hdlp, &apix_psm_info, modinfop));
251 251 }
252 252
253 253 static int
254 254 apix_probe()
255 255 {
256 256 int rval;
257 257
258 258 if (apix_enable == 0)
259 259 return (PSM_FAILURE);
260 260
261 261 /* check for hw features if specified */
262 262 if (apix_hw_chk_enable) {
263 263 /* check if x2APIC mode is supported */
264 264 if ((apix_supported_hw & APIX_SUPPORT_X2APIC) ==
265 265 APIX_SUPPORT_X2APIC) {
266 266 if (!((apic_local_mode() == LOCAL_X2APIC) ||
267 267 apic_detect_x2apic())) {
268 268 /* x2APIC mode is not supported in the hw */
269 269 apix_enable = 0;
270 270 }
271 271 }
272 272 if (apix_enable == 0)
273 273 return (PSM_FAILURE);
274 274 }
275 275
276 276 rval = apic_probe_common(apix_psm_info.p_mach_idstring);
277 277 if (rval == PSM_SUCCESS)
278 278 apix_is_enabled = 1;
279 279 else
280 280 apix_is_enabled = 0;
281 281 return (rval);
282 282 }
283 283
284 284 /*
285 285 * Initialize the data structures needed by pcplusmpx module.
286 286 * Specifically, the data structures used by addspl() and delspl()
287 287 * routines.
288 288 */
289 289 static void
290 290 apix_softinit()
291 291 {
292 292 int i, *iptr;
293 293 apix_impl_t *hdlp;
294 294 int nproc;
295 295
296 296 nproc = max(apic_nproc, apic_max_nproc);
297 297
298 298 hdlp = kmem_zalloc(nproc * sizeof (apix_impl_t), KM_SLEEP);
299 299 for (i = 0; i < nproc; i++) {
300 300 apixs[i] = &hdlp[i];
301 301 apixs[i]->x_cpuid = i;
302 302 LOCK_INIT_CLEAR(&apixs[i]->x_lock);
303 303 }
304 304
305 305 /* cpu 0 is always up (for now) */
306 306 apic_cpus[0].aci_status = APIC_CPU_ONLINE | APIC_CPU_INTR_ENABLE;
307 307
308 308 iptr = (int *)&apic_irq_table[0];
309 309 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
310 310 apic_level_intr[i] = 0;
311 311 *iptr++ = NULL;
312 312 }
313 313 mutex_init(&airq_mutex, NULL, MUTEX_DEFAULT, NULL);
314 314
315 315 apix_dev_vector = kmem_zalloc(sizeof (apix_dev_vector_t *) * devcnt,
316 316 KM_SLEEP);
317 317
318 318 if (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) {
319 319 apix_major_to_cpu = kmem_zalloc(sizeof (int) * devcnt,
320 320 KM_SLEEP);
321 321 for (i = 0; i < devcnt; i++)
322 322 apix_major_to_cpu[i] = IRQ_UNINIT;
323 323 }
324 324
325 325 mutex_init(&apix_mutex, NULL, MUTEX_DEFAULT, NULL);
326 326 }
327 327
328 328 static int
329 329 apix_get_pending_spl(void)
330 330 {
331 331 int cpuid = CPU->cpu_id;
332 332
333 333 return (bsrw_insn(apixs[cpuid]->x_intr_pending));
334 334 }
335 335
336 336 static uintptr_t
337 337 apix_get_intr_handler(int cpu, short vec)
338 338 {
339 339 apix_vector_t *apix_vector;
340 340
341 341 ASSERT(cpu < apic_nproc && vec < APIX_NVECTOR);
342 342 if (cpu >= apic_nproc)
343 343 return (NULL);
344 344
345 345 apix_vector = apixs[cpu]->x_vectbl[vec];
346 346
347 347 return ((uintptr_t)(apix_vector->v_autovect));
348 348 }
349 349
350 350 #if defined(__amd64)
351 351 static unsigned char dummy_cpu_pri[MAXIPL + 1] = {
352 352 0, 0, 0, 0, 0, 0, 0, 0,
353 353 0, 0, 0, 0, 0, 0, 0, 0, 0
354 354 };
355 355 #endif
356 356
357 357 static void
358 358 apix_init()
359 359 {
360 360 extern void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *);
361 361
362 362 APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_softinit\n"));
363 363
↓ open down ↓ |
363 lines elided |
↑ open up ↑ |
364 364 do_interrupt_common = apix_do_interrupt;
365 365 addintr = apix_add_avintr;
366 366 remintr = apix_rem_avintr;
367 367 get_pending_spl = apix_get_pending_spl;
368 368 get_intr_handler = apix_get_intr_handler;
369 369 psm_get_localapicid = apic_get_localapicid;
370 370 psm_get_ioapicid = apic_get_ioapicid;
371 371
372 372 apix_softinit();
373 373 #if defined(__amd64)
374 - /*
375 - * Make cpu-specific interrupt info point to cr8pri vector
376 - */
377 374 CPU->cpu_pri_data = dummy_cpu_pri;
378 375 #else
379 376 if (cpuid_have_cr8access(CPU))
380 377 apic_have_32bit_cr8 = 1;
381 378 #endif /* __amd64 */
382 379
383 380 /*
384 381 * Initialize IRM pool parameters
385 382 */
386 383 if (irm_enable) {
387 384 int i;
388 385 int lowest_irq;
389 386 int highest_irq;
390 387
391 388 /* number of CPUs present */
392 389 apix_irminfo.apix_ncpus = apic_nproc;
393 390 /* total number of entries in all of the IOAPICs present */
394 391 lowest_irq = apic_io_vectbase[0];
395 392 highest_irq = apic_io_vectend[0];
396 393 for (i = 1; i < apic_io_max; i++) {
397 394 if (apic_io_vectbase[i] < lowest_irq)
398 395 lowest_irq = apic_io_vectbase[i];
399 396 if (apic_io_vectend[i] > highest_irq)
400 397 highest_irq = apic_io_vectend[i];
401 398 }
402 399 apix_irminfo.apix_ioapic_max_vectors =
403 400 highest_irq - lowest_irq + 1;
404 401 /*
405 402 * Number of available per-CPU vectors excluding
406 403 * reserved vectors for Dtrace, int80, system-call,
407 404 * fast-trap, etc.
408 405 */
409 406 apix_irminfo.apix_per_cpu_vectors = APIX_NAVINTR -
410 407 APIX_SW_RESERVED_VECTORS;
411 408
412 409 /* Number of vectors (pre) allocated (SCI and HPET) */
413 410 apix_irminfo.apix_vectors_allocated = 0;
414 411 if (apic_hpet_vect != -1)
415 412 apix_irminfo.apix_vectors_allocated++;
416 413 if (apic_sci_vect != -1)
417 414 apix_irminfo.apix_vectors_allocated++;
418 415 }
419 416 }
420 417
421 418 static void
422 419 apix_init_intr()
423 420 {
424 421 processorid_t cpun = psm_get_cpu_id();
425 422 uint_t nlvt;
426 423 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
427 424 extern void cmi_cmci_trap(void);
428 425
429 426 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
430 427
431 428 if (apic_mode == LOCAL_APIC) {
432 429 /*
433 430 * We are running APIC in MMIO mode.
434 431 */
435 432 if (apic_flat_model) {
436 433 apic_reg_ops->apic_write(APIC_FORMAT_REG,
437 434 APIC_FLAT_MODEL);
438 435 } else {
439 436 apic_reg_ops->apic_write(APIC_FORMAT_REG,
440 437 APIC_CLUSTER_MODEL);
441 438 }
442 439
443 440 apic_reg_ops->apic_write(APIC_DEST_REG,
444 441 AV_HIGH_ORDER >> cpun);
445 442 }
446 443
447 444 if (apic_directed_EOI_supported()) {
448 445 /*
449 446 * Setting the 12th bit in the Spurious Interrupt Vector
450 447 * Register suppresses broadcast EOIs generated by the local
451 448 * APIC. The suppression of broadcast EOIs happens only when
452 449 * interrupts are level-triggered.
453 450 */
454 451 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
455 452 }
456 453
457 454 /* need to enable APIC before unmasking NMI */
458 455 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
459 456
460 457 /*
461 458 * Presence of an invalid vector with delivery mode AV_FIXED can
462 459 * cause an error interrupt, even if the entry is masked...so
463 460 * write a valid vector to LVT entries along with the mask bit
464 461 */
465 462
466 463 /* All APICs have timer and LINT0/1 */
467 464 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
468 465 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
469 466 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
470 467
471 468 /*
472 469 * On integrated APICs, the number of LVT entries is
473 470 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
474 471 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
475 472 */
476 473
477 474 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
478 475 nlvt = 3;
479 476 } else {
480 477 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
481 478 0xFF) + 1;
482 479 }
483 480
484 481 if (nlvt >= 5) {
485 482 /* Enable performance counter overflow interrupt */
486 483
487 484 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
488 485 apic_enable_cpcovf_intr = 0;
489 486 if (apic_enable_cpcovf_intr) {
490 487 if (apic_cpcovf_vect == 0) {
491 488 int ipl = APIC_PCINT_IPL;
492 489
493 490 apic_cpcovf_vect = apix_get_ipivect(ipl, -1);
494 491 ASSERT(apic_cpcovf_vect);
495 492
496 493 (void) add_avintr(NULL, ipl,
497 494 (avfunc)kcpc_hw_overflow_intr,
498 495 "apic pcint", apic_cpcovf_vect,
499 496 NULL, NULL, NULL, NULL);
500 497 kcpc_hw_overflow_intr_installed = 1;
501 498 kcpc_hw_enable_cpc_intr =
502 499 apic_cpcovf_mask_clear;
503 500 }
504 501 apic_reg_ops->apic_write(APIC_PCINT_VECT,
505 502 apic_cpcovf_vect);
506 503 }
507 504 }
508 505
509 506 if (nlvt >= 6) {
510 507 /* Only mask TM intr if the BIOS apparently doesn't use it */
511 508
512 509 uint32_t lvtval;
513 510
514 511 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
515 512 if (((lvtval & AV_MASK) == AV_MASK) ||
516 513 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
517 514 apic_reg_ops->apic_write(APIC_THERM_VECT,
518 515 AV_MASK|APIC_RESV_IRQ);
519 516 }
520 517 }
521 518
522 519 /* Enable error interrupt */
523 520
524 521 if (nlvt >= 4 && apic_enable_error_intr) {
525 522 if (apic_errvect == 0) {
526 523 int ipl = 0xf; /* get highest priority intr */
527 524 apic_errvect = apix_get_ipivect(ipl, -1);
528 525 ASSERT(apic_errvect);
529 526 /*
530 527 * Not PSMI compliant, but we are going to merge
531 528 * with ON anyway
532 529 */
533 530 (void) add_avintr(NULL, ipl,
534 531 (avfunc)apic_error_intr, "apic error intr",
535 532 apic_errvect, NULL, NULL, NULL, NULL);
536 533 }
537 534 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
538 535 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
539 536 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
540 537 }
541 538
542 539 /* Enable CMCI interrupt */
543 540 if (cmi_enable_cmci) {
544 541 mutex_enter(&cmci_cpu_setup_lock);
545 542 if (cmci_cpu_setup_registered == 0) {
546 543 mutex_enter(&cpu_lock);
547 544 register_cpu_setup_func(cmci_cpu_setup, NULL);
548 545 mutex_exit(&cpu_lock);
549 546 cmci_cpu_setup_registered = 1;
550 547 }
551 548 mutex_exit(&cmci_cpu_setup_lock);
552 549
553 550 if (apic_cmci_vect == 0) {
554 551 int ipl = 0x2;
555 552 apic_cmci_vect = apix_get_ipivect(ipl, -1);
556 553 ASSERT(apic_cmci_vect);
557 554
558 555 (void) add_avintr(NULL, ipl,
559 556 (avfunc)cmi_cmci_trap, "apic cmci intr",
560 557 apic_cmci_vect, NULL, NULL, NULL, NULL);
561 558 }
562 559 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect);
563 560 }
564 561
565 562 apic_reg_ops->apic_write_task_reg(0);
566 563 }
567 564
568 565 static void
569 566 apix_picinit(void)
570 567 {
571 568 int i, j;
572 569 uint_t isr;
573 570
574 571 APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_picinit\n"));
575 572
576 573 /*
577 574 * initialize interrupt remapping before apic
578 575 * hardware initialization
579 576 */
580 577 apic_intrmap_init(apic_mode);
581 578 if (apic_vt_ops == psm_vt_ops)
582 579 apix_mul_ioapic_method = APIC_MUL_IOAPIC_IIR;
583 580
584 581 /*
585 582 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
586 583 * bit on without clearing it with EOI. Since softint
587 584 * uses vector 0x20 to interrupt itself, so softint will
588 585 * not work on this machine. In order to fix this problem
589 586 * a check is made to verify all the isr bits are clear.
590 587 * If not, EOIs are issued to clear the bits.
591 588 */
592 589 for (i = 7; i >= 1; i--) {
593 590 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
594 591 if (isr != 0)
595 592 for (j = 0; ((j < 32) && (isr != 0)); j++)
596 593 if (isr & (1 << j)) {
597 594 apic_reg_ops->apic_write(
598 595 APIC_EOI_REG, 0);
599 596 isr &= ~(1 << j);
600 597 apic_error |= APIC_ERR_BOOT_EOI;
601 598 }
602 599 }
603 600
604 601 /* set a flag so we know we have run apic_picinit() */
605 602 apic_picinit_called = 1;
606 603 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
607 604 LOCK_INIT_CLEAR(&apic_ioapic_lock);
608 605 LOCK_INIT_CLEAR(&apic_error_lock);
609 606 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
610 607
611 608 picsetup(); /* initialise the 8259 */
612 609
613 610 /* add nmi handler - least priority nmi handler */
614 611 LOCK_INIT_CLEAR(&apic_nmi_lock);
615 612
616 613 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
617 614 "apix NMI handler", (caddr_t)NULL))
618 615 cmn_err(CE_WARN, "apix: Unable to add nmi handler");
619 616
620 617 apix_init_intr();
621 618
622 619 /* enable apic mode if imcr present */
623 620 if (apic_imcrp) {
624 621 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
625 622 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
626 623 }
627 624
628 625 ioapix_init_intr(IOAPIC_MASK);
629 626
630 627 /* setup global IRM pool if applicable */
631 628 if (irm_enable)
632 629 apix_irm_init();
633 630 }
634 631
635 632 static __inline__ void
636 633 apix_send_eoi(void)
637 634 {
638 635 if (apic_mode == LOCAL_APIC)
639 636 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
640 637 else
641 638 X2APIC_WRITE(APIC_EOI_REG, 0);
642 639 }
643 640
644 641 /*
645 642 * platform_intr_enter
646 643 *
647 644 * Called at the beginning of the interrupt service routine, but unlike
648 645 * pcplusmp, does not mask interrupts. An EOI is given to the interrupt
649 646 * controller to enable other HW interrupts but interrupts are still
650 647 * masked by the IF flag.
651 648 *
652 649 * Return -1 for spurious interrupts
653 650 *
654 651 */
655 652 static int
656 653 apix_intr_enter(int ipl, int *vectorp)
657 654 {
658 655 struct cpu *cpu = CPU;
659 656 uint32_t cpuid = CPU->cpu_id;
660 657 apic_cpus_info_t *cpu_infop;
661 658 uchar_t vector;
662 659 apix_vector_t *vecp;
663 660 int nipl = -1;
664 661
665 662 /*
666 663 * The real vector delivered is (*vectorp + 0x20), but our caller
667 664 * subtracts 0x20 from the vector before passing it to us.
668 665 * (That's why APIC_BASE_VECT is 0x20.)
669 666 */
670 667 vector = *vectorp = (uchar_t)*vectorp + APIC_BASE_VECT;
671 668
672 669 cpu_infop = &apic_cpus[cpuid];
673 670 if (vector == APIC_SPUR_INTR) {
674 671 cpu_infop->aci_spur_cnt++;
675 672 return (APIC_INT_SPURIOUS);
676 673 }
677 674
678 675 vecp = xv_vector(cpuid, vector);
679 676 if (vecp == NULL) {
680 677 if (APIX_IS_FAKE_INTR(vector))
681 678 nipl = apix_rebindinfo.i_pri;
682 679 apix_send_eoi();
683 680 return (nipl);
684 681 }
685 682 nipl = vecp->v_pri;
686 683
687 684 /* if interrupted by the clock, increment apic_nsec_since_boot */
688 685 if (vector == (apic_clkvect + APIC_BASE_VECT)) {
689 686 if (!apic_oneshot) {
690 687 /* NOTE: this is not MT aware */
691 688 apic_hrtime_stamp++;
692 689 apic_nsec_since_boot += apic_nsec_per_intr;
693 690 apic_hrtime_stamp++;
694 691 last_count_read = apic_hertz_count;
695 692 apix_redistribute_compute();
696 693 }
697 694
698 695 apix_send_eoi();
699 696
700 697 return (nipl);
701 698 }
702 699
703 700 ASSERT(vecp->v_state != APIX_STATE_OBSOLETED);
704 701
705 702 /* pre-EOI handling for level-triggered interrupts */
706 703 if (!APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method) &&
707 704 (vecp->v_type & APIX_TYPE_FIXED) && apic_level_intr[vecp->v_inum])
708 705 apix_level_intr_pre_eoi(vecp->v_inum);
709 706
710 707 /* send back EOI */
711 708 apix_send_eoi();
712 709
713 710 cpu_infop->aci_current[nipl] = vector;
714 711 if ((nipl > ipl) && (nipl > cpu->cpu_base_spl)) {
715 712 cpu_infop->aci_curipl = (uchar_t)nipl;
716 713 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
717 714 }
718 715
719 716 #ifdef DEBUG
720 717 if (vector >= APIX_IPI_MIN)
721 718 return (nipl); /* skip IPI */
722 719
723 720 APIC_DEBUG_BUF_PUT(vector);
724 721 APIC_DEBUG_BUF_PUT(vecp->v_inum);
725 722 APIC_DEBUG_BUF_PUT(nipl);
726 723 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
727 724 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
728 725 drv_usecwait(apic_stretch_interrupts);
729 726 #endif /* DEBUG */
730 727
731 728 return (nipl);
732 729 }
733 730
734 731 /*
735 732 * Any changes made to this function must also change X2APIC
736 733 * version of intr_exit.
737 734 */
738 735 static void
739 736 apix_intr_exit(int prev_ipl, int arg2)
740 737 {
741 738 int cpuid = psm_get_cpu_id();
742 739 apic_cpus_info_t *cpu_infop = &apic_cpus[cpuid];
743 740 apix_impl_t *apixp = apixs[cpuid];
744 741
745 742 UNREFERENCED_1PARAMETER(arg2);
746 743
747 744 cpu_infop->aci_curipl = (uchar_t)prev_ipl;
748 745 /* ISR above current pri could not be in progress */
749 746 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1;
750 747
751 748 if (apixp->x_obsoletes != NULL) {
752 749 if (APIX_CPU_LOCK_HELD(cpuid))
753 750 return;
754 751
755 752 APIX_ENTER_CPU_LOCK(cpuid);
756 753 (void) apix_obsolete_vector(apixp->x_obsoletes);
757 754 APIX_LEAVE_CPU_LOCK(cpuid);
758 755 }
759 756 }
760 757
761 758 /*
762 759 * The pcplusmp setspl code uses the TPR to mask all interrupts at or below the
763 760 * given ipl, but apix never uses the TPR and we never mask a subset of the
764 761 * interrupts. They are either all blocked by the IF flag or all can come in.
765 762 *
766 763 * For setspl, we mask all interrupts for XC_HI_PIL (15), otherwise, interrupts
767 764 * can come in if currently enabled by the IF flag. This table shows the state
768 765 * of the IF flag when we leave this function.
769 766 *
770 767 * curr IF | ipl == 15 ipl != 15
771 768 * --------+---------------------------
772 769 * 0 | 0 0
773 770 * 1 | 0 1
774 771 */
775 772 static void
776 773 apix_setspl(int ipl)
777 774 {
778 775 /*
779 776 * Interrupts at ipl above this cannot be in progress, so the following
780 777 * mask is ok.
781 778 */
782 779 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
783 780
784 781 if (ipl == XC_HI_PIL)
785 782 cli();
786 783 }
787 784
788 785 int
789 786 apix_addspl(int virtvec, int ipl, int min_ipl, int max_ipl)
790 787 {
791 788 uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec);
792 789 uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec);
793 790 apix_vector_t *vecp = xv_vector(cpuid, vector);
794 791
795 792 UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl);
796 793 ASSERT(vecp != NULL && LOCK_HELD(&apix_lock));
797 794
798 795 if (vecp->v_type == APIX_TYPE_FIXED)
799 796 apix_intx_set_shared(vecp->v_inum, 1);
800 797
801 798 /* There are more interrupts, so it's already been enabled */
802 799 if (vecp->v_share > 1)
803 800 return (PSM_SUCCESS);
804 801
805 802 /* return if it is not hardware interrupt */
806 803 if (vecp->v_type == APIX_TYPE_IPI)
807 804 return (PSM_SUCCESS);
808 805
809 806 /*
810 807 * if apix_picinit() has not been called yet, just return.
811 808 * At the end of apic_picinit(), we will call setup_io_intr().
812 809 */
813 810 if (!apic_picinit_called)
814 811 return (PSM_SUCCESS);
815 812
816 813 (void) apix_setup_io_intr(vecp);
817 814
818 815 return (PSM_SUCCESS);
819 816 }
820 817
821 818 int
822 819 apix_delspl(int virtvec, int ipl, int min_ipl, int max_ipl)
823 820 {
824 821 uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec);
825 822 uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec);
826 823 apix_vector_t *vecp = xv_vector(cpuid, vector);
827 824
828 825 UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl);
829 826 ASSERT(vecp != NULL && LOCK_HELD(&apix_lock));
830 827
831 828 if (vecp->v_type == APIX_TYPE_FIXED)
832 829 apix_intx_set_shared(vecp->v_inum, -1);
833 830
834 831 /* There are more interrupts */
835 832 if (vecp->v_share > 1)
836 833 return (PSM_SUCCESS);
837 834
838 835 /* return if it is not hardware interrupt */
839 836 if (vecp->v_type == APIX_TYPE_IPI)
840 837 return (PSM_SUCCESS);
841 838
842 839 if (!apic_picinit_called) {
843 840 cmn_err(CE_WARN, "apix: delete 0x%x before apic init",
844 841 virtvec);
845 842 return (PSM_SUCCESS);
846 843 }
847 844
848 845 apix_disable_vector(vecp);
849 846
850 847 return (PSM_SUCCESS);
851 848 }
852 849
853 850 /*
854 851 * Try and disable all interrupts. We just assign interrupts to other
855 852 * processors based on policy. If any were bound by user request, we
856 853 * let them continue and return failure. We do not bother to check
857 854 * for cache affinity while rebinding.
858 855 */
859 856 static int
860 857 apix_disable_intr(processorid_t cpun)
861 858 {
862 859 apix_impl_t *apixp = apixs[cpun];
863 860 apix_vector_t *vecp, *newp;
864 861 int bindcpu, i, hardbound = 0, errbound = 0, ret, loop, type;
865 862
866 863 lock_set(&apix_lock);
867 864
868 865 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
869 866 apic_cpus[cpun].aci_curipl = 0;
870 867
871 868 /* if this is for SUSPEND operation, skip rebinding */
872 869 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) {
873 870 for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
874 871 vecp = apixp->x_vectbl[i];
875 872 if (!IS_VECT_ENABLED(vecp))
876 873 continue;
877 874
878 875 apix_disable_vector(vecp);
879 876 }
880 877 lock_clear(&apix_lock);
881 878 return (PSM_SUCCESS);
882 879 }
883 880
884 881 for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
885 882 vecp = apixp->x_vectbl[i];
886 883 if (!IS_VECT_ENABLED(vecp))
887 884 continue;
888 885
889 886 if (vecp->v_flags & APIX_VECT_USER_BOUND) {
890 887 hardbound++;
891 888 continue;
892 889 }
893 890 type = vecp->v_type;
894 891
895 892 /*
896 893 * If there are bound interrupts on this cpu, then
897 894 * rebind them to other processors.
898 895 */
899 896 loop = 0;
900 897 do {
901 898 bindcpu = apic_find_cpu(APIC_CPU_INTR_ENABLE);
902 899
903 900 if (type != APIX_TYPE_MSI)
904 901 newp = apix_set_cpu(vecp, bindcpu, &ret);
905 902 else
906 903 newp = apix_grp_set_cpu(vecp, bindcpu, &ret);
907 904 } while ((newp == NULL) && (loop++ < apic_nproc));
908 905
909 906 if (loop >= apic_nproc) {
910 907 errbound++;
911 908 cmn_err(CE_WARN, "apix: failed to rebind vector %x/%x",
912 909 vecp->v_cpuid, vecp->v_vector);
913 910 }
914 911 }
915 912
916 913 lock_clear(&apix_lock);
917 914
918 915 if (hardbound || errbound) {
919 916 cmn_err(CE_WARN, "Could not disable interrupts on %d"
920 917 "due to user bound interrupts or failed operation",
921 918 cpun);
922 919 return (PSM_FAILURE);
923 920 }
924 921
925 922 return (PSM_SUCCESS);
926 923 }
927 924
928 925 /*
929 926 * Bind interrupts to specified CPU
930 927 */
931 928 static void
932 929 apix_enable_intr(processorid_t cpun)
933 930 {
934 931 apix_vector_t *vecp;
935 932 int i, ret;
936 933 processorid_t n;
937 934
938 935 lock_set(&apix_lock);
939 936
940 937 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
941 938
942 939 /* interrupt enabling for system resume */
943 940 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) {
944 941 for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
945 942 vecp = xv_vector(cpun, i);
946 943 if (!IS_VECT_ENABLED(vecp))
947 944 continue;
948 945
949 946 apix_enable_vector(vecp);
950 947 }
951 948 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
952 949 }
953 950
954 951 for (n = 0; n < apic_nproc; n++) {
955 952 if (!apic_cpu_in_range(n) || n == cpun ||
956 953 (apic_cpus[n].aci_status & APIC_CPU_INTR_ENABLE) == 0)
957 954 continue;
958 955
959 956 for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
960 957 vecp = xv_vector(n, i);
961 958 if (!IS_VECT_ENABLED(vecp) ||
962 959 vecp->v_bound_cpuid != cpun)
963 960 continue;
964 961
965 962 if (vecp->v_type != APIX_TYPE_MSI)
966 963 (void) apix_set_cpu(vecp, cpun, &ret);
967 964 else
968 965 (void) apix_grp_set_cpu(vecp, cpun, &ret);
969 966 }
970 967 }
971 968
972 969 lock_clear(&apix_lock);
973 970 }
974 971
975 972 /*
976 973 * Allocate vector for IPI
977 974 * type == -1 indicates it is an internal request. Do not change
978 975 * resv_vector for these requests.
979 976 */
980 977 static int
981 978 apix_get_ipivect(int ipl, int type)
982 979 {
983 980 uchar_t vector;
984 981
985 982 if ((vector = apix_alloc_ipi(ipl)) > 0) {
986 983 if (type != -1)
987 984 apic_resv_vector[ipl] = vector;
988 985 return (vector);
989 986 }
990 987 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
991 988 return (-1); /* shouldn't happen */
992 989 }
993 990
994 991 static int
995 992 apix_get_clkvect(int ipl)
996 993 {
997 994 int vector;
998 995
999 996 if ((vector = apix_get_ipivect(ipl, -1)) == -1)
1000 997 return (-1);
1001 998
1002 999 apic_clkvect = vector - APIC_BASE_VECT;
1003 1000 APIC_VERBOSE(IPI, (CE_CONT, "apix: clock vector = %x\n",
1004 1001 apic_clkvect));
1005 1002 return (vector);
1006 1003 }
1007 1004
1008 1005 static int
1009 1006 apix_post_cpu_start()
1010 1007 {
1011 1008 int cpun;
1012 1009 static int cpus_started = 1;
1013 1010
1014 1011 /* We know this CPU + BSP started successfully. */
1015 1012 cpus_started++;
1016 1013
1017 1014 /*
1018 1015 * On BSP we would have enabled X2APIC, if supported by processor,
1019 1016 * in acpi_probe(), but on AP we do it here.
1020 1017 *
1021 1018 * We enable X2APIC mode only if BSP is running in X2APIC & the
1022 1019 * local APIC mode of the current CPU is MMIO (xAPIC).
1023 1020 */
1024 1021 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
1025 1022 apic_local_mode() == LOCAL_APIC) {
1026 1023 apic_enable_x2apic();
1027 1024 }
1028 1025
1029 1026 /*
1030 1027 * Switch back to x2apic IPI sending method for performance when target
1031 1028 * CPU has entered x2apic mode.
1032 1029 */
1033 1030 if (apic_mode == LOCAL_X2APIC) {
1034 1031 apic_switch_ipi_callback(B_FALSE);
1035 1032 }
1036 1033
1037 1034 splx(ipltospl(LOCK_LEVEL));
1038 1035 apix_init_intr();
1039 1036
1040 1037 /*
1041 1038 * since some systems don't enable the internal cache on the non-boot
1042 1039 * cpus, so we have to enable them here
1043 1040 */
1044 1041 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
1045 1042
1046 1043 #ifdef DEBUG
1047 1044 APIC_AV_PENDING_SET();
1048 1045 #else
1049 1046 if (apic_mode == LOCAL_APIC)
1050 1047 APIC_AV_PENDING_SET();
1051 1048 #endif /* DEBUG */
1052 1049
1053 1050 /*
1054 1051 * We may be booting, or resuming from suspend; aci_status will
1055 1052 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
1056 1053 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
1057 1054 */
1058 1055 cpun = psm_get_cpu_id();
1059 1056 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
1060 1057
1061 1058 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
1062 1059
1063 1060 return (PSM_SUCCESS);
1064 1061 }
1065 1062
1066 1063 /*
1067 1064 * If this module needs a periodic handler for the interrupt distribution, it
1068 1065 * can be added here. The argument to the periodic handler is not currently
1069 1066 * used, but is reserved for future.
1070 1067 */
1071 1068 static void
1072 1069 apix_post_cyclic_setup(void *arg)
1073 1070 {
1074 1071 UNREFERENCED_1PARAMETER(arg);
1075 1072
1076 1073 cyc_handler_t cyh;
1077 1074 cyc_time_t cyt;
1078 1075
1079 1076 /* cpu_lock is held */
1080 1077 /* set up a periodic handler for intr redistribution */
1081 1078
1082 1079 /*
1083 1080 * In peridoc mode intr redistribution processing is done in
1084 1081 * apic_intr_enter during clk intr processing
1085 1082 */
1086 1083 if (!apic_oneshot)
1087 1084 return;
1088 1085
1089 1086 /*
1090 1087 * Register a periodical handler for the redistribution processing.
1091 1088 * Though we would generally prefer to use the DDI interface for
1092 1089 * periodic handler invocation, ddi_periodic_add(9F), we are
1093 1090 * unfortunately already holding cpu_lock, which ddi_periodic_add will
1094 1091 * attempt to take for us. Thus, we add our own cyclic directly:
1095 1092 */
1096 1093 cyh.cyh_func = (void (*)(void *))apix_redistribute_compute;
1097 1094 cyh.cyh_arg = NULL;
1098 1095 cyh.cyh_level = CY_LOW_LEVEL;
1099 1096
1100 1097 cyt.cyt_when = 0;
1101 1098 cyt.cyt_interval = apic_redistribute_sample_interval;
1102 1099
1103 1100 apic_cyclic_id = cyclic_add(&cyh, &cyt);
1104 1101 }
1105 1102
1106 1103 /*
1107 1104 * Called the first time we enable x2apic mode on this cpu.
1108 1105 * Update some of the function pointers to use x2apic routines.
1109 1106 */
1110 1107 void
1111 1108 x2apic_update_psm()
1112 1109 {
1113 1110 struct psm_ops *pops = &apix_ops;
1114 1111
1115 1112 ASSERT(pops != NULL);
1116 1113
1117 1114 /*
1118 1115 * The pcplusmp module's version of x2apic_update_psm makes additional
1119 1116 * changes that we do not have to make here. It needs to make those
1120 1117 * changes because pcplusmp relies on the TPR register and the means of
1121 1118 * addressing that changes when using the local apic versus the x2apic.
1122 1119 * It's also worth noting that the apix driver specific function end up
1123 1120 * being apix_foo as opposed to apic_foo and x2apic_foo.
1124 1121 */
1125 1122 pops->psm_send_ipi = x2apic_send_ipi;
1126 1123
1127 1124 send_dirintf = pops->psm_send_ipi;
1128 1125
1129 1126 apic_mode = LOCAL_X2APIC;
1130 1127 apic_change_ops();
1131 1128 }
1132 1129
1133 1130 /*
1134 1131 * This function provides external interface to the nexus for all
1135 1132 * functionalities related to the new DDI interrupt framework.
1136 1133 *
1137 1134 * Input:
1138 1135 * dip - pointer to the dev_info structure of the requested device
1139 1136 * hdlp - pointer to the internal interrupt handle structure for the
1140 1137 * requested interrupt
1141 1138 * intr_op - opcode for this call
1142 1139 * result - pointer to the integer that will hold the result to be
1143 1140 * passed back if return value is PSM_SUCCESS
1144 1141 *
1145 1142 * Output:
1146 1143 * return value is either PSM_SUCCESS or PSM_FAILURE
1147 1144 */
1148 1145 static int
1149 1146 apix_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp,
1150 1147 psm_intr_op_t intr_op, int *result)
1151 1148 {
1152 1149 int cap;
1153 1150 apix_vector_t *vecp, *newvecp;
1154 1151 struct intrspec *ispec, intr_spec;
1155 1152 processorid_t target;
1156 1153
1157 1154 ispec = &intr_spec;
1158 1155 ispec->intrspec_pri = hdlp->ih_pri;
1159 1156 ispec->intrspec_vec = hdlp->ih_inum;
1160 1157 ispec->intrspec_func = hdlp->ih_cb_func;
1161 1158
1162 1159 switch (intr_op) {
1163 1160 case PSM_INTR_OP_ALLOC_VECTORS:
1164 1161 switch (hdlp->ih_type) {
1165 1162 case DDI_INTR_TYPE_MSI:
1166 1163 /* allocate MSI vectors */
1167 1164 *result = apix_alloc_msi(dip, hdlp->ih_inum,
1168 1165 hdlp->ih_scratch1,
1169 1166 (int)(uintptr_t)hdlp->ih_scratch2);
1170 1167 break;
1171 1168 case DDI_INTR_TYPE_MSIX:
1172 1169 /* allocate MSI-X vectors */
1173 1170 *result = apix_alloc_msix(dip, hdlp->ih_inum,
1174 1171 hdlp->ih_scratch1,
1175 1172 (int)(uintptr_t)hdlp->ih_scratch2);
1176 1173 break;
1177 1174 case DDI_INTR_TYPE_FIXED:
1178 1175 /* allocate or share vector for fixed */
1179 1176 if ((ihdl_plat_t *)hdlp->ih_private == NULL) {
1180 1177 return (PSM_FAILURE);
1181 1178 }
1182 1179 ispec = ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp;
1183 1180 *result = apix_intx_alloc_vector(dip, hdlp->ih_inum,
1184 1181 ispec);
1185 1182 break;
1186 1183 default:
1187 1184 return (PSM_FAILURE);
1188 1185 }
1189 1186 break;
1190 1187 case PSM_INTR_OP_FREE_VECTORS:
1191 1188 apix_free_vectors(dip, hdlp->ih_inum, hdlp->ih_scratch1,
1192 1189 hdlp->ih_type);
1193 1190 break;
1194 1191 case PSM_INTR_OP_XLATE_VECTOR:
1195 1192 /*
1196 1193 * Vectors are allocated by ALLOC and freed by FREE.
1197 1194 * XLATE finds and returns APIX_VIRTVEC_VECTOR(cpu, vector).
1198 1195 */
1199 1196 *result = APIX_INVALID_VECT;
1200 1197 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1201 1198 if (vecp != NULL) {
1202 1199 *result = APIX_VIRTVECTOR(vecp->v_cpuid,
1203 1200 vecp->v_vector);
1204 1201 break;
1205 1202 }
1206 1203
1207 1204 /*
1208 1205 * No vector to device mapping exists. If this is FIXED type
1209 1206 * then check if this IRQ is already mapped for another device
1210 1207 * then return the vector number for it (i.e. shared IRQ case).
1211 1208 * Otherwise, return PSM_FAILURE.
1212 1209 */
1213 1210 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) {
1214 1211 vecp = apix_intx_xlate_vector(dip, hdlp->ih_inum,
1215 1212 ispec);
1216 1213 *result = (vecp == NULL) ? APIX_INVALID_VECT :
1217 1214 APIX_VIRTVECTOR(vecp->v_cpuid, vecp->v_vector);
1218 1215 }
1219 1216 if (*result == APIX_INVALID_VECT)
1220 1217 return (PSM_FAILURE);
1221 1218 break;
1222 1219 case PSM_INTR_OP_GET_PENDING:
1223 1220 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1224 1221 if (vecp == NULL)
1225 1222 return (PSM_FAILURE);
1226 1223
1227 1224 *result = apix_get_pending(vecp);
1228 1225 break;
1229 1226 case PSM_INTR_OP_CLEAR_MASK:
1230 1227 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1231 1228 return (PSM_FAILURE);
1232 1229
1233 1230 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1234 1231 if (vecp == NULL)
1235 1232 return (PSM_FAILURE);
1236 1233
1237 1234 apix_intx_clear_mask(vecp->v_inum);
1238 1235 break;
1239 1236 case PSM_INTR_OP_SET_MASK:
1240 1237 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1241 1238 return (PSM_FAILURE);
1242 1239
1243 1240 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1244 1241 if (vecp == NULL)
1245 1242 return (PSM_FAILURE);
1246 1243
1247 1244 apix_intx_set_mask(vecp->v_inum);
1248 1245 break;
1249 1246 case PSM_INTR_OP_GET_SHARED:
1250 1247 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1251 1248 return (PSM_FAILURE);
1252 1249
1253 1250 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1254 1251 if (vecp == NULL)
1255 1252 return (PSM_FAILURE);
1256 1253
1257 1254 *result = apix_intx_get_shared(vecp->v_inum);
1258 1255 break;
1259 1256 case PSM_INTR_OP_SET_PRI:
1260 1257 /*
1261 1258 * Called prior to adding the interrupt handler or when
1262 1259 * an interrupt handler is unassigned.
1263 1260 */
1264 1261 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
1265 1262 return (PSM_SUCCESS);
1266 1263
1267 1264 if (apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type) == NULL)
1268 1265 return (PSM_FAILURE);
1269 1266
1270 1267 break;
1271 1268 case PSM_INTR_OP_SET_CPU:
1272 1269 case PSM_INTR_OP_GRP_SET_CPU:
1273 1270 /*
1274 1271 * The interrupt handle given here has been allocated
1275 1272 * specifically for this command, and ih_private carries
1276 1273 * a CPU value.
1277 1274 */
1278 1275 *result = EINVAL;
1279 1276 target = (int)(intptr_t)hdlp->ih_private;
1280 1277 if (!apic_cpu_in_range(target)) {
1281 1278 DDI_INTR_IMPLDBG((CE_WARN,
1282 1279 "[grp_]set_cpu: cpu out of range: %d\n", target));
1283 1280 return (PSM_FAILURE);
1284 1281 }
1285 1282
1286 1283 lock_set(&apix_lock);
1287 1284
1288 1285 vecp = apix_get_req_vector(hdlp, hdlp->ih_flags);
1289 1286 if (!IS_VECT_ENABLED(vecp)) {
1290 1287 DDI_INTR_IMPLDBG((CE_WARN,
1291 1288 "[grp]_set_cpu: invalid vector 0x%x\n",
1292 1289 hdlp->ih_vector));
1293 1290 lock_clear(&apix_lock);
1294 1291 return (PSM_FAILURE);
1295 1292 }
1296 1293
1297 1294 *result = 0;
1298 1295
1299 1296 if (intr_op == PSM_INTR_OP_SET_CPU)
1300 1297 newvecp = apix_set_cpu(vecp, target, result);
1301 1298 else
1302 1299 newvecp = apix_grp_set_cpu(vecp, target, result);
1303 1300
1304 1301 lock_clear(&apix_lock);
1305 1302
1306 1303 if (newvecp == NULL) {
1307 1304 *result = EIO;
1308 1305 return (PSM_FAILURE);
1309 1306 }
1310 1307 newvecp->v_bound_cpuid = target;
1311 1308 hdlp->ih_vector = APIX_VIRTVECTOR(newvecp->v_cpuid,
1312 1309 newvecp->v_vector);
1313 1310 break;
1314 1311
1315 1312 case PSM_INTR_OP_GET_INTR:
1316 1313 /*
1317 1314 * The interrupt handle given here has been allocated
1318 1315 * specifically for this command, and ih_private carries
1319 1316 * a pointer to a apic_get_intr_t.
1320 1317 */
1321 1318 if (apix_get_intr_info(hdlp, hdlp->ih_private) != PSM_SUCCESS)
1322 1319 return (PSM_FAILURE);
1323 1320 break;
1324 1321
1325 1322 case PSM_INTR_OP_CHECK_MSI:
1326 1323 /*
1327 1324 * Check MSI/X is supported or not at APIC level and
1328 1325 * masked off the MSI/X bits in hdlp->ih_type if not
1329 1326 * supported before return. If MSI/X is supported,
1330 1327 * leave the ih_type unchanged and return.
1331 1328 *
1332 1329 * hdlp->ih_type passed in from the nexus has all the
1333 1330 * interrupt types supported by the device.
1334 1331 */
1335 1332 if (apic_support_msi == 0) { /* uninitialized */
1336 1333 /*
1337 1334 * if apic_support_msi is not set, call
1338 1335 * apic_check_msi_support() to check whether msi
1339 1336 * is supported first
1340 1337 */
1341 1338 if (apic_check_msi_support() == PSM_SUCCESS)
1342 1339 apic_support_msi = 1; /* supported */
1343 1340 else
1344 1341 apic_support_msi = -1; /* not-supported */
1345 1342 }
1346 1343 if (apic_support_msi == 1) {
1347 1344 if (apic_msix_enable)
1348 1345 *result = hdlp->ih_type;
1349 1346 else
1350 1347 *result = hdlp->ih_type & ~DDI_INTR_TYPE_MSIX;
1351 1348 } else
1352 1349 *result = hdlp->ih_type & ~(DDI_INTR_TYPE_MSI |
1353 1350 DDI_INTR_TYPE_MSIX);
1354 1351 break;
1355 1352 case PSM_INTR_OP_GET_CAP:
1356 1353 cap = DDI_INTR_FLAG_PENDING;
1357 1354 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
1358 1355 cap |= DDI_INTR_FLAG_MASKABLE;
1359 1356 *result = cap;
1360 1357 break;
1361 1358 case PSM_INTR_OP_APIC_TYPE:
1362 1359 ((apic_get_type_t *)(hdlp->ih_private))->avgi_type =
1363 1360 apix_get_apic_type();
1364 1361 ((apic_get_type_t *)(hdlp->ih_private))->avgi_num_intr =
1365 1362 APIX_IPI_MIN;
1366 1363 ((apic_get_type_t *)(hdlp->ih_private))->avgi_num_cpu =
1367 1364 apic_nproc;
1368 1365 hdlp->ih_ver = apic_get_apic_version();
1369 1366 break;
1370 1367 case PSM_INTR_OP_SET_CAP:
1371 1368 default:
1372 1369 return (PSM_FAILURE);
1373 1370 }
1374 1371
1375 1372 return (PSM_SUCCESS);
1376 1373 }
1377 1374
1378 1375 static void
1379 1376 apix_cleanup_busy(void)
1380 1377 {
1381 1378 int i, j;
1382 1379 apix_vector_t *vecp;
1383 1380
1384 1381 for (i = 0; i < apic_nproc; i++) {
1385 1382 if (!apic_cpu_in_range(i))
1386 1383 continue;
1387 1384 apic_cpus[i].aci_busy = 0;
1388 1385 for (j = APIX_AVINTR_MIN; j < APIX_AVINTR_MAX; j++) {
1389 1386 if ((vecp = xv_vector(i, j)) != NULL)
1390 1387 vecp->v_busy = 0;
1391 1388 }
1392 1389 }
1393 1390 }
1394 1391
1395 1392 static void
1396 1393 apix_redistribute_compute(void)
1397 1394 {
1398 1395 int i, j, max_busy;
1399 1396
1400 1397 if (!apic_enable_dynamic_migration)
1401 1398 return;
1402 1399
1403 1400 if (++apic_nticks == apic_sample_factor_redistribution) {
1404 1401 /*
1405 1402 * Time to call apic_intr_redistribute().
1406 1403 * reset apic_nticks. This will cause max_busy
1407 1404 * to be calculated below and if it is more than
1408 1405 * apic_int_busy, we will do the whole thing
1409 1406 */
1410 1407 apic_nticks = 0;
1411 1408 }
1412 1409 max_busy = 0;
1413 1410 for (i = 0; i < apic_nproc; i++) {
1414 1411 if (!apic_cpu_in_range(i))
1415 1412 continue;
1416 1413 /*
1417 1414 * Check if curipl is non zero & if ISR is in
1418 1415 * progress
1419 1416 */
1420 1417 if (((j = apic_cpus[i].aci_curipl) != 0) &&
1421 1418 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1422 1419
1423 1420 int vect;
1424 1421 apic_cpus[i].aci_busy++;
1425 1422 vect = apic_cpus[i].aci_current[j];
1426 1423 apixs[i]->x_vectbl[vect]->v_busy++;
1427 1424 }
1428 1425
1429 1426 if (!apic_nticks &&
1430 1427 (apic_cpus[i].aci_busy > max_busy))
1431 1428 max_busy = apic_cpus[i].aci_busy;
1432 1429 }
1433 1430 if (!apic_nticks) {
1434 1431 if (max_busy > apic_int_busy_mark) {
1435 1432 /*
1436 1433 * We could make the following check be
1437 1434 * skipped > 1 in which case, we get a
1438 1435 * redistribution at half the busy mark (due to
1439 1436 * double interval). Need to be able to collect
1440 1437 * more empirical data to decide if that is a
1441 1438 * good strategy. Punt for now.
1442 1439 */
1443 1440 apix_cleanup_busy();
1444 1441 apic_skipped_redistribute = 0;
1445 1442 } else
1446 1443 apic_skipped_redistribute++;
1447 1444 }
1448 1445 }
1449 1446
1450 1447 /*
1451 1448 * intr_ops() service routines
1452 1449 */
1453 1450
1454 1451 static int
1455 1452 apix_get_pending(apix_vector_t *vecp)
1456 1453 {
1457 1454 int bit, index, irr, pending;
1458 1455
1459 1456 /* need to get on the bound cpu */
1460 1457 mutex_enter(&cpu_lock);
1461 1458 affinity_set(vecp->v_cpuid);
1462 1459
1463 1460 index = vecp->v_vector / 32;
1464 1461 bit = vecp->v_vector % 32;
1465 1462 irr = apic_reg_ops->apic_read(APIC_IRR_REG + index);
1466 1463
1467 1464 affinity_clear();
1468 1465 mutex_exit(&cpu_lock);
1469 1466
1470 1467 pending = (irr & (1 << bit)) ? 1 : 0;
1471 1468 if (!pending && vecp->v_type == APIX_TYPE_FIXED)
1472 1469 pending = apix_intx_get_pending(vecp->v_inum);
1473 1470
1474 1471 return (pending);
1475 1472 }
1476 1473
1477 1474 static apix_vector_t *
1478 1475 apix_get_req_vector(ddi_intr_handle_impl_t *hdlp, ushort_t flags)
1479 1476 {
1480 1477 apix_vector_t *vecp;
1481 1478 processorid_t cpuid;
1482 1479 int32_t virt_vec = 0;
1483 1480
1484 1481 switch (flags & PSMGI_INTRBY_FLAGS) {
1485 1482 case PSMGI_INTRBY_IRQ:
1486 1483 return (apix_intx_get_vector(hdlp->ih_vector));
1487 1484 case PSMGI_INTRBY_VEC:
1488 1485 virt_vec = (virt_vec == 0) ? hdlp->ih_vector : virt_vec;
1489 1486
1490 1487 cpuid = APIX_VIRTVEC_CPU(virt_vec);
1491 1488 if (!apic_cpu_in_range(cpuid))
1492 1489 return (NULL);
1493 1490
1494 1491 vecp = xv_vector(cpuid, APIX_VIRTVEC_VECTOR(virt_vec));
1495 1492 break;
1496 1493 case PSMGI_INTRBY_DEFAULT:
1497 1494 vecp = apix_get_dev_map(hdlp->ih_dip, hdlp->ih_inum,
1498 1495 hdlp->ih_type);
1499 1496 break;
1500 1497 default:
1501 1498 return (NULL);
1502 1499 }
1503 1500
1504 1501 return (vecp);
1505 1502 }
1506 1503
1507 1504 static int
1508 1505 apix_get_intr_info(ddi_intr_handle_impl_t *hdlp,
1509 1506 apic_get_intr_t *intr_params_p)
1510 1507 {
1511 1508 apix_vector_t *vecp;
1512 1509 struct autovec *av_dev;
1513 1510 int i;
1514 1511
1515 1512 vecp = apix_get_req_vector(hdlp, intr_params_p->avgi_req_flags);
1516 1513 if (IS_VECT_FREE(vecp)) {
1517 1514 intr_params_p->avgi_num_devs = 0;
1518 1515 intr_params_p->avgi_cpu_id = 0;
1519 1516 intr_params_p->avgi_req_flags = 0;
1520 1517 return (PSM_SUCCESS);
1521 1518 }
1522 1519
1523 1520 if (intr_params_p->avgi_req_flags & PSMGI_REQ_CPUID) {
1524 1521 intr_params_p->avgi_cpu_id = vecp->v_cpuid;
1525 1522
1526 1523 /* Return user bound info for intrd. */
1527 1524 if (intr_params_p->avgi_cpu_id & IRQ_USER_BOUND) {
1528 1525 intr_params_p->avgi_cpu_id &= ~IRQ_USER_BOUND;
1529 1526 intr_params_p->avgi_cpu_id |= PSMGI_CPU_USER_BOUND;
1530 1527 }
1531 1528 }
1532 1529
1533 1530 if (intr_params_p->avgi_req_flags & PSMGI_REQ_VECTOR)
1534 1531 intr_params_p->avgi_vector = vecp->v_vector;
1535 1532
1536 1533 if (intr_params_p->avgi_req_flags &
1537 1534 (PSMGI_REQ_NUM_DEVS | PSMGI_REQ_GET_DEVS))
1538 1535 /* Get number of devices from apic_irq table shared field. */
1539 1536 intr_params_p->avgi_num_devs = vecp->v_share;
1540 1537
1541 1538 if (intr_params_p->avgi_req_flags & PSMGI_REQ_GET_DEVS) {
1542 1539
1543 1540 intr_params_p->avgi_req_flags |= PSMGI_REQ_NUM_DEVS;
1544 1541
1545 1542 /* Some devices have NULL dip. Don't count these. */
1546 1543 if (intr_params_p->avgi_num_devs > 0) {
1547 1544 for (i = 0, av_dev = vecp->v_autovect; av_dev;
1548 1545 av_dev = av_dev->av_link) {
1549 1546 if (av_dev->av_vector && av_dev->av_dip)
1550 1547 i++;
1551 1548 }
1552 1549 intr_params_p->avgi_num_devs =
1553 1550 (uint8_t)MIN(intr_params_p->avgi_num_devs, i);
1554 1551 }
1555 1552
1556 1553 /* There are no viable dips to return. */
1557 1554 if (intr_params_p->avgi_num_devs == 0) {
1558 1555 intr_params_p->avgi_dip_list = NULL;
1559 1556
1560 1557 } else { /* Return list of dips */
1561 1558
1562 1559 /* Allocate space in array for that number of devs. */
1563 1560 intr_params_p->avgi_dip_list = kmem_zalloc(
1564 1561 intr_params_p->avgi_num_devs *
1565 1562 sizeof (dev_info_t *),
1566 1563 KM_NOSLEEP);
1567 1564 if (intr_params_p->avgi_dip_list == NULL) {
1568 1565 DDI_INTR_IMPLDBG((CE_WARN,
1569 1566 "apix_get_vector_intr_info: no memory"));
1570 1567 return (PSM_FAILURE);
1571 1568 }
1572 1569
1573 1570 /*
1574 1571 * Loop through the device list of the autovec table
1575 1572 * filling in the dip array.
1576 1573 *
1577 1574 * Note that the autovect table may have some special
1578 1575 * entries which contain NULL dips. These will be
1579 1576 * ignored.
1580 1577 */
1581 1578 for (i = 0, av_dev = vecp->v_autovect; av_dev;
1582 1579 av_dev = av_dev->av_link) {
1583 1580 if (av_dev->av_vector && av_dev->av_dip)
1584 1581 intr_params_p->avgi_dip_list[i++] =
1585 1582 av_dev->av_dip;
1586 1583 }
1587 1584 }
1588 1585 }
1589 1586
1590 1587 return (PSM_SUCCESS);
1591 1588 }
1592 1589
1593 1590 static char *
1594 1591 apix_get_apic_type(void)
1595 1592 {
1596 1593 return (apix_psm_info.p_mach_idstring);
1597 1594 }
1598 1595
1599 1596 apix_vector_t *
1600 1597 apix_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1601 1598 {
1602 1599 apix_vector_t *newp = NULL;
1603 1600 dev_info_t *dip;
1604 1601 int inum, cap_ptr;
1605 1602 ddi_acc_handle_t handle;
1606 1603 ddi_intr_msix_t *msix_p = NULL;
1607 1604 ushort_t msix_ctrl;
1608 1605 uintptr_t off;
1609 1606 uint32_t mask;
1610 1607
1611 1608 ASSERT(LOCK_HELD(&apix_lock));
1612 1609 *result = ENXIO;
1613 1610
1614 1611 /* Fail if this is an MSI intr and is part of a group. */
1615 1612 if (vecp->v_type == APIX_TYPE_MSI) {
1616 1613 if (i_ddi_intr_get_current_nintrs(APIX_GET_DIP(vecp)) > 1)
1617 1614 return (NULL);
1618 1615 else
1619 1616 return (apix_grp_set_cpu(vecp, new_cpu, result));
1620 1617 }
1621 1618
1622 1619 /*
1623 1620 * Mask MSI-X. It's unmasked when MSI-X gets enabled.
1624 1621 */
1625 1622 if (vecp->v_type == APIX_TYPE_MSIX && IS_VECT_ENABLED(vecp)) {
1626 1623 if ((dip = APIX_GET_DIP(vecp)) == NULL)
1627 1624 return (NULL);
1628 1625 inum = vecp->v_devp->dv_inum;
1629 1626
1630 1627 handle = i_ddi_get_pci_config_handle(dip);
1631 1628 cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip);
1632 1629 msix_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSIX_CTRL);
1633 1630 if ((msix_ctrl & PCI_MSIX_FUNCTION_MASK) == 0) {
1634 1631 /*
1635 1632 * Function is not masked, then mask "inum"th
1636 1633 * entry in the MSI-X table
1637 1634 */
1638 1635 msix_p = i_ddi_get_msix(dip);
1639 1636 off = (uintptr_t)msix_p->msix_tbl_addr + (inum *
1640 1637 PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET;
1641 1638 mask = ddi_get32(msix_p->msix_tbl_hdl, (uint32_t *)off);
1642 1639 ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off,
1643 1640 mask | 1);
1644 1641 }
1645 1642 }
1646 1643
1647 1644 *result = 0;
1648 1645 if ((newp = apix_rebind(vecp, new_cpu, 1)) == NULL)
1649 1646 *result = EIO;
1650 1647
1651 1648 /* Restore mask bit */
1652 1649 if (msix_p != NULL)
1653 1650 ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, mask);
1654 1651
1655 1652 return (newp);
1656 1653 }
1657 1654
1658 1655 /*
1659 1656 * Set cpu for MSIs
1660 1657 */
1661 1658 apix_vector_t *
1662 1659 apix_grp_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1663 1660 {
1664 1661 apix_vector_t *newp, *vp;
1665 1662 uint32_t orig_cpu = vecp->v_cpuid;
1666 1663 int orig_vect = vecp->v_vector;
1667 1664 int i, num_vectors, cap_ptr, msi_mask_off;
1668 1665 uint32_t msi_pvm;
1669 1666 ushort_t msi_ctrl;
1670 1667 ddi_acc_handle_t handle;
1671 1668 dev_info_t *dip;
1672 1669
1673 1670 APIC_VERBOSE(INTR, (CE_CONT, "apix_grp_set_cpu: oldcpu: %x, vector: %x,"
1674 1671 " newcpu:%x\n", vecp->v_cpuid, vecp->v_vector, new_cpu));
1675 1672
1676 1673 ASSERT(LOCK_HELD(&apix_lock));
1677 1674
1678 1675 *result = ENXIO;
1679 1676
1680 1677 if (vecp->v_type != APIX_TYPE_MSI) {
1681 1678 DDI_INTR_IMPLDBG((CE_WARN, "set_grp: intr not MSI\n"));
1682 1679 return (NULL);
1683 1680 }
1684 1681
1685 1682 if ((dip = APIX_GET_DIP(vecp)) == NULL)
1686 1683 return (NULL);
1687 1684
1688 1685 num_vectors = i_ddi_intr_get_current_nintrs(dip);
1689 1686 if ((num_vectors < 1) || ((num_vectors - 1) & orig_vect)) {
1690 1687 APIC_VERBOSE(INTR, (CE_WARN,
1691 1688 "set_grp: base vec not part of a grp or not aligned: "
1692 1689 "vec:0x%x, num_vec:0x%x\n", orig_vect, num_vectors));
1693 1690 return (NULL);
1694 1691 }
1695 1692
1696 1693 if (vecp->v_inum != apix_get_min_dev_inum(dip, vecp->v_type))
1697 1694 return (NULL);
1698 1695
1699 1696 *result = EIO;
1700 1697 for (i = 1; i < num_vectors; i++) {
1701 1698 if ((vp = xv_vector(orig_cpu, orig_vect + i)) == NULL)
1702 1699 return (NULL);
1703 1700 #ifdef DEBUG
1704 1701 /*
1705 1702 * Sanity check: CPU and dip is the same for all entries.
1706 1703 * May be called when first msi to be enabled, at this time
1707 1704 * add_avintr() is not called for other msi
1708 1705 */
1709 1706 if ((vp->v_share != 0) &&
1710 1707 ((APIX_GET_DIP(vp) != dip) ||
1711 1708 (vp->v_cpuid != vecp->v_cpuid))) {
1712 1709 APIC_VERBOSE(INTR, (CE_WARN,
1713 1710 "set_grp: cpu or dip for vec 0x%x difft than for "
1714 1711 "vec 0x%x\n", orig_vect, orig_vect + i));
1715 1712 APIC_VERBOSE(INTR, (CE_WARN,
1716 1713 " cpu: %d vs %d, dip: 0x%p vs 0x%p\n", orig_cpu,
1717 1714 vp->v_cpuid, (void *)dip,
1718 1715 (void *)APIX_GET_DIP(vp)));
1719 1716 return (NULL);
1720 1717 }
1721 1718 #endif /* DEBUG */
1722 1719 }
1723 1720
1724 1721 cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip);
1725 1722 handle = i_ddi_get_pci_config_handle(dip);
1726 1723 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL);
1727 1724
1728 1725 /* MSI Per vector masking is supported. */
1729 1726 if (msi_ctrl & PCI_MSI_PVM_MASK) {
1730 1727 if (msi_ctrl & PCI_MSI_64BIT_MASK)
1731 1728 msi_mask_off = cap_ptr + PCI_MSI_64BIT_MASKBITS;
1732 1729 else
1733 1730 msi_mask_off = cap_ptr + PCI_MSI_32BIT_MASK;
1734 1731 msi_pvm = pci_config_get32(handle, msi_mask_off);
1735 1732 pci_config_put32(handle, msi_mask_off, (uint32_t)-1);
1736 1733 APIC_VERBOSE(INTR, (CE_CONT,
1737 1734 "set_grp: pvm supported. Mask set to 0x%x\n",
1738 1735 pci_config_get32(handle, msi_mask_off)));
1739 1736 }
1740 1737
1741 1738 if ((newp = apix_rebind(vecp, new_cpu, num_vectors)) != NULL)
1742 1739 *result = 0;
1743 1740
1744 1741 /* Reenable vectors if per vector masking is supported. */
1745 1742 if (msi_ctrl & PCI_MSI_PVM_MASK) {
1746 1743 pci_config_put32(handle, msi_mask_off, msi_pvm);
1747 1744 APIC_VERBOSE(INTR, (CE_CONT,
1748 1745 "set_grp: pvm supported. Mask restored to 0x%x\n",
1749 1746 pci_config_get32(handle, msi_mask_off)));
1750 1747 }
1751 1748
1752 1749 return (newp);
1753 1750 }
1754 1751
1755 1752 void
1756 1753 apix_intx_set_vector(int irqno, uint32_t cpuid, uchar_t vector)
1757 1754 {
1758 1755 apic_irq_t *irqp;
1759 1756
1760 1757 mutex_enter(&airq_mutex);
1761 1758 irqp = apic_irq_table[irqno];
1762 1759 irqp->airq_cpu = cpuid;
1763 1760 irqp->airq_vector = vector;
1764 1761 apic_record_rdt_entry(irqp, irqno);
1765 1762 mutex_exit(&airq_mutex);
1766 1763 }
1767 1764
1768 1765 apix_vector_t *
1769 1766 apix_intx_get_vector(int irqno)
1770 1767 {
1771 1768 apic_irq_t *irqp;
1772 1769 uint32_t cpuid;
1773 1770 uchar_t vector;
1774 1771
1775 1772 mutex_enter(&airq_mutex);
1776 1773 irqp = apic_irq_table[irqno & 0xff];
1777 1774 if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) {
1778 1775 mutex_exit(&airq_mutex);
1779 1776 return (NULL);
1780 1777 }
1781 1778 cpuid = irqp->airq_cpu;
1782 1779 vector = irqp->airq_vector;
1783 1780 mutex_exit(&airq_mutex);
1784 1781
1785 1782 return (xv_vector(cpuid, vector));
1786 1783 }
1787 1784
1788 1785 /*
1789 1786 * Must called with interrupts disabled and apic_ioapic_lock held
1790 1787 */
1791 1788 void
1792 1789 apix_intx_enable(int irqno)
1793 1790 {
1794 1791 uchar_t ioapicindex, intin;
1795 1792 apic_irq_t *irqp = apic_irq_table[irqno];
1796 1793 ioapic_rdt_t irdt;
1797 1794 apic_cpus_info_t *cpu_infop;
1798 1795 apix_vector_t *vecp = xv_vector(irqp->airq_cpu, irqp->airq_vector);
1799 1796
1800 1797 ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp));
1801 1798
1802 1799 ioapicindex = irqp->airq_ioapicindex;
1803 1800 intin = irqp->airq_intin_no;
1804 1801 cpu_infop = &apic_cpus[irqp->airq_cpu];
1805 1802
1806 1803 irdt.ir_lo = AV_PDEST | AV_FIXED | irqp->airq_rdt_entry;
1807 1804 irdt.ir_hi = cpu_infop->aci_local_id;
1808 1805
1809 1806 apic_vt_ops->apic_intrmap_alloc_entry(&vecp->v_intrmap_private, NULL,
1810 1807 vecp->v_type, 1, ioapicindex);
1811 1808 apic_vt_ops->apic_intrmap_map_entry(vecp->v_intrmap_private,
1812 1809 (void *)&irdt, vecp->v_type, 1);
1813 1810 apic_vt_ops->apic_intrmap_record_rdt(vecp->v_intrmap_private, &irdt);
1814 1811
1815 1812 /* write RDT entry high dword - destination */
1816 1813 WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin,
1817 1814 irdt.ir_hi);
1818 1815
1819 1816 /* Write the vector, trigger, and polarity portion of the RDT */
1820 1817 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin, irdt.ir_lo);
1821 1818
1822 1819 vecp->v_state = APIX_STATE_ENABLED;
1823 1820
1824 1821 APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_enable: ioapic 0x%x"
1825 1822 " intin 0x%x rdt_low 0x%x rdt_high 0x%x\n",
1826 1823 ioapicindex, intin, irdt.ir_lo, irdt.ir_hi));
1827 1824 }
1828 1825
1829 1826 /*
1830 1827 * Must called with interrupts disabled and apic_ioapic_lock held
1831 1828 */
1832 1829 void
1833 1830 apix_intx_disable(int irqno)
1834 1831 {
1835 1832 apic_irq_t *irqp = apic_irq_table[irqno];
1836 1833 int ioapicindex, intin;
1837 1834
1838 1835 ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp));
1839 1836 /*
1840 1837 * The assumption here is that this is safe, even for
1841 1838 * systems with IOAPICs that suffer from the hardware
1842 1839 * erratum because all devices have been quiesced before
1843 1840 * they unregister their interrupt handlers. If that
1844 1841 * assumption turns out to be false, this mask operation
1845 1842 * can induce the same erratum result we're trying to
1846 1843 * avoid.
1847 1844 */
1848 1845 ioapicindex = irqp->airq_ioapicindex;
1849 1846 intin = irqp->airq_intin_no;
1850 1847 ioapic_write(ioapicindex, APIC_RDT_CMD + 2 * intin, AV_MASK);
1851 1848
1852 1849 APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_disable: ioapic 0x%x"
1853 1850 " intin 0x%x\n", ioapicindex, intin));
1854 1851 }
1855 1852
1856 1853 void
1857 1854 apix_intx_free(int irqno)
1858 1855 {
1859 1856 apic_irq_t *irqp;
1860 1857
1861 1858 mutex_enter(&airq_mutex);
1862 1859 irqp = apic_irq_table[irqno];
1863 1860
1864 1861 if (IS_IRQ_FREE(irqp)) {
1865 1862 mutex_exit(&airq_mutex);
1866 1863 return;
1867 1864 }
1868 1865
1869 1866 irqp->airq_mps_intr_index = FREE_INDEX;
1870 1867 irqp->airq_cpu = IRQ_UNINIT;
1871 1868 irqp->airq_vector = APIX_INVALID_VECT;
1872 1869 mutex_exit(&airq_mutex);
1873 1870 }
1874 1871
1875 1872 #ifdef DEBUG
1876 1873 int apix_intr_deliver_timeouts = 0;
1877 1874 int apix_intr_rirr_timeouts = 0;
1878 1875 int apix_intr_rirr_reset_failure = 0;
1879 1876 #endif
1880 1877 int apix_max_reps_irr_pending = 10;
1881 1878
1882 1879 #define GET_RDT_BITS(ioapic, intin, bits) \
1883 1880 (READ_IOAPIC_RDT_ENTRY_LOW_DWORD((ioapic), (intin)) & (bits))
1884 1881 #define APIX_CHECK_IRR_DELAY drv_usectohz(5000)
1885 1882
1886 1883 int
1887 1884 apix_intx_rebind(int irqno, processorid_t cpuid, uchar_t vector)
1888 1885 {
1889 1886 apic_irq_t *irqp = apic_irq_table[irqno];
1890 1887 ulong_t iflag;
1891 1888 int waited, ioapic_ix, intin_no, level, repeats, rdt_entry, masked;
1892 1889
1893 1890 ASSERT(irqp != NULL);
1894 1891
1895 1892 iflag = intr_clear();
1896 1893 lock_set(&apic_ioapic_lock);
1897 1894
1898 1895 ioapic_ix = irqp->airq_ioapicindex;
1899 1896 intin_no = irqp->airq_intin_no;
1900 1897 level = apic_level_intr[irqno];
1901 1898
1902 1899 /*
1903 1900 * Wait for the delivery status bit to be cleared. This should
1904 1901 * be a very small amount of time.
1905 1902 */
1906 1903 repeats = 0;
1907 1904 do {
1908 1905 repeats++;
1909 1906
1910 1907 for (waited = 0; waited < apic_max_reps_clear_pending;
1911 1908 waited++) {
1912 1909 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) == 0)
1913 1910 break;
1914 1911 }
1915 1912 if (!level)
1916 1913 break;
1917 1914
1918 1915 /*
1919 1916 * Mask the RDT entry for level-triggered interrupts.
1920 1917 */
1921 1918 irqp->airq_rdt_entry |= AV_MASK;
1922 1919 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1923 1920 intin_no);
1924 1921 if ((masked = (rdt_entry & AV_MASK)) == 0) {
1925 1922 /* Mask it */
1926 1923 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no,
1927 1924 AV_MASK | rdt_entry);
1928 1925 }
1929 1926
1930 1927 /*
1931 1928 * If there was a race and an interrupt was injected
1932 1929 * just before we masked, check for that case here.
1933 1930 * Then, unmask the RDT entry and try again. If we're
1934 1931 * on our last try, don't unmask (because we want the
1935 1932 * RDT entry to remain masked for the rest of the
1936 1933 * function).
1937 1934 */
1938 1935 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1939 1936 intin_no);
1940 1937 if ((masked == 0) && ((rdt_entry & AV_PENDING) != 0) &&
1941 1938 (repeats < apic_max_reps_clear_pending)) {
1942 1939 /* Unmask it */
1943 1940 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1944 1941 intin_no, rdt_entry & ~AV_MASK);
1945 1942 irqp->airq_rdt_entry &= ~AV_MASK;
1946 1943 }
1947 1944 } while ((rdt_entry & AV_PENDING) &&
1948 1945 (repeats < apic_max_reps_clear_pending));
1949 1946
1950 1947 #ifdef DEBUG
1951 1948 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) != 0)
1952 1949 apix_intr_deliver_timeouts++;
1953 1950 #endif
1954 1951
1955 1952 if (!level || !APIX_IS_MASK_RDT(apix_mul_ioapic_method))
1956 1953 goto done;
1957 1954
1958 1955 /*
1959 1956 * wait for remote IRR to be cleared for level-triggered
1960 1957 * interrupts
1961 1958 */
1962 1959 repeats = 0;
1963 1960 do {
1964 1961 repeats++;
1965 1962
1966 1963 for (waited = 0; waited < apic_max_reps_clear_pending;
1967 1964 waited++) {
1968 1965 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR)
1969 1966 == 0)
1970 1967 break;
1971 1968 }
1972 1969
1973 1970 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
1974 1971 lock_clear(&apic_ioapic_lock);
1975 1972 intr_restore(iflag);
1976 1973
1977 1974 delay(APIX_CHECK_IRR_DELAY);
1978 1975
1979 1976 iflag = intr_clear();
1980 1977 lock_set(&apic_ioapic_lock);
1981 1978 }
1982 1979 } while (repeats < apix_max_reps_irr_pending);
1983 1980
1984 1981 if (repeats >= apix_max_reps_irr_pending) {
1985 1982 #ifdef DEBUG
1986 1983 apix_intr_rirr_timeouts++;
1987 1984 #endif
1988 1985
1989 1986 /*
1990 1987 * If we waited and the Remote IRR bit is still not cleared,
1991 1988 * AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS
1992 1989 * times for this interrupt, try the last-ditch workaround:
1993 1990 */
1994 1991 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
1995 1992 /*
1996 1993 * Trying to clear the bit through normal
1997 1994 * channels has failed. So as a last-ditch
1998 1995 * effort, try to set the trigger mode to
1999 1996 * edge, then to level. This has been
2000 1997 * observed to work on many systems.
2001 1998 */
2002 1999 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
2003 2000 intin_no,
2004 2001 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
2005 2002 intin_no) & ~AV_LEVEL);
2006 2003 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
2007 2004 intin_no,
2008 2005 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
2009 2006 intin_no) | AV_LEVEL);
2010 2007 }
2011 2008
2012 2009 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
2013 2010 #ifdef DEBUG
2014 2011 apix_intr_rirr_reset_failure++;
2015 2012 #endif
2016 2013 lock_clear(&apic_ioapic_lock);
2017 2014 intr_restore(iflag);
2018 2015 prom_printf("apix: Remote IRR still "
2019 2016 "not clear for IOAPIC %d intin %d.\n"
2020 2017 "\tInterrupts to this pin may cease "
2021 2018 "functioning.\n", ioapic_ix, intin_no);
2022 2019 return (1); /* return failure */
2023 2020 }
2024 2021 }
2025 2022
2026 2023 done:
2027 2024 /* change apic_irq_table */
2028 2025 lock_clear(&apic_ioapic_lock);
2029 2026 intr_restore(iflag);
2030 2027 apix_intx_set_vector(irqno, cpuid, vector);
2031 2028 iflag = intr_clear();
2032 2029 lock_set(&apic_ioapic_lock);
2033 2030
2034 2031 /* reprogramme IO-APIC RDT entry */
2035 2032 apix_intx_enable(irqno);
2036 2033
2037 2034 lock_clear(&apic_ioapic_lock);
2038 2035 intr_restore(iflag);
2039 2036
2040 2037 return (0);
2041 2038 }
2042 2039
2043 2040 static int
2044 2041 apix_intx_get_pending(int irqno)
2045 2042 {
2046 2043 apic_irq_t *irqp;
2047 2044 int intin, ioapicindex, pending;
2048 2045 ulong_t iflag;
2049 2046
2050 2047 mutex_enter(&airq_mutex);
2051 2048 irqp = apic_irq_table[irqno];
2052 2049 if (IS_IRQ_FREE(irqp)) {
2053 2050 mutex_exit(&airq_mutex);
2054 2051 return (0);
2055 2052 }
2056 2053
2057 2054 /* check IO-APIC delivery status */
2058 2055 intin = irqp->airq_intin_no;
2059 2056 ioapicindex = irqp->airq_ioapicindex;
2060 2057 mutex_exit(&airq_mutex);
2061 2058
2062 2059 iflag = intr_clear();
2063 2060 lock_set(&apic_ioapic_lock);
2064 2061
2065 2062 pending = (READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin) &
2066 2063 AV_PENDING) ? 1 : 0;
2067 2064
2068 2065 lock_clear(&apic_ioapic_lock);
2069 2066 intr_restore(iflag);
2070 2067
2071 2068 return (pending);
2072 2069 }
2073 2070
2074 2071 /*
2075 2072 * This function will mask the interrupt on the I/O APIC
2076 2073 */
2077 2074 static void
2078 2075 apix_intx_set_mask(int irqno)
2079 2076 {
2080 2077 int intin, ioapixindex, rdt_entry;
2081 2078 ulong_t iflag;
2082 2079 apic_irq_t *irqp;
2083 2080
2084 2081 mutex_enter(&airq_mutex);
2085 2082 irqp = apic_irq_table[irqno];
2086 2083
2087 2084 ASSERT(irqp->airq_mps_intr_index != FREE_INDEX);
2088 2085
2089 2086 intin = irqp->airq_intin_no;
2090 2087 ioapixindex = irqp->airq_ioapicindex;
2091 2088 mutex_exit(&airq_mutex);
2092 2089
2093 2090 iflag = intr_clear();
2094 2091 lock_set(&apic_ioapic_lock);
2095 2092
2096 2093 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin);
2097 2094
2098 2095 /* clear mask */
2099 2096 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin,
2100 2097 (AV_MASK | rdt_entry));
2101 2098
2102 2099 lock_clear(&apic_ioapic_lock);
2103 2100 intr_restore(iflag);
2104 2101 }
2105 2102
2106 2103 /*
2107 2104 * This function will clear the mask for the interrupt on the I/O APIC
2108 2105 */
2109 2106 static void
2110 2107 apix_intx_clear_mask(int irqno)
2111 2108 {
2112 2109 int intin, ioapixindex, rdt_entry;
2113 2110 ulong_t iflag;
2114 2111 apic_irq_t *irqp;
2115 2112
2116 2113 mutex_enter(&airq_mutex);
2117 2114 irqp = apic_irq_table[irqno];
2118 2115
2119 2116 ASSERT(irqp->airq_mps_intr_index != FREE_INDEX);
2120 2117
2121 2118 intin = irqp->airq_intin_no;
2122 2119 ioapixindex = irqp->airq_ioapicindex;
2123 2120 mutex_exit(&airq_mutex);
2124 2121
2125 2122 iflag = intr_clear();
2126 2123 lock_set(&apic_ioapic_lock);
2127 2124
2128 2125 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin);
2129 2126
2130 2127 /* clear mask */
2131 2128 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin,
2132 2129 ((~AV_MASK) & rdt_entry));
2133 2130
2134 2131 lock_clear(&apic_ioapic_lock);
2135 2132 intr_restore(iflag);
2136 2133 }
2137 2134
2138 2135 /*
2139 2136 * For level-triggered interrupt, mask the IRQ line. Mask means
2140 2137 * new interrupts will not be delivered. The interrupt already
2141 2138 * accepted by a local APIC is not affected
2142 2139 */
2143 2140 void
2144 2141 apix_level_intr_pre_eoi(int irq)
2145 2142 {
2146 2143 apic_irq_t *irqp = apic_irq_table[irq];
2147 2144 int apic_ix, intin_ix;
2148 2145
2149 2146 if (irqp == NULL)
2150 2147 return;
2151 2148
2152 2149 ASSERT(apic_level_intr[irq] == TRIGGER_MODE_LEVEL);
2153 2150
2154 2151 lock_set(&apic_ioapic_lock);
2155 2152
2156 2153 intin_ix = irqp->airq_intin_no;
2157 2154 apic_ix = irqp->airq_ioapicindex;
2158 2155
2159 2156 if (irqp->airq_cpu != CPU->cpu_id) {
2160 2157 if (!APIX_IS_MASK_RDT(apix_mul_ioapic_method))
2161 2158 ioapic_write_eoi(apic_ix, irqp->airq_vector);
2162 2159 lock_clear(&apic_ioapic_lock);
2163 2160 return;
2164 2161 }
2165 2162
2166 2163 if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC) {
2167 2164 /*
2168 2165 * This is a IOxAPIC and there is EOI register:
2169 2166 * Change the vector to reserved unused vector, so that
2170 2167 * the EOI from Local APIC won't clear the Remote IRR for
2171 2168 * this level trigger interrupt. Instead, we'll manually
2172 2169 * clear it in apix_post_hardint() after ISR handling.
2173 2170 */
2174 2171 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2175 2172 (irqp->airq_rdt_entry & (~0xff)) | APIX_RESV_VECTOR);
2176 2173 } else {
2177 2174 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2178 2175 AV_MASK | irqp->airq_rdt_entry);
2179 2176 }
2180 2177
2181 2178 lock_clear(&apic_ioapic_lock);
2182 2179 }
2183 2180
2184 2181 /*
2185 2182 * For level-triggered interrupt, unmask the IRQ line
2186 2183 * or restore the original vector number.
2187 2184 */
2188 2185 void
2189 2186 apix_level_intr_post_dispatch(int irq)
2190 2187 {
2191 2188 apic_irq_t *irqp = apic_irq_table[irq];
2192 2189 int apic_ix, intin_ix;
2193 2190
2194 2191 if (irqp == NULL)
2195 2192 return;
2196 2193
2197 2194 lock_set(&apic_ioapic_lock);
2198 2195
2199 2196 intin_ix = irqp->airq_intin_no;
2200 2197 apic_ix = irqp->airq_ioapicindex;
2201 2198
2202 2199 if (APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method)) {
2203 2200 /*
2204 2201 * Already sent EOI back to Local APIC.
2205 2202 * Send EOI to IO-APIC
2206 2203 */
2207 2204 ioapic_write_eoi(apic_ix, irqp->airq_vector);
2208 2205 } else {
2209 2206 /* clear the mask or restore the vector */
2210 2207 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2211 2208 irqp->airq_rdt_entry);
2212 2209
2213 2210 /* send EOI to IOxAPIC */
2214 2211 if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC)
2215 2212 ioapic_write_eoi(apic_ix, irqp->airq_vector);
2216 2213 }
2217 2214
2218 2215 lock_clear(&apic_ioapic_lock);
2219 2216 }
2220 2217
2221 2218 static int
2222 2219 apix_intx_get_shared(int irqno)
2223 2220 {
2224 2221 apic_irq_t *irqp;
2225 2222 int share;
2226 2223
2227 2224 mutex_enter(&airq_mutex);
2228 2225 irqp = apic_irq_table[irqno];
2229 2226 if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) {
2230 2227 mutex_exit(&airq_mutex);
2231 2228 return (0);
2232 2229 }
2233 2230 share = irqp->airq_share;
2234 2231 mutex_exit(&airq_mutex);
2235 2232
2236 2233 return (share);
2237 2234 }
2238 2235
2239 2236 static void
2240 2237 apix_intx_set_shared(int irqno, int delta)
2241 2238 {
2242 2239 apic_irq_t *irqp;
2243 2240
2244 2241 mutex_enter(&airq_mutex);
2245 2242 irqp = apic_irq_table[irqno];
2246 2243 if (IS_IRQ_FREE(irqp)) {
2247 2244 mutex_exit(&airq_mutex);
2248 2245 return;
2249 2246 }
2250 2247 irqp->airq_share += delta;
2251 2248 mutex_exit(&airq_mutex);
2252 2249 }
2253 2250
2254 2251 /*
2255 2252 * Setup IRQ table. Return IRQ no or -1 on failure
2256 2253 */
2257 2254 static int
2258 2255 apix_intx_setup(dev_info_t *dip, int inum, int irqno,
2259 2256 struct apic_io_intr *intrp, struct intrspec *ispec, iflag_t *iflagp)
2260 2257 {
2261 2258 int origirq = ispec->intrspec_vec;
2262 2259 int newirq;
2263 2260 short intr_index;
2264 2261 uchar_t ipin, ioapic, ioapicindex;
2265 2262 apic_irq_t *irqp;
2266 2263
2267 2264 UNREFERENCED_1PARAMETER(inum);
2268 2265
2269 2266 if (intrp != NULL) {
2270 2267 intr_index = (short)(intrp - apic_io_intrp);
2271 2268 ioapic = intrp->intr_destid;
2272 2269 ipin = intrp->intr_destintin;
2273 2270
2274 2271 /* Find ioapicindex. If destid was ALL, we will exit with 0. */
2275 2272 for (ioapicindex = apic_io_max - 1; ioapicindex; ioapicindex--)
2276 2273 if (apic_io_id[ioapicindex] == ioapic)
2277 2274 break;
2278 2275 ASSERT((ioapic == apic_io_id[ioapicindex]) ||
2279 2276 (ioapic == INTR_ALL_APIC));
2280 2277
2281 2278 /* check whether this intin# has been used by another irqno */
2282 2279 if ((newirq = apic_find_intin(ioapicindex, ipin)) != -1)
2283 2280 return (newirq);
2284 2281
2285 2282 } else if (iflagp != NULL) { /* ACPI */
2286 2283 intr_index = ACPI_INDEX;
2287 2284 ioapicindex = acpi_find_ioapic(irqno);
2288 2285 ASSERT(ioapicindex != 0xFF);
2289 2286 ioapic = apic_io_id[ioapicindex];
2290 2287 ipin = irqno - apic_io_vectbase[ioapicindex];
2291 2288
2292 2289 if (apic_irq_table[irqno] &&
2293 2290 apic_irq_table[irqno]->airq_mps_intr_index == ACPI_INDEX) {
2294 2291 ASSERT(apic_irq_table[irqno]->airq_intin_no == ipin &&
2295 2292 apic_irq_table[irqno]->airq_ioapicindex ==
2296 2293 ioapicindex);
2297 2294 return (irqno);
2298 2295 }
2299 2296
2300 2297 } else { /* default configuration */
2301 2298 intr_index = DEFAULT_INDEX;
2302 2299 ioapicindex = 0;
2303 2300 ioapic = apic_io_id[ioapicindex];
2304 2301 ipin = (uchar_t)irqno;
2305 2302 }
2306 2303
2307 2304 /* allocate a new IRQ no */
2308 2305 if ((irqp = apic_irq_table[irqno]) == NULL) {
2309 2306 irqp = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP);
2310 2307 apic_irq_table[irqno] = irqp;
2311 2308 } else {
2312 2309 if (irqp->airq_mps_intr_index != FREE_INDEX) {
2313 2310 newirq = apic_allocate_irq(apic_first_avail_irq);
2314 2311 if (newirq == -1) {
2315 2312 return (-1);
2316 2313 }
2317 2314 irqno = newirq;
2318 2315 irqp = apic_irq_table[irqno];
2319 2316 ASSERT(irqp != NULL);
2320 2317 }
2321 2318 }
2322 2319 apic_max_device_irq = max(irqno, apic_max_device_irq);
2323 2320 apic_min_device_irq = min(irqno, apic_min_device_irq);
2324 2321
2325 2322 irqp->airq_mps_intr_index = intr_index;
2326 2323 irqp->airq_ioapicindex = ioapicindex;
2327 2324 irqp->airq_intin_no = ipin;
2328 2325 irqp->airq_dip = dip;
2329 2326 irqp->airq_origirq = (uchar_t)origirq;
2330 2327 if (iflagp != NULL)
2331 2328 irqp->airq_iflag = *iflagp;
2332 2329 irqp->airq_cpu = IRQ_UNINIT;
2333 2330 irqp->airq_vector = 0;
2334 2331
2335 2332 return (irqno);
2336 2333 }
2337 2334
2338 2335 /*
2339 2336 * Setup IRQ table for non-pci devices. Return IRQ no or -1 on error
2340 2337 */
2341 2338 static int
2342 2339 apix_intx_setup_nonpci(dev_info_t *dip, int inum, int bustype,
2343 2340 struct intrspec *ispec)
2344 2341 {
2345 2342 int irqno = ispec->intrspec_vec;
2346 2343 int newirq, i;
2347 2344 iflag_t intr_flag;
2348 2345 ACPI_SUBTABLE_HEADER *hp;
2349 2346 ACPI_MADT_INTERRUPT_OVERRIDE *isop;
2350 2347 struct apic_io_intr *intrp;
2351 2348
2352 2349 if (!apic_enable_acpi || apic_use_acpi_madt_only) {
2353 2350 int busid;
2354 2351
2355 2352 if (bustype == 0)
2356 2353 bustype = eisa_level_intr_mask ? BUS_EISA : BUS_ISA;
2357 2354
2358 2355 /* loop checking BUS_ISA/BUS_EISA */
2359 2356 for (i = 0; i < 2; i++) {
2360 2357 if (((busid = apic_find_bus_id(bustype)) != -1) &&
2361 2358 ((intrp = apic_find_io_intr_w_busid(irqno, busid))
2362 2359 != NULL)) {
2363 2360 return (apix_intx_setup(dip, inum, irqno,
2364 2361 intrp, ispec, NULL));
2365 2362 }
2366 2363 bustype = (bustype == BUS_EISA) ? BUS_ISA : BUS_EISA;
2367 2364 }
2368 2365
2369 2366 /* fall back to default configuration */
2370 2367 return (-1);
2371 2368 }
2372 2369
2373 2370 /* search iso entries first */
2374 2371 if (acpi_iso_cnt != 0) {
2375 2372 hp = (ACPI_SUBTABLE_HEADER *)acpi_isop;
2376 2373 i = 0;
2377 2374 while (i < acpi_iso_cnt) {
2378 2375 if (hp->Type == ACPI_MADT_TYPE_INTERRUPT_OVERRIDE) {
2379 2376 isop = (ACPI_MADT_INTERRUPT_OVERRIDE *) hp;
2380 2377 if (isop->Bus == 0 &&
2381 2378 isop->SourceIrq == irqno) {
2382 2379 newirq = isop->GlobalIrq;
2383 2380 intr_flag.intr_po = isop->IntiFlags &
2384 2381 ACPI_MADT_POLARITY_MASK;
2385 2382 intr_flag.intr_el = (isop->IntiFlags &
2386 2383 ACPI_MADT_TRIGGER_MASK) >> 2;
2387 2384 intr_flag.bustype = BUS_ISA;
2388 2385
2389 2386 return (apix_intx_setup(dip, inum,
2390 2387 newirq, NULL, ispec, &intr_flag));
2391 2388 }
2392 2389 i++;
2393 2390 }
2394 2391 hp = (ACPI_SUBTABLE_HEADER *)(((char *)hp) +
2395 2392 hp->Length);
2396 2393 }
2397 2394 }
2398 2395 intr_flag.intr_po = INTR_PO_ACTIVE_HIGH;
2399 2396 intr_flag.intr_el = INTR_EL_EDGE;
2400 2397 intr_flag.bustype = BUS_ISA;
2401 2398 return (apix_intx_setup(dip, inum, irqno, NULL, ispec, &intr_flag));
2402 2399 }
2403 2400
2404 2401
2405 2402 /*
2406 2403 * Setup IRQ table for pci devices. Return IRQ no or -1 on error
2407 2404 */
2408 2405 static int
2409 2406 apix_intx_setup_pci(dev_info_t *dip, int inum, int bustype,
2410 2407 struct intrspec *ispec)
2411 2408 {
2412 2409 int busid, devid, pci_irq;
2413 2410 ddi_acc_handle_t cfg_handle;
2414 2411 uchar_t ipin;
2415 2412 iflag_t intr_flag;
2416 2413 struct apic_io_intr *intrp;
2417 2414
2418 2415 if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0)
2419 2416 return (-1);
2420 2417
2421 2418 if (busid == 0 && apic_pci_bus_total == 1)
2422 2419 busid = (int)apic_single_pci_busid;
2423 2420
2424 2421 if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS)
2425 2422 return (-1);
2426 2423 ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA;
2427 2424 pci_config_teardown(&cfg_handle);
2428 2425
2429 2426 if (apic_enable_acpi && !apic_use_acpi_madt_only) { /* ACPI */
2430 2427 if (apic_acpi_translate_pci_irq(dip, busid, devid,
2431 2428 ipin, &pci_irq, &intr_flag) != ACPI_PSM_SUCCESS)
2432 2429 return (-1);
2433 2430
2434 2431 intr_flag.bustype = (uchar_t)bustype;
2435 2432 return (apix_intx_setup(dip, inum, pci_irq, NULL, ispec,
2436 2433 &intr_flag));
2437 2434 }
2438 2435
2439 2436 /* MP configuration table */
2440 2437 pci_irq = ((devid & 0x1f) << 2) | (ipin & 0x3);
2441 2438 if ((intrp = apic_find_io_intr_w_busid(pci_irq, busid)) == NULL) {
2442 2439 pci_irq = apic_handle_pci_pci_bridge(dip, devid, ipin, &intrp);
2443 2440 if (pci_irq == -1)
2444 2441 return (-1);
2445 2442 }
2446 2443
2447 2444 return (apix_intx_setup(dip, inum, pci_irq, intrp, ispec, NULL));
2448 2445 }
2449 2446
2450 2447 /*
2451 2448 * Translate and return IRQ no
2452 2449 */
2453 2450 static int
2454 2451 apix_intx_xlate_irq(dev_info_t *dip, int inum, struct intrspec *ispec)
2455 2452 {
2456 2453 int newirq, irqno = ispec->intrspec_vec;
2457 2454 int parent_is_pci_or_pciex = 0, child_is_pciex = 0;
2458 2455 int bustype = 0, dev_len;
2459 2456 char dev_type[16];
2460 2457
2461 2458 if (apic_defconf) {
2462 2459 mutex_enter(&airq_mutex);
2463 2460 goto defconf;
2464 2461 }
2465 2462
2466 2463 if ((dip == NULL) || (!apic_irq_translate && !apic_enable_acpi)) {
2467 2464 mutex_enter(&airq_mutex);
2468 2465 goto nonpci;
2469 2466 }
2470 2467
2471 2468 /*
2472 2469 * use ddi_getlongprop_buf() instead of ddi_prop_lookup_string()
2473 2470 * to avoid extra buffer allocation.
2474 2471 */
2475 2472 dev_len = sizeof (dev_type);
2476 2473 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip),
2477 2474 DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type,
2478 2475 &dev_len) == DDI_PROP_SUCCESS) {
2479 2476 if ((strcmp(dev_type, "pci") == 0) ||
2480 2477 (strcmp(dev_type, "pciex") == 0))
2481 2478 parent_is_pci_or_pciex = 1;
2482 2479 }
2483 2480
2484 2481 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip,
2485 2482 DDI_PROP_DONTPASS, "compatible", (caddr_t)dev_type,
2486 2483 &dev_len) == DDI_PROP_SUCCESS) {
2487 2484 if (strstr(dev_type, "pciex"))
2488 2485 child_is_pciex = 1;
2489 2486 }
2490 2487
2491 2488 mutex_enter(&airq_mutex);
2492 2489
2493 2490 if (parent_is_pci_or_pciex) {
2494 2491 bustype = child_is_pciex ? BUS_PCIE : BUS_PCI;
2495 2492 newirq = apix_intx_setup_pci(dip, inum, bustype, ispec);
2496 2493 if (newirq != -1)
2497 2494 goto done;
2498 2495 bustype = 0;
2499 2496 } else if (strcmp(dev_type, "isa") == 0)
2500 2497 bustype = BUS_ISA;
2501 2498 else if (strcmp(dev_type, "eisa") == 0)
2502 2499 bustype = BUS_EISA;
2503 2500
2504 2501 nonpci:
2505 2502 newirq = apix_intx_setup_nonpci(dip, inum, bustype, ispec);
2506 2503 if (newirq != -1)
2507 2504 goto done;
2508 2505
2509 2506 defconf:
2510 2507 newirq = apix_intx_setup(dip, inum, irqno, NULL, ispec, NULL);
2511 2508 if (newirq == -1) {
2512 2509 mutex_exit(&airq_mutex);
2513 2510 return (-1);
2514 2511 }
2515 2512 done:
2516 2513 ASSERT(apic_irq_table[newirq]);
2517 2514 mutex_exit(&airq_mutex);
2518 2515 return (newirq);
2519 2516 }
2520 2517
2521 2518 static int
2522 2519 apix_intx_alloc_vector(dev_info_t *dip, int inum, struct intrspec *ispec)
2523 2520 {
2524 2521 int irqno;
2525 2522 apix_vector_t *vecp;
2526 2523
2527 2524 if ((irqno = apix_intx_xlate_irq(dip, inum, ispec)) == -1)
2528 2525 return (0);
2529 2526
2530 2527 if ((vecp = apix_alloc_intx(dip, inum, irqno)) == NULL)
2531 2528 return (0);
2532 2529
2533 2530 DDI_INTR_IMPLDBG((CE_CONT, "apix_intx_alloc_vector: dip=0x%p name=%s "
2534 2531 "irqno=0x%x cpuid=%d vector=0x%x\n",
2535 2532 (void *)dip, ddi_driver_name(dip), irqno,
2536 2533 vecp->v_cpuid, vecp->v_vector));
2537 2534
2538 2535 return (1);
2539 2536 }
2540 2537
2541 2538 /*
2542 2539 * Return the vector number if the translated IRQ for this device
2543 2540 * has a vector mapping setup. If no IRQ setup exists or no vector is
2544 2541 * allocated to it then return 0.
2545 2542 */
2546 2543 static apix_vector_t *
2547 2544 apix_intx_xlate_vector(dev_info_t *dip, int inum, struct intrspec *ispec)
2548 2545 {
2549 2546 int irqno;
2550 2547 apix_vector_t *vecp;
2551 2548
2552 2549 /* get the IRQ number */
2553 2550 if ((irqno = apix_intx_xlate_irq(dip, inum, ispec)) == -1)
2554 2551 return (NULL);
2555 2552
2556 2553 /* get the vector number if a vector is allocated to this irqno */
2557 2554 vecp = apix_intx_get_vector(irqno);
2558 2555
2559 2556 return (vecp);
2560 2557 }
2561 2558
2562 2559 /* stub function */
2563 2560 int
2564 2561 apix_loaded(void)
2565 2562 {
2566 2563 return (apix_is_enabled);
2567 2564 }
↓ open down ↓ |
2181 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX