13 * Copyright (c) 2014 Joyent, Inc. All rights reserved.
14 */
15
16 #ifndef _SYS_CPUID_IMPL_H
17 #define _SYS_CPUID_IMPL_H
18
19 #include <sys/stdint.h>
20 #include <sys/arm_archext.h>
21 #include <sys/types.h>
22
23 /*
24 * Routines to read ARM cpuid co-processors
25 */
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 typedef struct arm_cpuid_cache {
32 boolean_t acc_exists;
33 boolean_t acc_rcolor;
34 uint8_t acc_assoc;
35 uint8_t acc_linesz;
36 uint32_t acc_size;
37 } arm_cpuid_cache_t;
38
39 typedef struct arm_cpuid {
40 uint32_t ac_ident;
41 uint32_t ac_pfr[2];
42 uint32_t ac_dfr;
43 uint32_t ac_mmfr[4];
44 uint32_t ac_isar[6];
45 uint32_t ac_fpident;
46 uint32_t ac_mvfr[2];
47 boolean_t ac_unifiedl1;
48 arm_cpuid_cache_t ac_icache;
49 arm_cpuid_cache_t ac_dcache;
50 } arm_cpuid_t;
51
52 extern uint32_t arm_cpuid_idreg();
53 extern uint32_t arm_cpuid_pfr0();
54 extern uint32_t arm_cpuid_pfr1();
55 extern uint32_t arm_cpuid_dfr0();
56 extern uint32_t arm_cpuid_mmfr0();
57 extern uint32_t arm_cpuid_mmfr1();
58 extern uint32_t arm_cpuid_mmfr2();
59 extern uint32_t arm_cpuid_mmfr3();
60 extern uint32_t arm_cpuid_isar0();
61 extern uint32_t arm_cpuid_isar1();
62 extern uint32_t arm_cpuid_isar2();
63 extern uint32_t arm_cpuid_isar3();
64 extern uint32_t arm_cpuid_isar4();
65 extern uint32_t arm_cpuid_isar5();
66
67 extern uint32_t arm_cpuid_vfpidreg();
68 extern uint32_t arm_cpuid_mvfr0();
69 extern uint32_t arm_cpuid_mvfr1();
70
71 extern uint32_t arm_cpuid_ctr();
72
73 #ifdef __cplusplus
74 }
75 #endif
76
77 #endif /* _SYS_CPUID_IMPL_H */
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13 * Copyright (c) 2014 Joyent, Inc. All rights reserved.
14 */
15
16 #ifndef _SYS_CPUID_IMPL_H
17 #define _SYS_CPUID_IMPL_H
18
19 #include <sys/stdint.h>
20 #include <sys/arm_archext.h>
21 #include <sys/types.h>
22
23 /*
24 * Routines to read ARM cpuid co-processors
25 */
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 typedef struct arm_cpuid_cache {
32 boolean_t acc_exists;
33 boolean_t acc_unified;
34 boolean_t acc_wt;
35 boolean_t acc_wb;
36 boolean_t acc_ra;
37 boolean_t acc_wa;
38 uint16_t acc_sets;
39 uint8_t acc_linesz;
40 uint16_t acc_assoc;
41
42 boolean_t acc_rcolor;
43 uint32_t acc_size;
44 } arm_cpuid_cache_t;
45
46 typedef struct arm_cpuid {
47 uint32_t ac_ident;
48 uint32_t ac_pfr[2];
49 uint32_t ac_dfr;
50 uint32_t ac_mmfr[4];
51 uint32_t ac_isar[6];
52 uint32_t ac_fpident;
53 uint32_t ac_mvfr[2];
54 uint32_t ac_clidr;
55
56 /*
57 * ARM supports 7 levels of caches. Each level can have separate
58 * I/D caches or a unified cache. We keep track of all these as a
59 * two dimensional array. First, we select if we're dealing with a
60 * I cache (B_TRUE) or a D/unified cache (B_FALSE), and then we
61 * index on the level. Note that L1 caches are at index 0.
62 */
63 uint32_t ac_ccsidr[2][7];
64 arm_cpuid_cache_t ac_caches[2][7];
65 } arm_cpuid_t;
66
67 extern uint32_t arm_cpuid_midr();
68 extern uint32_t arm_cpuid_pfr0();
69 extern uint32_t arm_cpuid_pfr1();
70 extern uint32_t arm_cpuid_dfr0();
71 extern uint32_t arm_cpuid_mmfr0();
72 extern uint32_t arm_cpuid_mmfr1();
73 extern uint32_t arm_cpuid_mmfr2();
74 extern uint32_t arm_cpuid_mmfr3();
75 extern uint32_t arm_cpuid_isar0();
76 extern uint32_t arm_cpuid_isar1();
77 extern uint32_t arm_cpuid_isar2();
78 extern uint32_t arm_cpuid_isar3();
79 extern uint32_t arm_cpuid_isar4();
80 extern uint32_t arm_cpuid_isar5();
81
82 extern uint32_t arm_cpuid_vfpidreg();
83 extern uint32_t arm_cpuid_mvfr0();
84 extern uint32_t arm_cpuid_mvfr1();
85
86 extern uint32_t arm_cpuid_clidr();
87 extern uint32_t arm_cpuid_ccsidr(uint32_t level, boolean_t icache);
88
89 #ifdef __cplusplus
90 }
91 #endif
92
93 #endif /* _SYS_CPUID_IMPL_H */
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