1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2014 Joyent, Inc. All rights reserved. 14 */ 15 16 .file "cpuid.s" 17 18 /* 19 * Read cpuid values from coprocessors 20 */ 21 22 #include <sys/asm_linkage.h> 23 24 #if defined(lint) || defined(__lint) 25 26 uint32_t 27 arm_cpuid_idreg() 28 {} 29 30 uint32_t 31 arm_cpuid_pfr0() 32 {} 33 34 uint32_t 35 arm_cpuid_pfr1() 36 {} 37 38 uint32_t 39 arm_cpuid_dfr0() 40 {} 41 42 uint32_t 43 arm_cpuid_mmfr0() 44 {} 45 46 uint32_t 47 arm_cpuid_mmfr1() 48 {} 49 50 uint32_t 51 arm_cpuid_mmfr2() 52 {} 53 54 uint32_t 55 arm_cpuid_mmfr3() 56 {} 57 58 uint32_t 59 arm_cpuid_isar0() 60 {} 61 62 uint32_t 63 arm_cpuid_isar1() 64 {} 65 66 uint32_t 67 arm_cpuid_isar2() 68 {} 69 70 uint32_t 71 arm_cpuid_isar3() 72 {} 73 74 uint32_t 75 arm_cpuid_isar4() 76 {} 77 78 uint32_t 79 arm_cpuid_isar5() 80 {} 81 82 uint32_t 83 arm_cpuid_vfpidreg() 84 {} 85 86 uint32_t 87 arm_cpuid_mvfr0() 88 {} 89 90 uint32_t 91 arm_cpuid_mvfr1() 92 {} 93 94 uint32_t 95 arm_cpuid_ctr() 96 {} 97 98 #else /* __lint */ 99 100 ENTRY(arm_cpuid_idreg) 101 mrc p15, 0, r0, c0, c0, 0 102 bx lr 103 SET_SIZE(arm_cpuid_idreg) 104 105 ENTRY(arm_cpuid_pfr0) 106 mrc p15, 0, r0, c0, c1, 0 107 bx lr 108 SET_SIZE(arm_cpuid_pfr0) 109 110 ENTRY(arm_cpuid_pfr1) 111 mrc p15, 0, r0, c0, c1, 1 112 bx lr 113 SET_SIZE(arm_cpuid_pfr1) 114 115 ENTRY(arm_cpuid_dfr0) 116 mrc p15, 0, r0, c0, c1, 2 117 bx lr 118 SET_SIZE(arm_cpuid_dfr0) 119 120 ENTRY(arm_cpuid_mmfr0) 121 mrc p15, 0, r0, c0, c1, 4 122 bx lr 123 SET_SIZE(arm_cpuid_mmfr0) 124 125 ENTRY(arm_cpuid_mmfr1) 126 mrc p15, 0, r0, c0, c1, 5 127 bx lr 128 SET_SIZE(arm_cpuid_mmfr1) 129 130 ENTRY(arm_cpuid_mmfr2) 131 mrc p15, 0, r0, c0, c1, 6 132 bx lr 133 SET_SIZE(arm_cpuid_mmfr2) 134 135 ENTRY(arm_cpuid_mmfr3) 136 mrc p15, 0, r0, c0, c1, 7 137 bx lr 138 SET_SIZE(arm_cpuid_mmfr3) 139 140 ENTRY(arm_cpuid_isar0) 141 mrc p15, 0, r0, c0, c2, 0 142 bx lr 143 SET_SIZE(arm_cpuid_isar0) 144 145 ENTRY(arm_cpuid_isar1) 146 mrc p15, 0, r0, c0, c2, 1 147 bx lr 148 SET_SIZE(arm_cpuid_isar1) 149 150 ENTRY(arm_cpuid_isar2) 151 mrc p15, 0, r0, c0, c2, 2 152 bx lr 153 SET_SIZE(arm_cpuid_isar2) 154 155 ENTRY(arm_cpuid_isar3) 156 mrc p15, 0, r0, c0, c2, 3 157 bx lr 158 SET_SIZE(arm_cpuid_isar3) 159 160 ENTRY(arm_cpuid_isar4) 161 mrc p15, 0, r0, c0, c2, 4 162 bx lr 163 SET_SIZE(arm_cpuid_isar4) 164 165 ENTRY(arm_cpuid_isar5) 166 mrc p15, 0, r0, c0, c2, 5 167 bx lr 168 SET_SIZE(arm_cpuid_isar5) 169 170 ENTRY(arm_cpuid_vfpidreg) 171 vmrs r0, FPSID 172 bx lr 173 SET_SIZE(arm_cpuid_vfpidreg) 174 175 ENTRY(arm_cpuid_mvfr0) 176 vmrs r0, MVFR0 177 bx lr 178 SET_SIZE(arm_cpuid_mvfr0) 179 180 ENTRY(arm_cpuid_mvfr1) 181 vmrs r0, MVFR1 182 bx lr 183 SET_SIZE(arm_cpuid_mvfr1) 184 185 ENTRY(arm_cpuid_ctr) 186 mrc p15, 0, r0, c0, c0, 1 187 bx lr 188 SET_SIZE(arm_cpuid_ctr) 189 #endif /* __lint */