132 /* status reg3 */
133 #define WP_SR3 0x40 /* write protected */
134 #define T0_SR3 0x10 /* track zero */
135
136 /* DOR - Digital Output register - 82077 only */
137 #define EJECT 0x80 /* eject diskette - was in Auxio */
138 #define EJECT_DMA 0x20 /* eject diskette - on DMA platform */
139 #define MOTEN(unit) (unit ? 0x30 : 0x10) /* motor enable bit */
140 #define DMAGATE 0x8 /* must be high to enable interrupts */
141 #define RESET 0x4 /* reset bit */
142 #define DRVSEL 0x1 /* drive select */
143
144 /* DIR - Digital Input register - 82077 only */
145 #define DSKCHG 0x80 /* diskette was changed - was in Auxio */
146
147 #define DRV_MASK 0x03 /* drive mask for the second command byte */
148
149 #ifndef _ASM
150 #define Moton_delay (drv_usectohz(750000)) /* motor on delay */
151 /* 0.75 seconds */
152 #define Motoff_delay (6 * drv_usectohz(1000000)) /* motor off delay */
153 /* 6 seconds */
154
155 /* Macros to set and retrieve data from the controller registers */
156 #define Msr(fdc) ddi_get8(fdc->c_handlep_cont, \
157 ((uint8_t *)fdc->c_control))
158 #define Dsr(fdc, val) ddi_put8(fdc->c_handlep_cont, \
159 ((uint8_t *)fdc->c_control),\
160 ((uint8_t)val))
161 #define Dir(fdc) ddi_get8(fdc->c_handlep_cont, \
162 ((uint8_t *)fdc->c_dir))
163 #define Fifo(fdc) ddi_get8(fdc->c_handlep_cont, \
164 ((uint8_t *)fdc->c_fifo))
165 #define Set_Fifo(fdc, val) ddi_put8(fdc->c_handlep_cont, \
166 ((uint8_t *)fdc->c_fifo), \
167 ((uint8_t)val))
168 #define Dor(fdc) ddi_get8(fdc->c_handlep_cont, ((uint8_t *)fdc->c_dor))
169 #define Set_dor(fdc, val, flag) \
170 { if (flag) \
171 ddi_put8(fdc->c_handlep_cont, ((uint8_t *)fdc->c_dor), \
172 ((uint8_t)(Dor(fdc) | (val)))); \
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132 /* status reg3 */
133 #define WP_SR3 0x40 /* write protected */
134 #define T0_SR3 0x10 /* track zero */
135
136 /* DOR - Digital Output register - 82077 only */
137 #define EJECT 0x80 /* eject diskette - was in Auxio */
138 #define EJECT_DMA 0x20 /* eject diskette - on DMA platform */
139 #define MOTEN(unit) (unit ? 0x30 : 0x10) /* motor enable bit */
140 #define DMAGATE 0x8 /* must be high to enable interrupts */
141 #define RESET 0x4 /* reset bit */
142 #define DRVSEL 0x1 /* drive select */
143
144 /* DIR - Digital Input register - 82077 only */
145 #define DSKCHG 0x80 /* diskette was changed - was in Auxio */
146
147 #define DRV_MASK 0x03 /* drive mask for the second command byte */
148
149 #ifndef _ASM
150 #define Moton_delay (drv_usectohz(750000)) /* motor on delay */
151 /* 0.75 seconds */
152 #define Motoff_delay drv_sectohz(6) /* motor off delay */
153 /* 6 seconds */
154
155 /* Macros to set and retrieve data from the controller registers */
156 #define Msr(fdc) ddi_get8(fdc->c_handlep_cont, \
157 ((uint8_t *)fdc->c_control))
158 #define Dsr(fdc, val) ddi_put8(fdc->c_handlep_cont, \
159 ((uint8_t *)fdc->c_control),\
160 ((uint8_t)val))
161 #define Dir(fdc) ddi_get8(fdc->c_handlep_cont, \
162 ((uint8_t *)fdc->c_dir))
163 #define Fifo(fdc) ddi_get8(fdc->c_handlep_cont, \
164 ((uint8_t *)fdc->c_fifo))
165 #define Set_Fifo(fdc, val) ddi_put8(fdc->c_handlep_cont, \
166 ((uint8_t *)fdc->c_fifo), \
167 ((uint8_t)val))
168 #define Dor(fdc) ddi_get8(fdc->c_handlep_cont, ((uint8_t *)fdc->c_dor))
169 #define Set_dor(fdc, val, flag) \
170 { if (flag) \
171 ddi_put8(fdc->c_handlep_cont, ((uint8_t *)fdc->c_dor), \
172 ((uint8_t)(Dor(fdc) | (val)))); \
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