5028          * Print the ISP firmware revision number and attributes information
5029          * Read the RISC to Host Status register
5030          */
5031         n = (int)snprintf(buf, size_left, "ISP FW Version %d.%02d.%02d "
5032             "Attributes %04x\n\nR2H Status Register\n%08x",
5033             qlt->fw_major, qlt->fw_minor,
5034             qlt->fw_subminor, qlt->fw_attr, REG_RD32(qlt, REG_RISC_STATUS));
5035         buf += n; size_left -= n;
5036 
5037         /*
5038          * Before pausing the RISC, make sure no mailbox can execute
5039          */
5040         mutex_enter(&qlt->mbox_lock);
5041         if (qlt->mbox_io_state != MBOX_STATE_UNKNOWN) {
5042                 /*
5043                  * Wait to grab the mailboxes
5044                  */
5045                 for (retries = 0; (qlt->mbox_io_state != MBOX_STATE_READY) &&
5046                     (qlt->mbox_io_state != MBOX_STATE_UNKNOWN); retries++) {
5047                         (void) cv_timedwait(&qlt->mbox_cv, &qlt->mbox_lock,
5048                             ddi_get_lbolt() + drv_usectohz(1000000));
5049                         if (retries > 5) {
5050                                 mutex_exit(&qlt->mbox_lock);
5051                                 EL(qlt, "can't drain out mailbox commands\n");
5052                                 goto dump_fail;
5053                         }
5054                 }
5055                 qlt->mbox_io_state = MBOX_STATE_UNKNOWN;
5056                 cv_broadcast(&qlt->mbox_cv);
5057         }
5058         mutex_exit(&qlt->mbox_lock);
5059 
5060         /*
5061          * Pause the RISC processor
5062          */
5063         REG_WR32(qlt, REG_HCCR, HCCR_CMD(SET_RISC_PAUSE));
5064 
5065         /*
5066          * Wait for the RISC processor to pause
5067          */
5068         for (i = 0; i < 200; i++) {

5028          * Print the ISP firmware revision number and attributes information
5029          * Read the RISC to Host Status register
5030          */
5031         n = (int)snprintf(buf, size_left, "ISP FW Version %d.%02d.%02d "
5032             "Attributes %04x\n\nR2H Status Register\n%08x",
5033             qlt->fw_major, qlt->fw_minor,
5034             qlt->fw_subminor, qlt->fw_attr, REG_RD32(qlt, REG_RISC_STATUS));
5035         buf += n; size_left -= n;
5036 
5037         /*
5038          * Before pausing the RISC, make sure no mailbox can execute
5039          */
5040         mutex_enter(&qlt->mbox_lock);
5041         if (qlt->mbox_io_state != MBOX_STATE_UNKNOWN) {
5042                 /*
5043                  * Wait to grab the mailboxes
5044                  */
5045                 for (retries = 0; (qlt->mbox_io_state != MBOX_STATE_READY) &&
5046                     (qlt->mbox_io_state != MBOX_STATE_UNKNOWN); retries++) {
5047                         (void) cv_timedwait(&qlt->mbox_cv, &qlt->mbox_lock,
5048                             ddi_get_lbolt() + drv_sectohz(1));
5049                         if (retries > 5) {
5050                                 mutex_exit(&qlt->mbox_lock);
5051                                 EL(qlt, "can't drain out mailbox commands\n");
5052                                 goto dump_fail;
5053                         }
5054                 }
5055                 qlt->mbox_io_state = MBOX_STATE_UNKNOWN;
5056                 cv_broadcast(&qlt->mbox_cv);
5057         }
5058         mutex_exit(&qlt->mbox_lock);
5059 
5060         /*
5061          * Pause the RISC processor
5062          */
5063         REG_WR32(qlt, REG_HCCR, HCCR_CMD(SET_RISC_PAUSE));
5064 
5065         /*
5066          * Wait for the RISC processor to pause
5067          */
5068         for (i = 0; i < 200; i++) {