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4804 apix & pcplusmp are nearly warning free already
Tentatively Reviewed by: Robert Mustacchi <rm@joyent.com>
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--- old/usr/src/uts/i86pc/io/pcplusmp/apic.c
+++ new/usr/src/uts/i86pc/io/pcplusmp/apic.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
31 31 */
32 32
33 33 /*
34 34 * To understand how the pcplusmp module interacts with the interrupt subsystem
35 35 * read the theory statement in uts/i86pc/os/intr.c.
36 36 */
37 37
38 38 /*
39 39 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
40 40 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
41 41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
42 42 * PSMI 1.5 extensions are supported in Solaris Nevada.
43 43 * PSMI 1.6 extensions are supported in Solaris Nevada.
44 44 * PSMI 1.7 extensions are supported in Solaris Nevada.
45 45 */
46 46 #define PSMI_1_7
47 47
48 48 #include <sys/processor.h>
49 49 #include <sys/time.h>
50 50 #include <sys/psm.h>
51 51 #include <sys/smp_impldefs.h>
52 52 #include <sys/cram.h>
53 53 #include <sys/acpi/acpi.h>
54 54 #include <sys/acpica.h>
55 55 #include <sys/psm_common.h>
56 56 #include <sys/apic.h>
57 57 #include <sys/pit.h>
58 58 #include <sys/ddi.h>
59 59 #include <sys/sunddi.h>
60 60 #include <sys/ddi_impldefs.h>
61 61 #include <sys/pci.h>
62 62 #include <sys/promif.h>
63 63 #include <sys/x86_archext.h>
64 64 #include <sys/cpc_impl.h>
65 65 #include <sys/uadmin.h>
66 66 #include <sys/panic.h>
67 67 #include <sys/debug.h>
68 68 #include <sys/archsystm.h>
69 69 #include <sys/trap.h>
70 70 #include <sys/machsystm.h>
71 71 #include <sys/sysmacros.h>
72 72 #include <sys/cpuvar.h>
73 73 #include <sys/rm_platter.h>
74 74 #include <sys/privregs.h>
75 75 #include <sys/note.h>
76 76 #include <sys/pci_intr_lib.h>
77 77 #include <sys/spl.h>
78 78 #include <sys/clock.h>
79 79 #include <sys/cyclic.h>
80 80 #include <sys/dditypes.h>
81 81 #include <sys/sunddi.h>
82 82 #include <sys/x_call.h>
83 83 #include <sys/reboot.h>
84 84 #include <sys/hpet.h>
85 85 #include <sys/apic_common.h>
86 86 #include <sys/apic_timer.h>
87 87
88 88 /*
89 89 * Local Function Prototypes
90 90 */
91 91 static void apic_init_intr(void);
92 92
93 93 /*
94 94 * standard MP entries
95 95 */
96 96 static int apic_probe(void);
97 97 static int apic_getclkirq(int ipl);
98 98 static void apic_init(void);
99 99 static void apic_picinit(void);
100 100 static int apic_post_cpu_start(void);
101 101 static int apic_intr_enter(int ipl, int *vect);
102 102 static void apic_setspl(int ipl);
103 103 static void x2apic_setspl(int ipl);
104 104 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
105 105 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
106 106 static int apic_disable_intr(processorid_t cpun);
107 107 static void apic_enable_intr(processorid_t cpun);
108 108 static int apic_get_ipivect(int ipl, int type);
109 109 static void apic_post_cyclic_setup(void *arg);
110 110
111 111 /*
112 112 * The following vector assignments influence the value of ipltopri and
113 113 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
114 114 * idle to 0 and IPL 0 to 0xf to differentiate idle in case
115 115 * we care to do so in future. Note some IPLs which are rarely used
116 116 * will share the vector ranges and heavily used IPLs (5 and 6) have
117 117 * a wide range.
118 118 *
119 119 * This array is used to initialize apic_ipls[] (in apic_init()).
120 120 *
121 121 * IPL Vector range. as passed to intr_enter
122 122 * 0 none.
123 123 * 1,2,3 0x20-0x2f 0x0-0xf
124 124 * 4 0x30-0x3f 0x10-0x1f
125 125 * 5 0x40-0x5f 0x20-0x3f
126 126 * 6 0x60-0x7f 0x40-0x5f
127 127 * 7,8,9 0x80-0x8f 0x60-0x6f
128 128 * 10 0x90-0x9f 0x70-0x7f
129 129 * 11 0xa0-0xaf 0x80-0x8f
130 130 * ... ...
131 131 * 15 0xe0-0xef 0xc0-0xcf
132 132 * 15 0xf0-0xff 0xd0-0xdf
133 133 */
134 134 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
135 135 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
136 136 };
137 137 /*
138 138 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
139 139 * NOTE that this is vector as passed into intr_enter which is
140 140 * programmed vector - 0x20 (APIC_BASE_VECT)
141 141 */
142 142
143 143 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
144 144 /* The taskpri to be programmed into apic to mask given ipl */
145 145
146 146 /*
147 147 * Correlation of the hardware vector to the IPL in use, initialized
148 148 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
149 149 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
150 150 * connected to errata-stricken IOAPICs
151 151 */
152 152 uchar_t apic_ipls[APIC_AVAIL_VECTOR];
153 153
154 154 /*
155 155 * Patchable global variables.
156 156 */
157 157 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
158 158 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
159 159
160 160 /*
161 161 * Local static data
162 162 */
163 163 static struct psm_ops apic_ops = {
164 164 apic_probe,
165 165
166 166 apic_init,
167 167 apic_picinit,
168 168 apic_intr_enter,
169 169 apic_intr_exit,
170 170 apic_setspl,
171 171 apic_addspl,
172 172 apic_delspl,
173 173 apic_disable_intr,
174 174 apic_enable_intr,
175 175 (int (*)(int))NULL, /* psm_softlvl_to_irq */
176 176 (void (*)(int))NULL, /* psm_set_softintr */
177 177
178 178 apic_set_idlecpu,
179 179 apic_unset_idlecpu,
180 180
181 181 apic_clkinit,
182 182 apic_getclkirq,
183 183 (void (*)(void))NULL, /* psm_hrtimeinit */
184 184 apic_gethrtime,
185 185
186 186 apic_get_next_processorid,
187 187 apic_cpu_start,
188 188 apic_post_cpu_start,
189 189 apic_shutdown,
190 190 apic_get_ipivect,
191 191 apic_send_ipi,
192 192
193 193 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
194 194 (void (*)(int, char *))NULL, /* psm_notify_error */
195 195 (void (*)(int))NULL, /* psm_notify_func */
196 196 apic_timer_reprogram,
197 197 apic_timer_enable,
198 198 apic_timer_disable,
199 199 apic_post_cyclic_setup,
200 200 apic_preshutdown,
201 201 apic_intr_ops, /* Advanced DDI Interrupt framework */
202 202 apic_state, /* save, restore apic state for S3 */
203 203 apic_cpu_ops, /* CPU control interface. */
204 204 };
205 205
206 206 struct psm_ops *psmops = &apic_ops;
207 207
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207 lines elided |
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208 208 static struct psm_info apic_psm_info = {
209 209 PSM_INFO_VER01_7, /* version */
210 210 PSM_OWN_EXCLUSIVE, /* ownership */
211 211 (struct psm_ops *)&apic_ops, /* operation */
212 212 APIC_PCPLUSMP_NAME, /* machine name */
213 213 "pcplusmp v1.4 compatible",
214 214 };
215 215
216 216 static void *apic_hdlp;
217 217
218 -/*
219 - * apic_let_idle_redistribute can have the following values:
220 - * 0 - If clock decremented it from 1 to 0, clock has to call redistribute.
221 - * apic_redistribute_lock prevents multiple idle cpus from redistributing
222 - */
223 -int apic_num_idle_redistributions = 0;
224 -static int apic_let_idle_redistribute = 0;
225 -
226 218 /* to gather intr data and redistribute */
227 219 static void apic_redistribute_compute(void);
228 220
229 221 /*
230 222 * This is the loadable module wrapper
231 223 */
232 224
233 225 int
234 226 _init(void)
235 227 {
236 228 if (apic_coarse_hrtime)
237 229 apic_ops.psm_gethrtime = &apic_gettime;
238 230 return (psm_mod_init(&apic_hdlp, &apic_psm_info));
239 231 }
240 232
241 233 int
242 234 _fini(void)
243 235 {
244 236 return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
245 237 }
246 238
247 239 int
248 240 _info(struct modinfo *modinfop)
249 241 {
250 242 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
251 243 }
252 244
253 245 static int
254 246 apic_probe(void)
255 247 {
256 248 /* check if apix is initialized */
257 249 if (apix_enable && apix_loaded())
258 250 return (PSM_FAILURE);
259 251 else
260 252 apix_enable = 0; /* continue using pcplusmp PSM */
261 253
262 254 return (apic_probe_common(apic_psm_info.p_mach_idstring));
263 255 }
264 256
265 257 static uchar_t
266 258 apic_xlate_vector_by_irq(uchar_t irq)
267 259 {
268 260 if (apic_irq_table[irq] == NULL)
269 261 return (0);
270 262
271 263 return (apic_irq_table[irq]->airq_vector);
272 264 }
273 265
274 266 void
275 267 apic_init(void)
276 268 {
277 269 int i;
278 270 int j = 1;
279 271
280 272 psm_get_ioapicid = apic_get_ioapicid;
281 273 psm_get_localapicid = apic_get_localapicid;
282 274 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
283 275
284 276 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
285 277 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
286 278 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
287 279 (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
288 280 /* get to highest vector at the same ipl */
289 281 continue;
290 282 for (; j <= apic_vectortoipl[i]; j++) {
291 283 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
292 284 APIC_BASE_VECT;
293 285 }
294 286 }
295 287 for (; j < MAXIPL + 1; j++)
296 288 /* fill up any empty ipltopri slots */
297 289 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
298 290 apic_init_common();
299 291
300 292 #if !defined(__amd64)
301 293 if (cpuid_have_cr8access(CPU))
302 294 apic_have_32bit_cr8 = 1;
303 295 #endif
304 296 }
305 297
306 298 static void
307 299 apic_init_intr(void)
308 300 {
309 301 processorid_t cpun = psm_get_cpu_id();
310 302 uint_t nlvt;
311 303 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
312 304
313 305 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
314 306
315 307 if (apic_mode == LOCAL_APIC) {
316 308 /*
317 309 * We are running APIC in MMIO mode.
318 310 */
319 311 if (apic_flat_model) {
320 312 apic_reg_ops->apic_write(APIC_FORMAT_REG,
321 313 APIC_FLAT_MODEL);
322 314 } else {
323 315 apic_reg_ops->apic_write(APIC_FORMAT_REG,
324 316 APIC_CLUSTER_MODEL);
325 317 }
326 318
327 319 apic_reg_ops->apic_write(APIC_DEST_REG,
328 320 AV_HIGH_ORDER >> cpun);
329 321 }
330 322
331 323 if (apic_directed_EOI_supported()) {
332 324 /*
333 325 * Setting the 12th bit in the Spurious Interrupt Vector
334 326 * Register suppresses broadcast EOIs generated by the local
335 327 * APIC. The suppression of broadcast EOIs happens only when
336 328 * interrupts are level-triggered.
337 329 */
338 330 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
339 331 }
340 332
341 333 /* need to enable APIC before unmasking NMI */
342 334 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
343 335
344 336 /*
345 337 * Presence of an invalid vector with delivery mode AV_FIXED can
346 338 * cause an error interrupt, even if the entry is masked...so
347 339 * write a valid vector to LVT entries along with the mask bit
348 340 */
349 341
350 342 /* All APICs have timer and LINT0/1 */
351 343 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
352 344 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
353 345 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
354 346
355 347 /*
356 348 * On integrated APICs, the number of LVT entries is
357 349 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
358 350 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
359 351 */
360 352
361 353 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
362 354 nlvt = 3;
363 355 } else {
364 356 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
365 357 0xFF) + 1;
366 358 }
367 359
368 360 if (nlvt >= 5) {
369 361 /* Enable performance counter overflow interrupt */
370 362
371 363 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
372 364 apic_enable_cpcovf_intr = 0;
373 365 if (apic_enable_cpcovf_intr) {
374 366 if (apic_cpcovf_vect == 0) {
375 367 int ipl = APIC_PCINT_IPL;
376 368 int irq = apic_get_ipivect(ipl, -1);
377 369
378 370 ASSERT(irq != -1);
379 371 apic_cpcovf_vect =
380 372 apic_irq_table[irq]->airq_vector;
381 373 ASSERT(apic_cpcovf_vect);
382 374 (void) add_avintr(NULL, ipl,
383 375 (avfunc)kcpc_hw_overflow_intr,
384 376 "apic pcint", irq, NULL, NULL, NULL, NULL);
385 377 kcpc_hw_overflow_intr_installed = 1;
386 378 kcpc_hw_enable_cpc_intr =
387 379 apic_cpcovf_mask_clear;
388 380 }
389 381 apic_reg_ops->apic_write(APIC_PCINT_VECT,
390 382 apic_cpcovf_vect);
391 383 }
392 384 }
393 385
394 386 if (nlvt >= 6) {
395 387 /* Only mask TM intr if the BIOS apparently doesn't use it */
396 388
397 389 uint32_t lvtval;
398 390
399 391 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
400 392 if (((lvtval & AV_MASK) == AV_MASK) ||
401 393 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
402 394 apic_reg_ops->apic_write(APIC_THERM_VECT,
403 395 AV_MASK|APIC_RESV_IRQ);
404 396 }
405 397 }
406 398
407 399 /* Enable error interrupt */
408 400
409 401 if (nlvt >= 4 && apic_enable_error_intr) {
410 402 if (apic_errvect == 0) {
411 403 int ipl = 0xf; /* get highest priority intr */
412 404 int irq = apic_get_ipivect(ipl, -1);
413 405
414 406 ASSERT(irq != -1);
415 407 apic_errvect = apic_irq_table[irq]->airq_vector;
416 408 ASSERT(apic_errvect);
417 409 /*
418 410 * Not PSMI compliant, but we are going to merge
419 411 * with ON anyway
420 412 */
421 413 (void) add_avintr((void *)NULL, ipl,
422 414 (avfunc)apic_error_intr, "apic error intr",
423 415 irq, NULL, NULL, NULL, NULL);
424 416 }
425 417 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
426 418 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
427 419 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
428 420 }
429 421
430 422 /* Enable CMCI interrupt */
431 423 if (cmi_enable_cmci) {
432 424
433 425 mutex_enter(&cmci_cpu_setup_lock);
434 426 if (cmci_cpu_setup_registered == 0) {
435 427 mutex_enter(&cpu_lock);
436 428 register_cpu_setup_func(cmci_cpu_setup, NULL);
437 429 mutex_exit(&cpu_lock);
438 430 cmci_cpu_setup_registered = 1;
439 431 }
440 432 mutex_exit(&cmci_cpu_setup_lock);
441 433
442 434 if (apic_cmci_vect == 0) {
443 435 int ipl = 0x2;
444 436 int irq = apic_get_ipivect(ipl, -1);
445 437
446 438 ASSERT(irq != -1);
447 439 apic_cmci_vect = apic_irq_table[irq]->airq_vector;
448 440 ASSERT(apic_cmci_vect);
449 441
450 442 (void) add_avintr(NULL, ipl,
451 443 (avfunc)cmi_cmci_trap,
452 444 "apic cmci intr", irq, NULL, NULL, NULL, NULL);
453 445 }
454 446 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect);
455 447 }
456 448 }
457 449
458 450 static void
459 451 apic_picinit(void)
460 452 {
461 453 int i, j;
462 454 uint_t isr;
463 455
464 456 /*
465 457 * Initialize and enable interrupt remapping before apic
466 458 * hardware initialization
467 459 */
468 460 apic_intrmap_init(apic_mode);
469 461
470 462 /*
471 463 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
472 464 * bit on without clearing it with EOI. Since softint
473 465 * uses vector 0x20 to interrupt itself, so softint will
474 466 * not work on this machine. In order to fix this problem
475 467 * a check is made to verify all the isr bits are clear.
476 468 * If not, EOIs are issued to clear the bits.
477 469 */
478 470 for (i = 7; i >= 1; i--) {
479 471 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
480 472 if (isr != 0)
481 473 for (j = 0; ((j < 32) && (isr != 0)); j++)
482 474 if (isr & (1 << j)) {
483 475 apic_reg_ops->apic_write(
484 476 APIC_EOI_REG, 0);
485 477 isr &= ~(1 << j);
486 478 apic_error |= APIC_ERR_BOOT_EOI;
487 479 }
488 480 }
489 481
490 482 /* set a flag so we know we have run apic_picinit() */
491 483 apic_picinit_called = 1;
492 484 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
493 485 LOCK_INIT_CLEAR(&apic_ioapic_lock);
494 486 LOCK_INIT_CLEAR(&apic_error_lock);
495 487 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
496 488
497 489 picsetup(); /* initialise the 8259 */
498 490
499 491 /* add nmi handler - least priority nmi handler */
500 492 LOCK_INIT_CLEAR(&apic_nmi_lock);
501 493
502 494 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
503 495 "pcplusmp NMI handler", (caddr_t)NULL))
504 496 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
505 497
506 498 /*
507 499 * Check for directed-EOI capability in the local APIC.
508 500 */
509 501 if (apic_directed_EOI_supported() == 1) {
510 502 apic_set_directed_EOI_handler();
511 503 }
512 504
513 505 apic_init_intr();
514 506
515 507 /* enable apic mode if imcr present */
516 508 if (apic_imcrp) {
517 509 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
518 510 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
519 511 }
520 512
521 513 ioapic_init_intr(IOAPIC_MASK);
522 514 }
523 515
524 516 #ifdef DEBUG
525 517 void
526 518 apic_break(void)
527 519 {
528 520 }
529 521 #endif /* DEBUG */
530 522
531 523 /*
532 524 * platform_intr_enter
533 525 *
534 526 * Called at the beginning of the interrupt service routine to
535 527 * mask all level equal to and below the interrupt priority
536 528 * of the interrupting vector. An EOI should be given to
537 529 * the interrupt controller to enable other HW interrupts.
538 530 *
539 531 * Return -1 for spurious interrupts
540 532 *
541 533 */
542 534 /*ARGSUSED*/
543 535 static int
544 536 apic_intr_enter(int ipl, int *vectorp)
545 537 {
546 538 uchar_t vector;
547 539 int nipl;
548 540 int irq;
549 541 ulong_t iflag;
550 542 apic_cpus_info_t *cpu_infop;
551 543
552 544 /*
553 545 * The real vector delivered is (*vectorp + 0x20), but our caller
554 546 * subtracts 0x20 from the vector before passing it to us.
555 547 * (That's why APIC_BASE_VECT is 0x20.)
556 548 */
557 549 vector = (uchar_t)*vectorp;
558 550
559 551 /* if interrupted by the clock, increment apic_nsec_since_boot */
560 552 if (vector == apic_clkvect) {
561 553 if (!apic_oneshot) {
562 554 /* NOTE: this is not MT aware */
563 555 apic_hrtime_stamp++;
564 556 apic_nsec_since_boot += apic_nsec_per_intr;
565 557 apic_hrtime_stamp++;
566 558 last_count_read = apic_hertz_count;
567 559 apic_redistribute_compute();
568 560 }
569 561
570 562 /* We will avoid all the book keeping overhead for clock */
571 563 nipl = apic_ipls[vector];
572 564
573 565 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
574 566
575 567 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
576 568 apic_reg_ops->apic_send_eoi(0);
577 569
578 570 return (nipl);
579 571 }
580 572
581 573 cpu_infop = &apic_cpus[psm_get_cpu_id()];
582 574
583 575 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
584 576 cpu_infop->aci_spur_cnt++;
585 577 return (APIC_INT_SPURIOUS);
586 578 }
587 579
588 580 /* Check if the vector we got is really what we need */
589 581 if (apic_revector_pending) {
590 582 /*
591 583 * Disable interrupts for the duration of
592 584 * the vector translation to prevent a self-race for
593 585 * the apic_revector_lock. This cannot be done
594 586 * in apic_xlate_vector because it is recursive and
595 587 * we want the vector translation to be atomic with
596 588 * respect to other (higher-priority) interrupts.
597 589 */
598 590 iflag = intr_clear();
599 591 vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
600 592 APIC_BASE_VECT;
601 593 intr_restore(iflag);
602 594 }
603 595
604 596 nipl = apic_ipls[vector];
605 597 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
606 598
607 599 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
608 600
609 601 cpu_infop->aci_current[nipl] = (uchar_t)irq;
610 602 cpu_infop->aci_curipl = (uchar_t)nipl;
611 603 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
612 604
613 605 /*
614 606 * apic_level_intr could have been assimilated into the irq struct.
615 607 * but, having it as a character array is more efficient in terms of
616 608 * cache usage. So, we leave it as is.
617 609 */
618 610 if (!apic_level_intr[irq]) {
619 611 apic_reg_ops->apic_send_eoi(0);
620 612 }
621 613
622 614 #ifdef DEBUG
623 615 APIC_DEBUG_BUF_PUT(vector);
624 616 APIC_DEBUG_BUF_PUT(irq);
625 617 APIC_DEBUG_BUF_PUT(nipl);
626 618 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
627 619 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
628 620 drv_usecwait(apic_stretch_interrupts);
629 621
630 622 if (apic_break_on_cpu == psm_get_cpu_id())
631 623 apic_break();
632 624 #endif /* DEBUG */
633 625 return (nipl);
634 626 }
635 627
636 628 /*
637 629 * This macro is a common code used by MMIO local apic and X2APIC
638 630 * local apic.
639 631 */
640 632 #define APIC_INTR_EXIT() \
641 633 { \
642 634 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \
643 635 if (apic_level_intr[irq]) \
644 636 apic_reg_ops->apic_send_eoi(irq); \
645 637 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \
646 638 /* ISR above current pri could not be in progress */ \
647 639 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \
648 640 }
649 641
650 642 /*
651 643 * Any changes made to this function must also change X2APIC
652 644 * version of intr_exit.
653 645 */
654 646 void
655 647 apic_intr_exit(int prev_ipl, int irq)
656 648 {
657 649 apic_cpus_info_t *cpu_infop;
658 650
659 651 apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]);
660 652
661 653 APIC_INTR_EXIT();
662 654 }
663 655
664 656 /*
665 657 * Same as apic_intr_exit() except it uses MSR rather than MMIO
666 658 * to access local apic registers.
667 659 */
668 660 void
669 661 x2apic_intr_exit(int prev_ipl, int irq)
670 662 {
671 663 apic_cpus_info_t *cpu_infop;
672 664
673 665 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]);
674 666 APIC_INTR_EXIT();
675 667 }
676 668
677 669 intr_exit_fn_t
678 670 psm_intr_exit_fn(void)
679 671 {
680 672 if (apic_mode == LOCAL_X2APIC)
681 673 return (x2apic_intr_exit);
682 674
683 675 return (apic_intr_exit);
684 676 }
685 677
686 678 /*
687 679 * Mask all interrupts below or equal to the given IPL.
688 680 * Any changes made to this function must also change X2APIC
689 681 * version of setspl.
690 682 */
691 683 static void
692 684 apic_setspl(int ipl)
693 685 {
694 686 apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]);
695 687
696 688 /* interrupts at ipl above this cannot be in progress */
697 689 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
698 690 /*
699 691 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
700 692 * have enough time to come in before the priority is raised again
701 693 * during the idle() loop.
702 694 */
703 695 if (apic_setspl_delay)
704 696 (void) apic_reg_ops->apic_get_pri();
705 697 }
706 698
707 699 /*
708 700 * X2APIC version of setspl.
709 701 * Mask all interrupts below or equal to the given IPL
710 702 */
711 703 static void
712 704 x2apic_setspl(int ipl)
713 705 {
714 706 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]);
715 707
716 708 /* interrupts at ipl above this cannot be in progress */
717 709 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
718 710 }
719 711
720 712 /*ARGSUSED*/
721 713 static int
722 714 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
723 715 {
724 716 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
725 717 }
726 718
727 719 static int
728 720 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
729 721 {
730 722 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
731 723 }
732 724
733 725 static int
734 726 apic_post_cpu_start(void)
735 727 {
736 728 int cpun;
737 729 static int cpus_started = 1;
738 730
739 731 /* We know this CPU + BSP started successfully. */
740 732 cpus_started++;
741 733
742 734 /*
743 735 * On BSP we would have enabled X2APIC, if supported by processor,
744 736 * in acpi_probe(), but on AP we do it here.
745 737 *
746 738 * We enable X2APIC mode only if BSP is running in X2APIC & the
747 739 * local APIC mode of the current CPU is MMIO (xAPIC).
748 740 */
749 741 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
750 742 apic_local_mode() == LOCAL_APIC) {
751 743 apic_enable_x2apic();
752 744 }
753 745
754 746 /*
755 747 * Switch back to x2apic IPI sending method for performance when target
756 748 * CPU has entered x2apic mode.
757 749 */
758 750 if (apic_mode == LOCAL_X2APIC) {
759 751 apic_switch_ipi_callback(B_FALSE);
760 752 }
761 753
762 754 splx(ipltospl(LOCK_LEVEL));
763 755 apic_init_intr();
764 756
765 757 /*
766 758 * since some systems don't enable the internal cache on the non-boot
767 759 * cpus, so we have to enable them here
768 760 */
769 761 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
770 762
771 763 #ifdef DEBUG
772 764 APIC_AV_PENDING_SET();
773 765 #else
774 766 if (apic_mode == LOCAL_APIC)
775 767 APIC_AV_PENDING_SET();
776 768 #endif /* DEBUG */
777 769
778 770 /*
779 771 * We may be booting, or resuming from suspend; aci_status will
780 772 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
781 773 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
782 774 */
783 775 cpun = psm_get_cpu_id();
784 776 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
785 777
786 778 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
787 779 return (PSM_SUCCESS);
788 780 }
789 781
790 782 /*
↓ open down ↓ |
555 lines elided |
↑ open up ↑ |
791 783 * type == -1 indicates it is an internal request. Do not change
792 784 * resv_vector for these requests
793 785 */
794 786 static int
795 787 apic_get_ipivect(int ipl, int type)
796 788 {
797 789 uchar_t vector;
798 790 int irq;
799 791
800 792 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
801 - if (vector = apic_allocate_vector(ipl, irq, 1)) {
793 + if ((vector = apic_allocate_vector(ipl, irq, 1))) {
802 794 apic_irq_table[irq]->airq_mps_intr_index =
803 795 RESERVE_INDEX;
804 796 apic_irq_table[irq]->airq_vector = vector;
805 797 if (type != -1) {
806 798 apic_resv_vector[ipl] = vector;
807 799 }
808 800 return (irq);
809 801 }
810 802 }
811 803 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
812 804 return (-1); /* shouldn't happen */
813 805 }
814 806
815 807 static int
816 808 apic_getclkirq(int ipl)
817 809 {
818 810 int irq;
819 811
820 812 if ((irq = apic_get_ipivect(ipl, -1)) == -1)
821 813 return (-1);
822 814 /*
823 815 * Note the vector in apic_clkvect for per clock handling.
824 816 */
825 817 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
826 818 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
827 819 apic_clkvect));
828 820 return (irq);
829 821 }
830 822
831 823 /*
832 824 * Try and disable all interrupts. We just assign interrupts to other
833 825 * processors based on policy. If any were bound by user request, we
834 826 * let them continue and return failure. We do not bother to check
835 827 * for cache affinity while rebinding.
836 828 */
837 829
838 830 static int
839 831 apic_disable_intr(processorid_t cpun)
840 832 {
841 833 int bind_cpu = 0, i, hardbound = 0;
842 834 apic_irq_t *irq_ptr;
843 835 ulong_t iflag;
844 836
845 837 iflag = intr_clear();
846 838 lock_set(&apic_ioapic_lock);
847 839
848 840 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
849 841 if (apic_reprogram_info[i].done == B_FALSE) {
850 842 if (apic_reprogram_info[i].bindcpu == cpun) {
851 843 /*
852 844 * CPU is busy -- it's the target of
853 845 * a pending reprogramming attempt
854 846 */
855 847 lock_clear(&apic_ioapic_lock);
856 848 intr_restore(iflag);
857 849 return (PSM_FAILURE);
858 850 }
859 851 }
860 852 }
861 853
862 854 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
863 855
864 856 apic_cpus[cpun].aci_curipl = 0;
865 857
866 858 i = apic_min_device_irq;
867 859 for (; i <= apic_max_device_irq; i++) {
868 860 /*
869 861 * If there are bound interrupts on this cpu, then
870 862 * rebind them to other processors.
871 863 */
872 864 if ((irq_ptr = apic_irq_table[i]) != NULL) {
873 865 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
874 866 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
875 867 (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
876 868
877 869 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
878 870 hardbound = 1;
879 871 continue;
880 872 }
881 873
882 874 if (irq_ptr->airq_temp_cpu == cpun) {
883 875 do {
884 876 bind_cpu =
885 877 apic_find_cpu(APIC_CPU_INTR_ENABLE);
886 878 } while (apic_rebind_all(irq_ptr, bind_cpu));
887 879 }
888 880 }
889 881 }
890 882
891 883 lock_clear(&apic_ioapic_lock);
892 884 intr_restore(iflag);
893 885
894 886 if (hardbound) {
895 887 cmn_err(CE_WARN, "Could not disable interrupts on %d"
896 888 "due to user bound interrupts", cpun);
897 889 return (PSM_FAILURE);
898 890 }
899 891 else
900 892 return (PSM_SUCCESS);
901 893 }
902 894
903 895 /*
904 896 * Bind interrupts to the CPU's local APIC.
905 897 * Interrupts should not be bound to a CPU's local APIC until the CPU
906 898 * is ready to receive interrupts.
907 899 */
908 900 static void
909 901 apic_enable_intr(processorid_t cpun)
910 902 {
911 903 int i;
912 904 apic_irq_t *irq_ptr;
913 905 ulong_t iflag;
914 906
915 907 iflag = intr_clear();
916 908 lock_set(&apic_ioapic_lock);
917 909
918 910 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
919 911
920 912 i = apic_min_device_irq;
921 913 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
922 914 if ((irq_ptr = apic_irq_table[i]) != NULL) {
923 915 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
924 916 (void) apic_rebind_all(irq_ptr,
925 917 irq_ptr->airq_cpu);
926 918 }
927 919 }
928 920 }
929 921
930 922 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
931 923 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
932 924
933 925 lock_clear(&apic_ioapic_lock);
934 926 intr_restore(iflag);
935 927 }
936 928
937 929 /*
938 930 * If this module needs a periodic handler for the interrupt distribution, it
939 931 * can be added here. The argument to the periodic handler is not currently
940 932 * used, but is reserved for future.
941 933 */
942 934 static void
943 935 apic_post_cyclic_setup(void *arg)
944 936 {
945 937 _NOTE(ARGUNUSED(arg))
946 938
947 939 cyc_handler_t cyh;
948 940 cyc_time_t cyt;
949 941
950 942 /* cpu_lock is held */
951 943 /* set up a periodic handler for intr redistribution */
952 944
953 945 /*
954 946 * In peridoc mode intr redistribution processing is done in
955 947 * apic_intr_enter during clk intr processing
956 948 */
957 949 if (!apic_oneshot)
958 950 return;
959 951
960 952 /*
961 953 * Register a periodical handler for the redistribution processing.
962 954 * Though we would generally prefer to use the DDI interface for
963 955 * periodic handler invocation, ddi_periodic_add(9F), we are
964 956 * unfortunately already holding cpu_lock, which ddi_periodic_add will
965 957 * attempt to take for us. Thus, we add our own cyclic directly:
966 958 */
967 959 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
968 960 cyh.cyh_arg = NULL;
969 961 cyh.cyh_level = CY_LOW_LEVEL;
970 962
971 963 cyt.cyt_when = 0;
972 964 cyt.cyt_interval = apic_redistribute_sample_interval;
973 965
974 966 apic_cyclic_id = cyclic_add(&cyh, &cyt);
975 967 }
976 968
977 969 static void
978 970 apic_redistribute_compute(void)
979 971 {
980 972 int i, j, max_busy;
981 973
982 974 if (apic_enable_dynamic_migration) {
983 975 if (++apic_nticks == apic_sample_factor_redistribution) {
984 976 /*
985 977 * Time to call apic_intr_redistribute().
986 978 * reset apic_nticks. This will cause max_busy
987 979 * to be calculated below and if it is more than
988 980 * apic_int_busy, we will do the whole thing
989 981 */
990 982 apic_nticks = 0;
991 983 }
992 984 max_busy = 0;
993 985 for (i = 0; i < apic_nproc; i++) {
994 986 if (!apic_cpu_in_range(i))
995 987 continue;
996 988
997 989 /*
998 990 * Check if curipl is non zero & if ISR is in
999 991 * progress
1000 992 */
1001 993 if (((j = apic_cpus[i].aci_curipl) != 0) &&
1002 994 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1003 995
1004 996 int irq;
1005 997 apic_cpus[i].aci_busy++;
1006 998 irq = apic_cpus[i].aci_current[j];
1007 999 apic_irq_table[irq]->airq_busy++;
1008 1000 }
1009 1001
1010 1002 if (!apic_nticks &&
1011 1003 (apic_cpus[i].aci_busy > max_busy))
1012 1004 max_busy = apic_cpus[i].aci_busy;
1013 1005 }
1014 1006 if (!apic_nticks) {
1015 1007 if (max_busy > apic_int_busy_mark) {
1016 1008 /*
1017 1009 * We could make the following check be
1018 1010 * skipped > 1 in which case, we get a
1019 1011 * redistribution at half the busy mark (due to
1020 1012 * double interval). Need to be able to collect
1021 1013 * more empirical data to decide if that is a
1022 1014 * good strategy. Punt for now.
1023 1015 */
1024 1016 if (apic_skipped_redistribute) {
1025 1017 apic_cleanup_busy();
1026 1018 apic_skipped_redistribute = 0;
1027 1019 } else {
1028 1020 apic_intr_redistribute();
1029 1021 }
1030 1022 } else
1031 1023 apic_skipped_redistribute++;
1032 1024 }
1033 1025 }
1034 1026 }
1035 1027
1036 1028
1037 1029 /*
1038 1030 * The following functions are in the platform specific file so that they
1039 1031 * can be different functions depending on whether we are running on
1040 1032 * bare metal or a hypervisor.
1041 1033 */
1042 1034
1043 1035 /*
1044 1036 * Check to make sure there are enough irq slots
1045 1037 */
1046 1038 int
1047 1039 apic_check_free_irqs(int count)
1048 1040 {
1049 1041 int i, avail;
1050 1042
1051 1043 avail = 0;
1052 1044 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1053 1045 if ((apic_irq_table[i] == NULL) ||
1054 1046 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
1055 1047 if (++avail >= count)
1056 1048 return (PSM_SUCCESS);
1057 1049 }
1058 1050 }
1059 1051 return (PSM_FAILURE);
1060 1052 }
1061 1053
1062 1054 /*
1063 1055 * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
1064 1056 */
1065 1057 int
1066 1058 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
1067 1059 int behavior)
1068 1060 {
1069 1061 int rcount, i;
1070 1062 uchar_t start, irqno;
1071 1063 uint32_t cpu;
1072 1064 major_t major;
1073 1065 apic_irq_t *irqptr;
1074 1066
1075 1067 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
1076 1068 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1077 1069 (void *)dip, inum, pri, count, behavior));
1078 1070
1079 1071 if (count > 1) {
1080 1072 if (behavior == DDI_INTR_ALLOC_STRICT &&
1081 1073 apic_multi_msi_enable == 0)
1082 1074 return (0);
1083 1075 if (apic_multi_msi_enable == 0)
1084 1076 count = 1;
1085 1077 }
1086 1078
1087 1079 if ((rcount = apic_navail_vector(dip, pri)) > count)
1088 1080 rcount = count;
1089 1081 else if (rcount == 0 || (rcount < count &&
1090 1082 behavior == DDI_INTR_ALLOC_STRICT))
1091 1083 return (0);
1092 1084
1093 1085 /* if not ISP2, then round it down */
1094 1086 if (!ISP2(rcount))
1095 1087 rcount = 1 << (highbit(rcount) - 1);
1096 1088
1097 1089 mutex_enter(&airq_mutex);
1098 1090
1099 1091 for (start = 0; rcount > 0; rcount >>= 1) {
1100 1092 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1101 1093 behavior == DDI_INTR_ALLOC_STRICT)
1102 1094 break;
1103 1095 }
1104 1096
1105 1097 if (start == 0) {
1106 1098 /* no vector available */
1107 1099 mutex_exit(&airq_mutex);
1108 1100 return (0);
1109 1101 }
1110 1102
1111 1103 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1112 1104 /* not enough free irq slots available */
1113 1105 mutex_exit(&airq_mutex);
1114 1106 return (0);
1115 1107 }
1116 1108
1117 1109 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1118 1110 for (i = 0; i < rcount; i++) {
1119 1111 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1120 1112 (uchar_t)-1) {
1121 1113 /*
1122 1114 * shouldn't happen because of the
1123 1115 * apic_check_free_irqs() check earlier
1124 1116 */
1125 1117 mutex_exit(&airq_mutex);
1126 1118 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1127 1119 "apic_allocate_irq failed\n"));
1128 1120 return (i);
1129 1121 }
1130 1122 apic_max_device_irq = max(irqno, apic_max_device_irq);
1131 1123 apic_min_device_irq = min(irqno, apic_min_device_irq);
1132 1124 irqptr = apic_irq_table[irqno];
1133 1125 #ifdef DEBUG
1134 1126 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1135 1127 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1136 1128 "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1137 1129 #endif
1138 1130 apic_vector_to_irq[start + i] = (uchar_t)irqno;
1139 1131
1140 1132 irqptr->airq_vector = (uchar_t)(start + i);
1141 1133 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1142 1134 irqptr->airq_intin_no = (uchar_t)rcount;
1143 1135 irqptr->airq_ipl = pri;
1144 1136 irqptr->airq_vector = start + i;
1145 1137 irqptr->airq_origirq = (uchar_t)(inum + i);
1146 1138 irqptr->airq_share_id = 0;
1147 1139 irqptr->airq_mps_intr_index = MSI_INDEX;
1148 1140 irqptr->airq_dip = dip;
1149 1141 irqptr->airq_major = major;
1150 1142 if (i == 0) /* they all bound to the same cpu */
1151 1143 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
1152 1144 0xff, 0xff);
1153 1145 else
1154 1146 irqptr->airq_cpu = cpu;
1155 1147 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1156 1148 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1157 1149 (void *)irqptr->airq_dip, irqptr->airq_vector,
1158 1150 irqptr->airq_origirq, pri));
1159 1151 }
1160 1152 mutex_exit(&airq_mutex);
1161 1153 return (rcount);
1162 1154 }
1163 1155
1164 1156 /*
1165 1157 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1166 1158 */
1167 1159 int
1168 1160 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1169 1161 int behavior)
1170 1162 {
1171 1163 int rcount, i;
1172 1164 major_t major;
1173 1165
1174 1166 mutex_enter(&airq_mutex);
1175 1167
1176 1168 if ((rcount = apic_navail_vector(dip, pri)) > count)
1177 1169 rcount = count;
1178 1170 else if (rcount == 0 || (rcount < count &&
1179 1171 behavior == DDI_INTR_ALLOC_STRICT)) {
1180 1172 rcount = 0;
1181 1173 goto out;
1182 1174 }
1183 1175
1184 1176 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1185 1177 /* not enough free irq slots available */
1186 1178 rcount = 0;
1187 1179 goto out;
1188 1180 }
1189 1181
1190 1182 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1191 1183 for (i = 0; i < rcount; i++) {
1192 1184 uchar_t vector, irqno;
1193 1185 apic_irq_t *irqptr;
1194 1186
1195 1187 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1196 1188 (uchar_t)-1) {
1197 1189 /*
1198 1190 * shouldn't happen because of the
1199 1191 * apic_check_free_irqs() check earlier
1200 1192 */
1201 1193 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1202 1194 "apic_allocate_irq failed\n"));
1203 1195 rcount = i;
1204 1196 goto out;
1205 1197 }
1206 1198 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1207 1199 /*
1208 1200 * shouldn't happen because of the
1209 1201 * apic_navail_vector() call earlier
1210 1202 */
1211 1203 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1212 1204 "apic_allocate_vector failed\n"));
1213 1205 rcount = i;
1214 1206 goto out;
1215 1207 }
1216 1208 apic_max_device_irq = max(irqno, apic_max_device_irq);
1217 1209 apic_min_device_irq = min(irqno, apic_min_device_irq);
1218 1210 irqptr = apic_irq_table[irqno];
1219 1211 irqptr->airq_vector = (uchar_t)vector;
1220 1212 irqptr->airq_ipl = pri;
1221 1213 irqptr->airq_origirq = (uchar_t)(inum + i);
1222 1214 irqptr->airq_share_id = 0;
1223 1215 irqptr->airq_mps_intr_index = MSIX_INDEX;
1224 1216 irqptr->airq_dip = dip;
1225 1217 irqptr->airq_major = major;
1226 1218 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1227 1219 }
1228 1220 out:
1229 1221 mutex_exit(&airq_mutex);
1230 1222 return (rcount);
1231 1223 }
1232 1224
1233 1225 /*
1234 1226 * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1235 1227 * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1236 1228 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1237 1229 * requests and allocated only when pri is set.
1238 1230 */
1239 1231 uchar_t
1240 1232 apic_allocate_vector(int ipl, int irq, int pri)
1241 1233 {
1242 1234 int lowest, highest, i;
1243 1235
1244 1236 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1245 1237 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1246 1238
1247 1239 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1248 1240 lowest -= APIC_VECTOR_PER_IPL;
1249 1241
1250 1242 #ifdef DEBUG
1251 1243 if (apic_restrict_vector) /* for testing shared interrupt logic */
1252 1244 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1253 1245 #endif /* DEBUG */
1254 1246 if (pri == 0)
1255 1247 highest -= APIC_HI_PRI_VECTS;
1256 1248
1257 1249 for (i = lowest; i <= highest; i++) {
1258 1250 if (APIC_CHECK_RESERVE_VECTORS(i))
1259 1251 continue;
1260 1252 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1261 1253 apic_vector_to_irq[i] = (uchar_t)irq;
1262 1254 return (i);
1263 1255 }
1264 1256 }
1265 1257
1266 1258 return (0);
1267 1259 }
1268 1260
1269 1261 /* Mark vector as not being used by any irq */
1270 1262 void
1271 1263 apic_free_vector(uchar_t vector)
1272 1264 {
1273 1265 apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1274 1266 }
1275 1267
1276 1268 /*
1277 1269 * Call rebind to do the actual programming.
1278 1270 * Must be called with interrupts disabled and apic_ioapic_lock held
1279 1271 * 'p' is polymorphic -- if this function is called to process a deferred
1280 1272 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1281 1273 * the irq pointer is retrieved. If not doing deferred reprogramming,
1282 1274 * p is of the type 'apic_irq_t *'.
1283 1275 *
1284 1276 * apic_ioapic_lock must be held across this call, as it protects apic_rebind
1285 1277 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1286 1278 * taken offline after a cpu is selected, but before apic_rebind is called to
1287 1279 * bind interrupts to it.
1288 1280 */
1289 1281 int
1290 1282 apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1291 1283 {
1292 1284 apic_irq_t *irqptr;
1293 1285 struct ioapic_reprogram_data *drep = NULL;
1294 1286 int rv;
1295 1287
1296 1288 if (deferred) {
1297 1289 drep = (struct ioapic_reprogram_data *)p;
1298 1290 ASSERT(drep != NULL);
1299 1291 irqptr = drep->irqp;
1300 1292 } else
1301 1293 irqptr = (apic_irq_t *)p;
1302 1294
1303 1295 ASSERT(irqptr != NULL);
1304 1296
1305 1297 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1306 1298 if (rv) {
1307 1299 /*
1308 1300 * CPU is not up or interrupts are disabled. Fall back to
1309 1301 * the first available CPU
1310 1302 */
1311 1303 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1312 1304 drep);
1313 1305 }
1314 1306
1315 1307 return (rv);
1316 1308 }
1317 1309
1318 1310
1319 1311 uchar_t
1320 1312 apic_modify_vector(uchar_t vector, int irq)
1321 1313 {
1322 1314 apic_vector_to_irq[vector] = (uchar_t)irq;
1323 1315 return (vector);
1324 1316 }
1325 1317
1326 1318 char *
1327 1319 apic_get_apic_type(void)
1328 1320 {
1329 1321 return (apic_psm_info.p_mach_idstring);
1330 1322 }
1331 1323
1332 1324 void
1333 1325 x2apic_update_psm(void)
1334 1326 {
1335 1327 struct psm_ops *pops = &apic_ops;
1336 1328
1337 1329 ASSERT(pops != NULL);
1338 1330
1339 1331 pops->psm_intr_exit = x2apic_intr_exit;
1340 1332 pops->psm_setspl = x2apic_setspl;
1341 1333
1342 1334 pops->psm_send_ipi = x2apic_send_ipi;
1343 1335 send_dirintf = pops->psm_send_ipi;
1344 1336
1345 1337 apic_mode = LOCAL_X2APIC;
1346 1338 apic_change_ops();
1347 1339 }
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