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6116 remove unused FMT_CPUID_*
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--- old/usr/src/uts/intel/sys/x86_archext.h
+++ new/usr/src/uts/intel/sys/x86_archext.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25 25 */
26 26 /*
27 27 * Copyright (c) 2010, Intel Corporation.
28 28 * All rights reserved.
29 29 */
30 30 /*
31 31 * Copyright (c) 2015, Joyent, Inc.
32 32 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
33 33 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
34 34 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
35 35 */
36 36
37 37 #ifndef _SYS_X86_ARCHEXT_H
38 38 #define _SYS_X86_ARCHEXT_H
39 39
40 40 #if !defined(_ASM)
41 41 #include <sys/regset.h>
42 42 #include <sys/processor.h>
43 43 #include <vm/seg_enum.h>
44 44 #include <vm/page.h>
45 45 #endif /* _ASM */
46 46
47 47 #ifdef __cplusplus
48 48 extern "C" {
49 49 #endif
50 50
51 51 /*
52 52 * cpuid instruction feature flags in %edx (standard function 1)
53 53 */
54 54
55 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
56 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
57 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
58 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
59 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
60 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
61 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
62 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
63 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
64 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
65 65 /* 0x400 - reserved */
66 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
67 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
68 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
69 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
70 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
71 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
72 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
73 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
74 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 75 /* 0x100000 - reserved */
76 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
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78 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
84 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87 87
88 -#define FMT_CPUID_INTC_EDX \
89 - "\20" \
90 - "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \
91 - "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \
92 - "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \
93 - "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
94 -
95 88 /*
96 89 * cpuid instruction feature flags in %ecx (standard function 1)
97 90 */
98 91
99 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
100 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
101 94 /* 0x00000004 - reserved */
102 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
103 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
104 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
105 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
106 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
107 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
108 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
109 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
110 103 /* 0x00000800 - reserved */
111 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
112 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
113 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
114 107 /* 0x00008000 - reserved */
115 108 /* 0x00010000 - reserved */
116 109 /* 0x00020000 - reserved */
117 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
118 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
119 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
120 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
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121 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
122 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
123 116 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
124 117 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
125 118 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
126 119 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
127 120 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
128 121 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
129 122 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
130 123
131 -#define FMT_CPUID_INTC_ECX \
132 - "\20" \
133 - "\37rdrand\36f16c\35avx\34osxsav\33xsave" \
134 - "\32aes" \
135 - "\30popcnt\27movbe\26x2apic\25sse4.2\24sse4.1\23dca" \
136 - "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \
137 - "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
138 -
139 124 /*
140 125 * cpuid instruction feature flags in %edx (extended function 0x80000001)
141 126 */
142 127
143 128 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
144 129 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
145 130 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
146 131 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
147 132 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
148 133 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
149 134 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
150 135 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
151 136 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
152 137 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
153 138 /* 0x00000400 - sysc on K6m6 */
154 139 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
155 140 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
156 141 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
157 142 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
158 143 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
159 144 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
160 145 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
161 146 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
162 147 /* 0x00040000 - reserved */
163 148 /* 0x00080000 - reserved */
164 149 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
165 150 /* 0x00200000 - reserved */
166 151 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
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167 152 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
168 153 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
169 154 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
170 155 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
171 156 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
172 157 /* 0x10000000 - reserved */
173 158 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
174 159 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
175 160 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
176 161
177 -#define FMT_CPUID_AMD_EDX \
178 - "\20" \
179 - "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \
180 - "\30mmx\27mmxext\25nx\22pse\21pat" \
181 - "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \
182 - "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
183 -
184 162 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
185 163 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
186 164 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
187 165 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
188 166 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
189 167 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
190 168 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
191 169 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
192 170 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
193 171 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
194 172 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
195 173 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
196 174 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
197 175 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
198 176 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
199 -
200 -#define FMT_CPUID_AMD_ECX \
201 - "\20" \
202 - "\22topoext" \
203 - "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \
204 - "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
205 177
206 178 /*
207 179 * Intel now seems to have claimed part of the "extended" function
208 180 * space that we previously for non-Intel implementors to use.
209 181 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
210 182 * is available in long mode i.e. what AMD indicate using bit 0.
211 183 * On the other hand, everything else is labelled as reserved.
212 184 */
213 185 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
214 186
215 187 /*
216 188 * Intel also uses cpuid leaf 7 to have additional instructions and features.
217 189 * Like some other leaves, but unlike the current ones we care about, it
218 190 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
219 191 * with the potential use of additional sub-leaves in the future, we now
220 192 * specifically label the EBX features with their leaf and sub-leaf.
221 193 */
222 194 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
223 195 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
224 196 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
225 197 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 Instrs */
226 198
227 199 #define P5_MCHADDR 0x0
228 200 #define P5_CESR 0x11
229 201 #define P5_CTR0 0x12
230 202 #define P5_CTR1 0x13
231 203
232 204 #define K5_MCHADDR 0x0
233 205 #define K5_MCHTYPE 0x01
234 206 #define K5_TSC 0x10
235 207 #define K5_TR12 0x12
236 208
237 209 #define REG_PAT 0x277
238 210
239 211 #define REG_MC0_CTL 0x400
240 212 #define REG_MC5_MISC 0x417
241 213 #define REG_PERFCTR0 0xc1
242 214 #define REG_PERFCTR1 0xc2
243 215
244 216 #define REG_PERFEVNT0 0x186
245 217 #define REG_PERFEVNT1 0x187
246 218
247 219 #define REG_TSC 0x10 /* timestamp counter */
248 220 #define REG_APIC_BASE_MSR 0x1b
249 221 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
250 222
251 223 #if !defined(__xpv)
252 224 /*
253 225 * AMD C1E
254 226 */
255 227 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
256 228 #define AMD_ACTONCMPHALT_SHIFT 27
257 229 #define AMD_ACTONCMPHALT_MASK 3
258 230 #endif
259 231
260 232 #define MSR_DEBUGCTL 0x1d9
261 233
262 234 #define DEBUGCTL_LBR 0x01
263 235 #define DEBUGCTL_BTF 0x02
264 236
265 237 /* Intel P6, AMD */
266 238 #define MSR_LBR_FROM 0x1db
267 239 #define MSR_LBR_TO 0x1dc
268 240 #define MSR_LEX_FROM 0x1dd
269 241 #define MSR_LEX_TO 0x1de
270 242
271 243 /* Intel P4 (pre-Prescott, non P4 M) */
272 244 #define MSR_P4_LBSTK_TOS 0x1da
273 245 #define MSR_P4_LBSTK_0 0x1db
274 246 #define MSR_P4_LBSTK_1 0x1dc
275 247 #define MSR_P4_LBSTK_2 0x1dd
276 248 #define MSR_P4_LBSTK_3 0x1de
277 249
278 250 /* Intel Pentium M */
279 251 #define MSR_P6M_LBSTK_TOS 0x1c9
280 252 #define MSR_P6M_LBSTK_0 0x040
281 253 #define MSR_P6M_LBSTK_1 0x041
282 254 #define MSR_P6M_LBSTK_2 0x042
283 255 #define MSR_P6M_LBSTK_3 0x043
284 256 #define MSR_P6M_LBSTK_4 0x044
285 257 #define MSR_P6M_LBSTK_5 0x045
286 258 #define MSR_P6M_LBSTK_6 0x046
287 259 #define MSR_P6M_LBSTK_7 0x047
288 260
289 261 /* Intel P4 (Prescott) */
290 262 #define MSR_PRP4_LBSTK_TOS 0x1da
291 263 #define MSR_PRP4_LBSTK_FROM_0 0x680
292 264 #define MSR_PRP4_LBSTK_FROM_1 0x681
293 265 #define MSR_PRP4_LBSTK_FROM_2 0x682
294 266 #define MSR_PRP4_LBSTK_FROM_3 0x683
295 267 #define MSR_PRP4_LBSTK_FROM_4 0x684
296 268 #define MSR_PRP4_LBSTK_FROM_5 0x685
297 269 #define MSR_PRP4_LBSTK_FROM_6 0x686
298 270 #define MSR_PRP4_LBSTK_FROM_7 0x687
299 271 #define MSR_PRP4_LBSTK_FROM_8 0x688
300 272 #define MSR_PRP4_LBSTK_FROM_9 0x689
301 273 #define MSR_PRP4_LBSTK_FROM_10 0x68a
302 274 #define MSR_PRP4_LBSTK_FROM_11 0x68b
303 275 #define MSR_PRP4_LBSTK_FROM_12 0x68c
304 276 #define MSR_PRP4_LBSTK_FROM_13 0x68d
305 277 #define MSR_PRP4_LBSTK_FROM_14 0x68e
306 278 #define MSR_PRP4_LBSTK_FROM_15 0x68f
307 279 #define MSR_PRP4_LBSTK_TO_0 0x6c0
308 280 #define MSR_PRP4_LBSTK_TO_1 0x6c1
309 281 #define MSR_PRP4_LBSTK_TO_2 0x6c2
310 282 #define MSR_PRP4_LBSTK_TO_3 0x6c3
311 283 #define MSR_PRP4_LBSTK_TO_4 0x6c4
312 284 #define MSR_PRP4_LBSTK_TO_5 0x6c5
313 285 #define MSR_PRP4_LBSTK_TO_6 0x6c6
314 286 #define MSR_PRP4_LBSTK_TO_7 0x6c7
315 287 #define MSR_PRP4_LBSTK_TO_8 0x6c8
316 288 #define MSR_PRP4_LBSTK_TO_9 0x6c9
317 289 #define MSR_PRP4_LBSTK_TO_10 0x6ca
318 290 #define MSR_PRP4_LBSTK_TO_11 0x6cb
319 291 #define MSR_PRP4_LBSTK_TO_12 0x6cc
320 292 #define MSR_PRP4_LBSTK_TO_13 0x6cd
321 293 #define MSR_PRP4_LBSTK_TO_14 0x6ce
322 294 #define MSR_PRP4_LBSTK_TO_15 0x6cf
323 295
324 296 #define MCI_CTL_VALUE 0xffffffff
325 297
326 298 #define MTRR_TYPE_UC 0
327 299 #define MTRR_TYPE_WC 1
328 300 #define MTRR_TYPE_WT 4
329 301 #define MTRR_TYPE_WP 5
330 302 #define MTRR_TYPE_WB 6
331 303 #define MTRR_TYPE_UC_ 7
332 304
333 305 /*
334 306 * For Solaris we set up the page attritubute table in the following way:
335 307 * PAT0 Write-Back
336 308 * PAT1 Write-Through
337 309 * PAT2 Unchacheable-
338 310 * PAT3 Uncacheable
339 311 * PAT4 Write-Back
340 312 * PAT5 Write-Through
341 313 * PAT6 Write-Combine
342 314 * PAT7 Uncacheable
343 315 * The only difference from h/w default is entry 6.
344 316 */
345 317 #define PAT_DEFAULT_ATTRIBUTE \
346 318 ((uint64_t)MTRR_TYPE_WB | \
347 319 ((uint64_t)MTRR_TYPE_WT << 8) | \
348 320 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
349 321 ((uint64_t)MTRR_TYPE_UC << 24) | \
350 322 ((uint64_t)MTRR_TYPE_WB << 32) | \
351 323 ((uint64_t)MTRR_TYPE_WT << 40) | \
352 324 ((uint64_t)MTRR_TYPE_WC << 48) | \
353 325 ((uint64_t)MTRR_TYPE_UC << 56))
354 326
355 327 #define X86FSET_LARGEPAGE 0
356 328 #define X86FSET_TSC 1
357 329 #define X86FSET_MSR 2
358 330 #define X86FSET_MTRR 3
359 331 #define X86FSET_PGE 4
360 332 #define X86FSET_DE 5
361 333 #define X86FSET_CMOV 6
362 334 #define X86FSET_MMX 7
363 335 #define X86FSET_MCA 8
364 336 #define X86FSET_PAE 9
365 337 #define X86FSET_CX8 10
366 338 #define X86FSET_PAT 11
367 339 #define X86FSET_SEP 12
368 340 #define X86FSET_SSE 13
369 341 #define X86FSET_SSE2 14
370 342 #define X86FSET_HTT 15
371 343 #define X86FSET_ASYSC 16
372 344 #define X86FSET_NX 17
373 345 #define X86FSET_SSE3 18
374 346 #define X86FSET_CX16 19
375 347 #define X86FSET_CMP 20
376 348 #define X86FSET_TSCP 21
377 349 #define X86FSET_MWAIT 22
378 350 #define X86FSET_SSE4A 23
379 351 #define X86FSET_CPUID 24
380 352 #define X86FSET_SSSE3 25
381 353 #define X86FSET_SSE4_1 26
382 354 #define X86FSET_SSE4_2 27
383 355 #define X86FSET_1GPG 28
384 356 #define X86FSET_CLFSH 29
385 357 #define X86FSET_64 30
386 358 #define X86FSET_AES 31
387 359 #define X86FSET_PCLMULQDQ 32
388 360 #define X86FSET_XSAVE 33
389 361 #define X86FSET_AVX 34
390 362 #define X86FSET_VMX 35
391 363 #define X86FSET_SVM 36
392 364 #define X86FSET_TOPOEXT 37
393 365 #define X86FSET_F16C 38
394 366 #define X86FSET_RDRAND 39
395 367 #define X86FSET_X2APIC 40
396 368 #define X86FSET_AVX2 41
397 369 #define X86FSET_BMI1 42
398 370 #define X86FSET_BMI2 43
399 371 #define X86FSET_FMA 44
400 372 #define X86FSET_SMEP 45
401 373
402 374 /*
403 375 * flags to patch tsc_read routine.
404 376 */
405 377 #define X86_NO_TSC 0x0
406 378 #define X86_HAVE_TSCP 0x1
407 379 #define X86_TSC_MFENCE 0x2
408 380 #define X86_TSC_LFENCE 0x4
409 381
410 382 /*
411 383 * Intel Deep C-State invariant TSC in leaf 0x80000007.
412 384 */
413 385 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
414 386
415 387 /*
416 388 * Intel Deep C-state always-running local APIC timer
417 389 */
418 390 #define CPUID_CSTATE_ARAT (0x4)
419 391
420 392 /*
421 393 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
422 394 */
423 395 #define CPUID_EPB_SUPPORT (1 << 3)
424 396
425 397 /*
426 398 * Intel TSC deadline timer
427 399 */
428 400 #define CPUID_DEADLINE_TSC (1 << 24)
429 401
430 402 /*
431 403 * x86_type is a legacy concept; this is supplanted
432 404 * for most purposes by x86_featureset; modern CPUs
433 405 * should be X86_TYPE_OTHER
434 406 */
435 407 #define X86_TYPE_OTHER 0
436 408 #define X86_TYPE_486 1
437 409 #define X86_TYPE_P5 2
438 410 #define X86_TYPE_P6 3
439 411 #define X86_TYPE_CYRIX_486 4
440 412 #define X86_TYPE_CYRIX_6x86L 5
441 413 #define X86_TYPE_CYRIX_6x86 6
442 414 #define X86_TYPE_CYRIX_GXm 7
443 415 #define X86_TYPE_CYRIX_6x86MX 8
444 416 #define X86_TYPE_CYRIX_MediaGX 9
445 417 #define X86_TYPE_CYRIX_MII 10
446 418 #define X86_TYPE_VIA_CYRIX_III 11
447 419 #define X86_TYPE_P4 12
448 420
449 421 /*
450 422 * x86_vendor allows us to select between
451 423 * implementation features and helps guide
452 424 * the interpretation of the cpuid instruction.
453 425 */
454 426 #define X86_VENDOR_Intel 0
455 427 #define X86_VENDORSTR_Intel "GenuineIntel"
456 428
457 429 #define X86_VENDOR_IntelClone 1
458 430
459 431 #define X86_VENDOR_AMD 2
460 432 #define X86_VENDORSTR_AMD "AuthenticAMD"
461 433
462 434 #define X86_VENDOR_Cyrix 3
463 435 #define X86_VENDORSTR_CYRIX "CyrixInstead"
464 436
465 437 #define X86_VENDOR_UMC 4
466 438 #define X86_VENDORSTR_UMC "UMC UMC UMC "
467 439
468 440 #define X86_VENDOR_NexGen 5
469 441 #define X86_VENDORSTR_NexGen "NexGenDriven"
470 442
471 443 #define X86_VENDOR_Centaur 6
472 444 #define X86_VENDORSTR_Centaur "CentaurHauls"
473 445
474 446 #define X86_VENDOR_Rise 7
475 447 #define X86_VENDORSTR_Rise "RiseRiseRise"
476 448
477 449 #define X86_VENDOR_SiS 8
478 450 #define X86_VENDORSTR_SiS "SiS SiS SiS "
479 451
480 452 #define X86_VENDOR_TM 9
481 453 #define X86_VENDORSTR_TM "GenuineTMx86"
482 454
483 455 #define X86_VENDOR_NSC 10
484 456 #define X86_VENDORSTR_NSC "Geode by NSC"
485 457
486 458 /*
487 459 * Vendor string max len + \0
488 460 */
489 461 #define X86_VENDOR_STRLEN 13
490 462
491 463 /*
492 464 * Some vendor/family/model/stepping ranges are commonly grouped under
493 465 * a single identifying banner by the vendor. The following encode
494 466 * that "revision" in a uint32_t with the 8 most significant bits
495 467 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
496 468 * family, and the remaining 16 typically forming a bitmask of revisions
497 469 * within that family with more significant bits indicating "later" revisions.
498 470 */
499 471
500 472 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
501 473 #define _X86_CHIPREV_VENDOR_SHIFT 24
502 474 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
503 475 #define _X86_CHIPREV_FAMILY_SHIFT 16
504 476 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
505 477
506 478 #define _X86_CHIPREV_VENDOR(x) \
507 479 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
508 480 #define _X86_CHIPREV_FAMILY(x) \
509 481 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
510 482 #define _X86_CHIPREV_REV(x) \
511 483 ((x) & _X86_CHIPREV_REV_MASK)
512 484
513 485 /* True if x matches in vendor and family and if x matches the given rev mask */
514 486 #define X86_CHIPREV_MATCH(x, mask) \
515 487 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
516 488 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
517 489 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
518 490
519 491 /* True if x matches in vendor and family, and rev is at least minx */
520 492 #define X86_CHIPREV_ATLEAST(x, minx) \
521 493 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
522 494 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
523 495 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
524 496
525 497 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
526 498 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
527 499 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
528 500
529 501 /* True if x matches in vendor, and family is at least minx */
530 502 #define X86_CHIPFAM_ATLEAST(x, minx) \
531 503 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
532 504 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
533 505
534 506 /* Revision default */
535 507 #define X86_CHIPREV_UNKNOWN 0x0
536 508
537 509 /*
538 510 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
539 511 * sufficiently different that we will distinguish them; in all other
540 512 * case we will identify the major revision.
541 513 */
542 514 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
543 515 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
544 516 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
545 517 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
546 518 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
547 519 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
548 520 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
549 521
550 522 /*
551 523 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
552 524 */
553 525 #define X86_CHIPREV_AMD_10_REV_A \
554 526 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
555 527 #define X86_CHIPREV_AMD_10_REV_B \
556 528 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
557 529 #define X86_CHIPREV_AMD_10_REV_C2 \
558 530 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
559 531 #define X86_CHIPREV_AMD_10_REV_C3 \
560 532 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
561 533 #define X86_CHIPREV_AMD_10_REV_D0 \
562 534 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
563 535 #define X86_CHIPREV_AMD_10_REV_D1 \
564 536 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
565 537 #define X86_CHIPREV_AMD_10_REV_E \
566 538 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
567 539
568 540 /*
569 541 * Definitions for AMD Family 0x11.
570 542 */
571 543 #define X86_CHIPREV_AMD_11_REV_B \
572 544 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
573 545
574 546 /*
575 547 * Definitions for AMD Family 0x12.
576 548 */
577 549 #define X86_CHIPREV_AMD_12_REV_B \
578 550 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
579 551
580 552 /*
581 553 * Definitions for AMD Family 0x14.
582 554 */
583 555 #define X86_CHIPREV_AMD_14_REV_B \
584 556 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
585 557 #define X86_CHIPREV_AMD_14_REV_C \
586 558 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
587 559
588 560 /*
589 561 * Definitions for AMD Family 0x15
590 562 */
591 563 #define X86_CHIPREV_AMD_15OR_REV_B2 \
592 564 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
593 565
594 566 #define X86_CHIPREV_AMD_15TN_REV_A1 \
595 567 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
596 568
597 569 /*
598 570 * Various socket/package types, extended as the need to distinguish
599 571 * a new type arises. The top 8 byte identfies the vendor and the
600 572 * remaining 24 bits describe 24 socket types.
601 573 */
602 574
603 575 #define _X86_SOCKET_VENDOR_SHIFT 24
604 576 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
605 577 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
606 578 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
607 579
608 580 #define _X86_SOCKET_MKVAL(vendor, bitval) \
609 581 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
610 582
611 583 #define X86_SOCKET_MATCH(s, mask) \
612 584 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
613 585 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
614 586
615 587 #define X86_SOCKET_UNKNOWN 0x0
616 588 /*
617 589 * AMD socket types
618 590 */
619 591 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
620 592 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
621 593 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
622 594 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
623 595 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
624 596 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
625 597 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
626 598 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
627 599 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
628 600 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
629 601 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
630 602 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
631 603 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
632 604 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
633 605 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000)
634 606 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000)
635 607 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000)
636 608 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000)
637 609 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000)
638 610 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000)
639 611 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000)
640 612 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000)
641 613
642 614 /*
643 615 * xgetbv/xsetbv support
644 616 */
645 617
646 618 #define XFEATURE_ENABLED_MASK 0x0
647 619 /*
648 620 * XFEATURE_ENABLED_MASK values (eax)
649 621 */
650 622 #define XFEATURE_LEGACY_FP 0x1
651 623 #define XFEATURE_SSE 0x2
652 624 #define XFEATURE_AVX 0x4
653 625 #define XFEATURE_MAX XFEATURE_AVX
654 626 #define XFEATURE_FP_ALL \
655 627 (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
656 628
657 629 #if !defined(_ASM)
658 630
659 631 #if defined(_KERNEL) || defined(_KMEMUSER)
660 632
661 633 #define NUM_X86_FEATURES 46
662 634 extern uchar_t x86_featureset[];
663 635
664 636 extern void free_x86_featureset(void *featureset);
665 637 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
666 638 extern void add_x86_feature(void *featureset, uint_t feature);
667 639 extern void remove_x86_feature(void *featureset, uint_t feature);
668 640 extern boolean_t compare_x86_featureset(void *setA, void *setB);
669 641 extern void print_x86_featureset(void *featureset);
670 642
671 643
672 644 extern uint_t x86_type;
673 645 extern uint_t x86_vendor;
674 646 extern uint_t x86_clflush_size;
675 647
676 648 extern uint_t pentiumpro_bug4046376;
677 649
678 650 extern const char CyrixInstead[];
679 651
680 652 #endif
681 653
682 654 #if defined(_KERNEL)
683 655
684 656 /*
685 657 * This structure is used to pass arguments and get return values back
686 658 * from the CPUID instruction in __cpuid_insn() routine.
687 659 */
688 660 struct cpuid_regs {
689 661 uint32_t cp_eax;
690 662 uint32_t cp_ebx;
691 663 uint32_t cp_ecx;
692 664 uint32_t cp_edx;
693 665 };
694 666
695 667 /*
696 668 * Utility functions to get/set extended control registers (XCR)
697 669 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
698 670 */
699 671 extern uint64_t get_xcr(uint_t);
700 672 extern void set_xcr(uint_t, uint64_t);
701 673
702 674 extern uint64_t rdmsr(uint_t);
703 675 extern void wrmsr(uint_t, const uint64_t);
704 676 extern uint64_t xrdmsr(uint_t);
705 677 extern void xwrmsr(uint_t, const uint64_t);
706 678 extern int checked_rdmsr(uint_t, uint64_t *);
707 679 extern int checked_wrmsr(uint_t, uint64_t);
708 680
709 681 extern void invalidate_cache(void);
710 682 extern ulong_t getcr4(void);
711 683 extern void setcr4(ulong_t);
712 684
713 685 extern void mtrr_sync(void);
714 686
715 687 extern void cpu_fast_syscall_enable(void *);
716 688 extern void cpu_fast_syscall_disable(void *);
717 689
718 690 struct cpu;
719 691
720 692 extern int cpuid_checkpass(struct cpu *, int);
721 693 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
722 694 extern uint32_t __cpuid_insn(struct cpuid_regs *);
723 695 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
724 696 extern int cpuid_getidstr(struct cpu *, char *, size_t);
725 697 extern const char *cpuid_getvendorstr(struct cpu *);
726 698 extern uint_t cpuid_getvendor(struct cpu *);
727 699 extern uint_t cpuid_getfamily(struct cpu *);
728 700 extern uint_t cpuid_getmodel(struct cpu *);
729 701 extern uint_t cpuid_getstep(struct cpu *);
730 702 extern uint_t cpuid_getsig(struct cpu *);
731 703 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
732 704 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
733 705 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
734 706 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
735 707 extern int cpuid_get_chipid(struct cpu *);
736 708 extern id_t cpuid_get_coreid(struct cpu *);
737 709 extern int cpuid_get_pkgcoreid(struct cpu *);
738 710 extern int cpuid_get_clogid(struct cpu *);
739 711 extern int cpuid_get_cacheid(struct cpu *);
740 712 extern uint32_t cpuid_get_apicid(struct cpu *);
741 713 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
742 714 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
743 715 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
744 716 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
745 717 extern int cpuid_is_cmt(struct cpu *);
746 718 extern int cpuid_syscall32_insn(struct cpu *);
747 719 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
748 720
749 721 extern uint32_t cpuid_getchiprev(struct cpu *);
750 722 extern const char *cpuid_getchiprevstr(struct cpu *);
751 723 extern uint32_t cpuid_getsockettype(struct cpu *);
752 724 extern const char *cpuid_getsocketstr(struct cpu *);
753 725
754 726 extern int cpuid_have_cr8access(struct cpu *);
755 727
756 728 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
757 729
758 730 struct cpuid_info;
759 731
760 732 extern void setx86isalist(void);
761 733 extern void cpuid_alloc_space(struct cpu *);
762 734 extern void cpuid_free_space(struct cpu *);
763 735 extern void cpuid_pass1(struct cpu *, uchar_t *);
764 736 extern void cpuid_pass2(struct cpu *);
765 737 extern void cpuid_pass3(struct cpu *);
766 738 extern void cpuid_pass4(struct cpu *, uint_t *);
767 739 extern void cpuid_set_cpu_properties(void *, processorid_t,
768 740 struct cpuid_info *);
769 741
770 742 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
771 743 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
772 744
773 745 #if !defined(__xpv)
774 746 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
775 747 extern void cpuid_mwait_free(struct cpu *);
776 748 extern int cpuid_deep_cstates_supported(void);
777 749 extern int cpuid_arat_supported(void);
778 750 extern int cpuid_iepb_supported(struct cpu *);
779 751 extern int cpuid_deadline_tsc_supported(void);
780 752 extern void vmware_port(int, uint32_t *);
781 753 #endif
782 754
783 755 struct cpu_ucode_info;
784 756
785 757 extern void ucode_alloc_space(struct cpu *);
786 758 extern void ucode_free_space(struct cpu *);
787 759 extern void ucode_check(struct cpu *);
788 760 extern void ucode_cleanup();
789 761
790 762 #if !defined(__xpv)
791 763 extern char _tsc_mfence_start;
792 764 extern char _tsc_mfence_end;
793 765 extern char _tscp_start;
794 766 extern char _tscp_end;
795 767 extern char _no_rdtsc_start;
796 768 extern char _no_rdtsc_end;
797 769 extern char _tsc_lfence_start;
798 770 extern char _tsc_lfence_end;
799 771 #endif
800 772
801 773 #if !defined(__xpv)
802 774 extern char bcopy_patch_start;
803 775 extern char bcopy_patch_end;
804 776 extern char bcopy_ck_size;
805 777 #endif
806 778
807 779 extern void post_startup_cpu_fixups(void);
808 780
809 781 extern uint_t workaround_errata(struct cpu *);
810 782
811 783 #if defined(OPTERON_ERRATUM_93)
812 784 extern int opteron_erratum_93;
813 785 #endif
814 786
815 787 #if defined(OPTERON_ERRATUM_91)
816 788 extern int opteron_erratum_91;
817 789 #endif
818 790
819 791 #if defined(OPTERON_ERRATUM_100)
820 792 extern int opteron_erratum_100;
821 793 #endif
822 794
823 795 #if defined(OPTERON_ERRATUM_121)
824 796 extern int opteron_erratum_121;
825 797 #endif
826 798
827 799 #if defined(OPTERON_WORKAROUND_6323525)
828 800 extern int opteron_workaround_6323525;
829 801 extern void patch_workaround_6323525(void);
830 802 #endif
831 803
832 804 #if !defined(__xpv)
833 805 extern void determine_platform(void);
834 806 #endif
835 807 extern int get_hwenv(void);
836 808 extern int is_controldom(void);
837 809
838 810 extern void xsave_setup_msr(struct cpu *);
839 811
840 812 /*
841 813 * Hypervisor signatures
842 814 */
843 815 #define HVSIG_XEN_HVM "XenVMMXenVMM"
844 816 #define HVSIG_VMWARE "VMwareVMware"
845 817 #define HVSIG_KVM "KVMKVMKVM"
846 818 #define HVSIG_MICROSOFT "Microsoft Hv"
847 819
848 820 /*
849 821 * Defined hardware environments
850 822 */
851 823 #define HW_NATIVE (1 << 0) /* Running on bare metal */
852 824 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */
853 825
854 826 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */
855 827 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */
856 828 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */
857 829 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */
858 830
859 831 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT)
860 832
861 833 #endif /* _KERNEL */
862 834
863 835 #endif /* !_ASM */
864 836
865 837 /*
866 838 * VMware hypervisor related defines
867 839 */
868 840 #define VMWARE_HVMAGIC 0x564d5868
869 841 #define VMWARE_HVPORT 0x5658
870 842 #define VMWARE_HVCMD_GETVERSION 0x0a
871 843 #define VMWARE_HVCMD_GETTSCFREQ 0x2d
872 844
873 845 #ifdef __cplusplus
874 846 }
875 847 #endif
876 848
877 849 #endif /* _SYS_X86_ARCHEXT_H */
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