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6116 remove unused FMT_CPUID_*

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          --- old/usr/src/uts/intel/sys/x86_archext.h
          +++ new/usr/src/uts/intel/sys/x86_archext.h
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  78   78  #define CPUID_INTC_EDX_MMX      0x00800000      /* MMX instructions */
  79   79  #define CPUID_INTC_EDX_FXSR     0x01000000      /* fxsave and fxrstor */
  80   80  #define CPUID_INTC_EDX_SSE      0x02000000      /* streaming SIMD extensions */
  81   81  #define CPUID_INTC_EDX_SSE2     0x04000000      /* SSE extensions */
  82   82  #define CPUID_INTC_EDX_SS       0x08000000      /* self-snoop */
  83   83  #define CPUID_INTC_EDX_HTT      0x10000000      /* Hyper Thread Technology */
  84   84  #define CPUID_INTC_EDX_TM       0x20000000      /* thermal monitoring */
  85   85  #define CPUID_INTC_EDX_IA64     0x40000000      /* Itanium emulating IA32 */
  86   86  #define CPUID_INTC_EDX_PBE      0x80000000      /* Pending Break Enable */
  87   87  
  88      -#define FMT_CPUID_INTC_EDX                                      \
  89      -        "\20"                                                   \
  90      -        "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr"     \
  91      -        "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat"        \
  92      -        "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8"         \
  93      -        "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
  94      -
  95   88  /*
  96   89   * cpuid instruction feature flags in %ecx (standard function 1)
  97   90   */
  98   91  
  99   92  #define CPUID_INTC_ECX_SSE3     0x00000001      /* Yet more SSE extensions */
 100   93  #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002     /* PCLMULQDQ insn */
 101   94                                                  /* 0x00000004 - reserved */
 102   95  #define CPUID_INTC_ECX_MON      0x00000008      /* MONITOR/MWAIT */
 103   96  #define CPUID_INTC_ECX_DSCPL    0x00000010      /* CPL-qualified debug store */
 104   97  #define CPUID_INTC_ECX_VMX      0x00000020      /* Hardware VM extensions */
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 121  114  #define CPUID_INTC_ECX_MOVBE    0x00400000      /* MOVBE insn */
 122  115  #define CPUID_INTC_ECX_POPCNT   0x00800000      /* POPCNT insn */
 123  116  #define CPUID_INTC_ECX_AES      0x02000000      /* AES insns */
 124  117  #define CPUID_INTC_ECX_XSAVE    0x04000000      /* XSAVE/XRESTOR insns */
 125  118  #define CPUID_INTC_ECX_OSXSAVE  0x08000000      /* OS supports XSAVE insns */
 126  119  #define CPUID_INTC_ECX_AVX      0x10000000      /* AVX supported */
 127  120  #define CPUID_INTC_ECX_F16C     0x20000000      /* F16C supported */
 128  121  #define CPUID_INTC_ECX_RDRAND   0x40000000      /* RDRAND supported */
 129  122  #define CPUID_INTC_ECX_HV       0x80000000      /* Hypervisor */
 130  123  
 131      -#define FMT_CPUID_INTC_ECX                                      \
 132      -        "\20"                                                   \
 133      -        "\37rdrand\36f16c\35avx\34osxsav\33xsave"               \
 134      -        "\32aes"                                                \
 135      -        "\30popcnt\27movbe\26x2apic\25sse4.2\24sse4.1\23dca"    \
 136      -        "\20\17etprd\16cx16\13cid\12ssse3\11tm2"                \
 137      -        "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
 138      -
 139  124  /*
 140  125   * cpuid instruction feature flags in %edx (extended function 0x80000001)
 141  126   */
 142  127  
 143  128  #define CPUID_AMD_EDX_FPU       0x00000001      /* x87 fpu present */
 144  129  #define CPUID_AMD_EDX_VME       0x00000002      /* virtual-8086 extension */
 145  130  #define CPUID_AMD_EDX_DE        0x00000004      /* debugging extensions */
 146  131  #define CPUID_AMD_EDX_PSE       0x00000008      /* page size extensions */
 147  132  #define CPUID_AMD_EDX_TSC       0x00000010      /* time stamp counter */
 148  133  #define CPUID_AMD_EDX_MSR       0x00000020      /* rdmsr and wrmsr */
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 167  152  #define CPUID_AMD_EDX_MMX       0x00800000      /* MMX instructions */
 168  153  #define CPUID_AMD_EDX_FXSR      0x01000000      /* fxsave and fxrstor */
 169  154  #define CPUID_AMD_EDX_FFXSR     0x02000000      /* fast fxsave/fxrstor */
 170  155  #define CPUID_AMD_EDX_1GPG      0x04000000      /* 1GB page */
 171  156  #define CPUID_AMD_EDX_TSCP      0x08000000      /* rdtscp instruction */
 172  157                                  /* 0x10000000 - reserved */
 173  158  #define CPUID_AMD_EDX_LM        0x20000000      /* AMD: long mode */
 174  159  #define CPUID_AMD_EDX_3DNowx    0x40000000      /* AMD: extensions to 3DNow! */
 175  160  #define CPUID_AMD_EDX_3DNow     0x80000000      /* AMD: 3DNow! instructions */
 176  161  
 177      -#define FMT_CPUID_AMD_EDX                                       \
 178      -        "\20"                                                   \
 179      -        "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr"              \
 180      -        "\30mmx\27mmxext\25nx\22pse\21pat"                      \
 181      -        "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8"     \
 182      -        "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
 183      -
 184  162  #define CPUID_AMD_ECX_AHF64     0x00000001      /* LAHF and SAHF in long mode */
 185  163  #define CPUID_AMD_ECX_CMP_LGCY  0x00000002      /* AMD: multicore chip */
 186  164  #define CPUID_AMD_ECX_SVM       0x00000004      /* AMD: secure VM */
 187  165  #define CPUID_AMD_ECX_EAS       0x00000008      /* extended apic space */
 188  166  #define CPUID_AMD_ECX_CR8D      0x00000010      /* AMD: 32-bit mov %cr8 */
 189  167  #define CPUID_AMD_ECX_LZCNT     0x00000020      /* AMD: LZCNT insn */
 190  168  #define CPUID_AMD_ECX_SSE4A     0x00000040      /* AMD: SSE4A insns */
 191  169  #define CPUID_AMD_ECX_MAS       0x00000080      /* AMD: MisAlignSse mnode */
 192  170  #define CPUID_AMD_ECX_3DNP      0x00000100      /* AMD: 3DNowPrefectch */
 193  171  #define CPUID_AMD_ECX_OSVW      0x00000200      /* AMD: OSVW */
 194  172  #define CPUID_AMD_ECX_IBS       0x00000400      /* AMD: IBS */
 195  173  #define CPUID_AMD_ECX_SSE5      0x00000800      /* AMD: SSE5 */
 196  174  #define CPUID_AMD_ECX_SKINIT    0x00001000      /* AMD: SKINIT */
 197  175  #define CPUID_AMD_ECX_WDT       0x00002000      /* AMD: WDT */
 198  176  #define CPUID_AMD_ECX_TOPOEXT   0x00400000      /* AMD: Topology Extensions */
 199      -
 200      -#define FMT_CPUID_AMD_ECX                                       \
 201      -        "\20"                                                   \
 202      -        "\22topoext"                                            \
 203      -        "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas"        \
 204      -        "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
 205  177  
 206  178  /*
 207  179   * Intel now seems to have claimed part of the "extended" function
 208  180   * space that we previously for non-Intel implementors to use.
 209  181   * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
 210  182   * is available in long mode i.e. what AMD indicate using bit 0.
 211  183   * On the other hand, everything else is labelled as reserved.
 212  184   */
 213  185  #define CPUID_INTC_ECX_AHF64    0x00100000      /* LAHF and SAHF in long mode */
 214  186  
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