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6116 remove unused FMT_CPUID_*
@@ -83,17 +83,10 @@
#define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
#define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
#define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
#define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
-#define FMT_CPUID_INTC_EDX \
- "\20" \
- "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \
- "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \
- "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \
- "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
-
/*
* cpuid instruction feature flags in %ecx (standard function 1)
*/
#define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
@@ -126,18 +119,10 @@
#define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
#define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
#define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
#define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
-#define FMT_CPUID_INTC_ECX \
- "\20" \
- "\37rdrand\36f16c\35avx\34osxsav\33xsave" \
- "\32aes" \
- "\30popcnt\27movbe\26x2apic\25sse4.2\24sse4.1\23dca" \
- "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \
- "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
-
/*
* cpuid instruction feature flags in %edx (extended function 0x80000001)
*/
#define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
@@ -172,17 +157,10 @@
/* 0x10000000 - reserved */
#define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
#define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
#define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
-#define FMT_CPUID_AMD_EDX \
- "\20" \
- "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \
- "\30mmx\27mmxext\25nx\22pse\21pat" \
- "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \
- "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
-
#define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
#define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
#define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
#define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
#define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
@@ -195,16 +173,10 @@
#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
#define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
#define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
#define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
-#define FMT_CPUID_AMD_ECX \
- "\20" \
- "\22topoext" \
- "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \
- "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
-
/*
* Intel now seems to have claimed part of the "extended" function
* space that we previously for non-Intel implementors to use.
* More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
* is available in long mode i.e. what AMD indicate using bit 0.