68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 /* 0x100000 - reserved */
76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87
88 #define FMT_CPUID_INTC_EDX \
89 "\20" \
90 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \
91 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \
92 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \
93 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
94
95 /*
96 * cpuid instruction feature flags in %ecx (standard function 1)
97 */
98
99 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
100 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
101 /* 0x00000004 - reserved */
102 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
103 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
104 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
105 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
106 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
107 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
108 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
109 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
110 /* 0x00000800 - reserved */
111 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
112 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
113 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
114 /* 0x00008000 - reserved */
115 /* 0x00010000 - reserved */
116 /* 0x00020000 - reserved */
117 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
118 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
119 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
120 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
121 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
122 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
123 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
124 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
125 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
126 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
127 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
128 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
129 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
130
131 #define FMT_CPUID_INTC_ECX \
132 "\20" \
133 "\37rdrand\36f16c\35avx\34osxsav\33xsave" \
134 "\32aes" \
135 "\30popcnt\27movbe\26x2apic\25sse4.2\24sse4.1\23dca" \
136 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \
137 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
138
139 /*
140 * cpuid instruction feature flags in %edx (extended function 0x80000001)
141 */
142
143 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
144 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
145 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
146 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
147 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
148 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
149 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
150 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
151 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
152 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
153 /* 0x00000400 - sysc on K6m6 */
154 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
155 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
156 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
157 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
158 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
159 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
160 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
161 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
162 /* 0x00040000 - reserved */
163 /* 0x00080000 - reserved */
164 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
165 /* 0x00200000 - reserved */
166 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
167 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
168 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
169 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
170 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
171 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
172 /* 0x10000000 - reserved */
173 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
174 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
175 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
176
177 #define FMT_CPUID_AMD_EDX \
178 "\20" \
179 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \
180 "\30mmx\27mmxext\25nx\22pse\21pat" \
181 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \
182 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
183
184 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
185 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
186 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
187 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
188 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
189 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
190 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
191 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
192 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
193 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
194 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
195 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
196 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
197 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
198 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
199
200 #define FMT_CPUID_AMD_ECX \
201 "\20" \
202 "\22topoext" \
203 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \
204 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
205
206 /*
207 * Intel now seems to have claimed part of the "extended" function
208 * space that we previously for non-Intel implementors to use.
209 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
210 * is available in long mode i.e. what AMD indicate using bit 0.
211 * On the other hand, everything else is labelled as reserved.
212 */
213 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
214
215 /*
216 * Intel also uses cpuid leaf 7 to have additional instructions and features.
217 * Like some other leaves, but unlike the current ones we care about, it
218 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
219 * with the potential use of additional sub-leaves in the future, we now
220 * specifically label the EBX features with their leaf and sub-leaf.
221 */
222 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
223 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
224 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
|
68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 /* 0x100000 - reserved */
76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87
88 /*
89 * cpuid instruction feature flags in %ecx (standard function 1)
90 */
91
92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
94 /* 0x00000004 - reserved */
95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
103 /* 0x00000800 - reserved */
104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
107 /* 0x00008000 - reserved */
108 /* 0x00010000 - reserved */
109 /* 0x00020000 - reserved */
110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
116 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
117 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
118 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
119 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
120 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
121 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
122 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
123
124 /*
125 * cpuid instruction feature flags in %edx (extended function 0x80000001)
126 */
127
128 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
129 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
130 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
131 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
132 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
133 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
134 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
135 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
136 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
137 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
138 /* 0x00000400 - sysc on K6m6 */
139 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
140 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
141 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
142 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
143 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
144 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
145 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
146 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
147 /* 0x00040000 - reserved */
148 /* 0x00080000 - reserved */
149 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
150 /* 0x00200000 - reserved */
151 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
152 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
153 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
154 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
155 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
156 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
157 /* 0x10000000 - reserved */
158 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
159 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
160 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
161
162 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
163 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
164 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
165 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
166 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
167 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
168 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
169 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
170 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
171 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
172 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
173 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
174 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
175 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
176 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
177
178 /*
179 * Intel now seems to have claimed part of the "extended" function
180 * space that we previously for non-Intel implementors to use.
181 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
182 * is available in long mode i.e. what AMD indicate using bit 0.
183 * On the other hand, everything else is labelled as reserved.
184 */
185 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
186
187 /*
188 * Intel also uses cpuid leaf 7 to have additional instructions and features.
189 * Like some other leaves, but unlike the current ones we care about, it
190 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
191 * with the potential use of additional sub-leaves in the future, we now
192 * specifically label the EBX features with their leaf and sub-leaf.
193 */
194 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
195 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
196 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
|