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5253 kmem_alloc/kmem_zalloc won't fail with KM_SLEEP
5254 getrbuf won't fail with KM_SLEEP
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--- old/usr/src/uts/common/io/usb/hcd/uhci/uhciutil.c
+++ new/usr/src/uts/common/io/usb/hcd/uhci/uhciutil.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 26
27 27 /*
28 28 * Universal Host Controller Driver (UHCI)
29 29 *
30 30 * The UHCI driver is a driver which interfaces to the Universal
31 31 * Serial Bus Driver (USBA) and the Host Controller (HC). The interface to
32 32 * the Host Controller is defined by the UHCI.
33 33 * This file contains misc functions.
34 34 */
35 35 #include <sys/usb/hcd/uhci/uhcid.h>
36 36 #include <sys/usb/hcd/uhci/uhciutil.h>
37 37 #include <sys/usb/hcd/uhci/uhcipolled.h>
38 38
39 39 #include <sys/disp.h>
40 40
41 41 /* Globals */
42 42 extern uint_t uhci_td_pool_size; /* Num TDs */
43 43 extern uint_t uhci_qh_pool_size; /* Num QHs */
44 44 extern ushort_t uhci_tree_bottom_nodes[];
45 45 extern void *uhci_statep;
46 46
47 47 /* function prototypes */
48 48 static void uhci_build_interrupt_lattice(uhci_state_t *uhcip);
49 49 static int uhci_init_frame_lst_table(dev_info_t *dip, uhci_state_t *uhcip);
50 50
51 51 static uint_t uhci_lattice_height(uint_t bandwidth);
52 52 static uint_t uhci_lattice_parent(uint_t node);
53 53 static uint_t uhci_leftmost_leaf(uint_t node, uint_t height);
54 54 static uint_t uhci_compute_total_bandwidth(usb_ep_descr_t *endpoint,
55 55 usb_port_status_t port_status);
56 56
57 57 static int uhci_bandwidth_adjust(uhci_state_t *uhcip,
58 58 usb_ep_descr_t *endpoint, usb_port_status_t port_status);
59 59
60 60 static uhci_td_t *uhci_allocate_td_from_pool(uhci_state_t *uhcip);
61 61 static void uhci_fill_in_td(uhci_state_t *uhcip,
62 62 uhci_td_t *td, uhci_td_t *current_dummy,
63 63 uint32_t buffer_offset, size_t length,
64 64 uhci_pipe_private_t *pp, uchar_t PID,
65 65 usb_req_attrs_t attrs, uhci_trans_wrapper_t *tw);
66 66 static uint32_t uhci_get_tw_paddr_by_offs(uhci_state_t *uhcip,
67 67 uint32_t buffer_offset, size_t length,
68 68 uhci_trans_wrapper_t *tw);
69 69 static uhci_trans_wrapper_t *uhci_create_transfer_wrapper(
70 70 uhci_state_t *uhcip, uhci_pipe_private_t *pp,
71 71 size_t length, usb_flags_t usb_flags);
72 72 static uhci_trans_wrapper_t *uhci_create_isoc_transfer_wrapper(
73 73 uhci_state_t *uhcip, uhci_pipe_private_t *pp,
74 74 usb_isoc_req_t *req, size_t length,
75 75 usb_flags_t usb_flags);
76 76
77 77 static int uhci_create_setup_pkt(uhci_state_t *uhcip,
78 78 uhci_pipe_private_t *pp, uhci_trans_wrapper_t *tw);
79 79 static void uhci_insert_ctrl_qh(uhci_state_t *uhcip,
80 80 uhci_pipe_private_t *pp);
81 81 static void uhci_remove_ctrl_qh(uhci_state_t *uhcip,
82 82 uhci_pipe_private_t *pp);
83 83 static void uhci_insert_intr_qh(uhci_state_t *uhcip,
84 84 uhci_pipe_private_t *pp);
85 85 static void uhci_remove_intr_qh(uhci_state_t *uhcip,
86 86 uhci_pipe_private_t *pp);
87 87 static void uhci_remove_bulk_qh(uhci_state_t *uhcip,
88 88 uhci_pipe_private_t *pp);
89 89 static void uhci_insert_bulk_qh(uhci_state_t *uhcip,
90 90 uhci_pipe_private_t *pp);
91 91 static void uhci_handle_bulk_td_errors(uhci_state_t *uhcip, uhci_td_t *td);
92 92 static int uhci_alloc_memory_for_tds(uhci_state_t *uhcip, uint_t num_tds,
93 93 uhci_bulk_isoc_xfer_t *info);
94 94 static int uhci_alloc_bulk_isoc_tds(uhci_state_t *uhcip, uint_t num_tds,
95 95 uhci_bulk_isoc_xfer_t *info);
96 96 static void uhci_get_isoc_td_by_index(uhci_state_t *uhcip,
97 97 uhci_bulk_isoc_xfer_t *info, uint_t index,
98 98 uhci_td_t **tdpp, uhci_bulk_isoc_td_pool_t **td_pool_pp);
99 99 static void uhci_get_bulk_td_by_paddr(uhci_state_t *uhcip,
100 100 uhci_bulk_isoc_xfer_t *info, uint32_t paddr,
101 101 uhci_bulk_isoc_td_pool_t **td_pool_pp);
102 102
103 103 static int uhci_handle_isoc_receive(uhci_state_t *uhcip,
104 104 uhci_pipe_private_t *pp, uhci_trans_wrapper_t *tw);
105 105 static void uhci_delete_isoc_td(uhci_state_t *uhcip,
106 106 uhci_td_t *td);
107 107 #ifdef DEBUG
108 108 static void uhci_print_td(uhci_state_t *uhcip, uhci_td_t *td);
109 109 static void uhci_print_qh(uhci_state_t *uhcip, queue_head_t *qh);
110 110 #endif
111 111
112 112
113 113 /*
114 114 * uhci_build_interrupt_lattice:
115 115 *
116 116 * Construct the interrupt lattice tree using static Queue Head pointers.
117 117 * This interrupt lattice tree will have total of 63 queue heads and the
118 118 * Host Controller (HC) processes queue heads every frame.
119 119 */
120 120 static void
121 121 uhci_build_interrupt_lattice(uhci_state_t *uhcip)
122 122 {
123 123 int half_list = NUM_INTR_QH_LISTS / 2;
124 124 uint16_t i, j, k;
125 125 uhci_td_t *sof_td, *isoc_td;
126 126 uintptr_t addr;
127 127 queue_head_t *list_array = uhcip->uhci_qh_pool_addr;
128 128 queue_head_t *tmp_qh;
129 129 frame_lst_table_t *frame_lst_tablep =
130 130 uhcip->uhci_frame_lst_tablep;
131 131
132 132 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
133 133 "uhci_build_interrupt_lattice:");
134 134
135 135 /*
136 136 * Reserve the first 63 queue head structures in the pool as static
137 137 * queue heads & these are required for constructing interrupt
138 138 * lattice tree.
139 139 */
140 140 for (i = 0; i < NUM_INTR_QH_LISTS; i++) {
141 141 SetQH32(uhcip, list_array[i].link_ptr, HC_END_OF_LIST);
142 142 SetQH32(uhcip, list_array[i].element_ptr, HC_END_OF_LIST);
143 143 list_array[i].qh_flag = QUEUE_HEAD_FLAG_STATIC;
144 144 list_array[i].node = i;
145 145 }
146 146
147 147 /* Build the interrupt lattice tree */
148 148 for (i = 0; i < half_list - 1; i++) {
149 149 /*
150 150 * The next pointer in the host controller queue head
151 151 * descriptor must contain an iommu address. Calculate
152 152 * the offset into the cpu address and add this to the
153 153 * starting iommu address.
154 154 */
155 155 addr = QH_PADDR(&list_array[i]) | HC_QUEUE_HEAD;
156 156
157 157 SetQH32(uhcip, list_array[2*i + 1].link_ptr, addr);
158 158 SetQH32(uhcip, list_array[2*i + 2].link_ptr, addr);
159 159 }
160 160
161 161 /*
162 162 * Initialize the interrupt list in the Frame list Table
163 163 * so that it points to the bottom of the tree.
164 164 */
165 165 for (i = 0, j = 0; i < pow_2(TREE_HEIGHT); i++) {
166 166 addr = QH_PADDR(&list_array[half_list + i - 1]);
167 167 for (k = 0; k < pow_2(VIRTUAL_TREE_HEIGHT); k++) {
168 168 SetFL32(uhcip,
169 169 frame_lst_tablep[uhci_tree_bottom_nodes[j++]],
170 170 addr | HC_QUEUE_HEAD);
171 171 }
172 172 }
173 173
174 174 /*
175 175 * Create a controller and bulk Queue heads
176 176 */
177 177 uhcip->uhci_ctrl_xfers_q_head = uhci_alloc_queue_head(uhcip);
178 178 tmp_qh = uhcip->uhci_ctrl_xfers_q_tail = uhcip->uhci_ctrl_xfers_q_head;
179 179
180 180 SetQH32(uhcip, list_array[0].link_ptr,
181 181 (QH_PADDR(tmp_qh) | HC_QUEUE_HEAD));
182 182
183 183 uhcip->uhci_bulk_xfers_q_head = uhci_alloc_queue_head(uhcip);
184 184 uhcip->uhci_bulk_xfers_q_tail = uhcip->uhci_bulk_xfers_q_head;
185 185 SetQH32(uhcip, tmp_qh->link_ptr,
186 186 (QH_PADDR(uhcip->uhci_bulk_xfers_q_head)|HC_QUEUE_HEAD));
187 187
188 188 SetQH32(uhcip, uhcip->uhci_bulk_xfers_q_head->link_ptr, HC_END_OF_LIST);
189 189
190 190 /*
191 191 * Add a dummy TD to the static queue head 0. THis is used
192 192 * to generate an at the end of frame.
193 193 */
194 194 sof_td = uhci_allocate_td_from_pool(uhcip);
195 195
196 196 SetQH32(uhcip, list_array[0].element_ptr,
197 197 TD_PADDR(sof_td) | HC_TD_HEAD);
198 198 SetTD32(uhcip, sof_td->link_ptr, HC_END_OF_LIST);
199 199 uhcip->uhci_sof_td = sof_td;
200 200
201 201 /*
202 202 * Add a dummy td that is used to generate an interrupt for
203 203 * every 1024 frames.
204 204 */
205 205 isoc_td = uhci_allocate_td_from_pool(uhcip);
206 206 SetTD32(uhcip, isoc_td->link_ptr, HC_END_OF_LIST);
207 207 uhcip->uhci_isoc_td = isoc_td;
208 208
209 209 uhcip->uhci_isoc_qh = uhci_alloc_queue_head(uhcip);
210 210 SetQH32(uhcip, uhcip->uhci_isoc_qh->link_ptr,
211 211 GetFL32(uhcip, uhcip->uhci_frame_lst_tablep[MAX_FRAME_NUM]));
212 212 SetQH32(uhcip, uhcip->uhci_isoc_qh->element_ptr, TD_PADDR(isoc_td));
213 213 SetFL32(uhcip, uhcip->uhci_frame_lst_tablep[MAX_FRAME_NUM],
214 214 QH_PADDR(uhcip->uhci_isoc_qh) | HC_QUEUE_HEAD);
215 215 }
216 216
217 217
218 218 /*
219 219 * uhci_allocate_pools:
220 220 * Allocate the system memory for the Queue Heads Descriptor and
221 221 * for the Transfer Descriptor (TD) pools. Both QH and TD structures
222 222 * must be aligned to a 16 byte boundary.
223 223 */
224 224 int
225 225 uhci_allocate_pools(uhci_state_t *uhcip)
226 226 {
227 227 dev_info_t *dip = uhcip->uhci_dip;
228 228 size_t real_length;
229 229 int i, result;
230 230 uint_t ccount;
231 231 ddi_device_acc_attr_t dev_attr;
232 232
233 233 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
234 234 "uhci_allocate_pools:");
235 235
236 236 /* The host controller will be little endian */
237 237 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
238 238 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
239 239 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
240 240
241 241 /* Allocate the TD pool DMA handle */
242 242 if (ddi_dma_alloc_handle(dip, &uhcip->uhci_dma_attr, DDI_DMA_SLEEP, 0,
243 243 &uhcip->uhci_td_pool_dma_handle) != DDI_SUCCESS) {
244 244
245 245 return (USB_FAILURE);
246 246 }
247 247
248 248 /* Allocate the memory for the TD pool */
249 249 if (ddi_dma_mem_alloc(uhcip->uhci_td_pool_dma_handle,
250 250 uhci_td_pool_size * sizeof (uhci_td_t),
251 251 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 0,
252 252 (caddr_t *)&uhcip->uhci_td_pool_addr, &real_length,
253 253 &uhcip->uhci_td_pool_mem_handle)) {
254 254
255 255 return (USB_FAILURE);
256 256 }
257 257
258 258 /* Map the TD pool into the I/O address space */
259 259 result = ddi_dma_addr_bind_handle(uhcip->uhci_td_pool_dma_handle,
260 260 NULL, (caddr_t)uhcip->uhci_td_pool_addr, real_length,
261 261 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP,
262 262 NULL, &uhcip->uhci_td_pool_cookie, &ccount);
263 263
264 264 bzero((void *)uhcip->uhci_td_pool_addr,
265 265 uhci_td_pool_size * sizeof (uhci_td_t));
266 266
267 267 /* Process the result */
268 268 if (result == DDI_DMA_MAPPED) {
269 269 /* The cookie count should be 1 */
270 270 if (ccount != 1) {
271 271 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
272 272 "uhci_allocate_pools: More than 1 cookie");
273 273
274 274 return (USB_FAILURE);
275 275 }
276 276 } else {
277 277 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
278 278 "uhci_allocate_pools: Result = %d", result);
279 279
280 280 uhci_decode_ddi_dma_addr_bind_handle_result(uhcip, result);
281 281
282 282 return (USB_FAILURE);
283 283 }
284 284
285 285 uhcip->uhci_dma_addr_bind_flag |= UHCI_TD_POOL_BOUND;
286 286
287 287 /* Initialize the TD pool */
288 288 for (i = 0; i < uhci_td_pool_size; i++) {
289 289 uhcip->uhci_td_pool_addr[i].flag = TD_FLAG_FREE;
290 290 }
291 291
292 292 /* Allocate the TD pool DMA handle */
293 293 if (ddi_dma_alloc_handle(dip, &uhcip->uhci_dma_attr, DDI_DMA_SLEEP,
294 294 0, &uhcip->uhci_qh_pool_dma_handle) != DDI_SUCCESS) {
295 295
296 296 return (USB_FAILURE);
297 297 }
298 298
299 299 /* Allocate the memory for the QH pool */
300 300 if (ddi_dma_mem_alloc(uhcip->uhci_qh_pool_dma_handle,
301 301 uhci_qh_pool_size * sizeof (queue_head_t),
302 302 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 0,
303 303 (caddr_t *)&uhcip->uhci_qh_pool_addr, &real_length,
304 304 &uhcip->uhci_qh_pool_mem_handle) != DDI_SUCCESS) {
305 305
306 306 return (USB_FAILURE);
307 307 }
308 308
309 309 result = ddi_dma_addr_bind_handle(uhcip->uhci_qh_pool_dma_handle,
310 310 NULL, (caddr_t)uhcip->uhci_qh_pool_addr, real_length,
311 311 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
312 312 &uhcip->uhci_qh_pool_cookie, &ccount);
313 313
314 314 /* Process the result */
315 315 if (result == DDI_DMA_MAPPED) {
316 316 /* The cookie count should be 1 */
317 317 if (ccount != 1) {
318 318 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
319 319 "uhci_allocate_pools: More than 1 cookie");
320 320
321 321 return (USB_FAILURE);
322 322 }
323 323 } else {
324 324 uhci_decode_ddi_dma_addr_bind_handle_result(uhcip, result);
325 325
326 326 return (USB_FAILURE);
327 327 }
328 328
329 329 uhcip->uhci_dma_addr_bind_flag |= UHCI_QH_POOL_BOUND;
330 330
331 331 bzero((void *)uhcip->uhci_qh_pool_addr,
332 332 uhci_qh_pool_size * sizeof (queue_head_t));
333 333
334 334 /* Initialize the QH pool */
335 335 for (i = 0; i < uhci_qh_pool_size; i ++) {
336 336 uhcip->uhci_qh_pool_addr[i].qh_flag = QUEUE_HEAD_FLAG_FREE;
337 337 }
338 338
339 339 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
340 340 "uhci_allocate_pools: Completed");
341 341
342 342 return (USB_SUCCESS);
343 343 }
344 344
345 345
346 346 /*
347 347 * uhci_free_pools:
348 348 * Cleanup on attach failure or detach
349 349 */
350 350 void
351 351 uhci_free_pools(uhci_state_t *uhcip)
352 352 {
353 353 int i, flag, rval;
354 354 uhci_td_t *td;
355 355 uhci_trans_wrapper_t *tw;
356 356
357 357 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
358 358 "uhci_free_pools:");
359 359
360 360 if (uhcip->uhci_td_pool_addr && uhcip->uhci_td_pool_mem_handle) {
361 361 for (i = 0; i < uhci_td_pool_size; i ++) {
362 362 td = &uhcip->uhci_td_pool_addr[i];
363 363
364 364 flag = uhcip->uhci_td_pool_addr[i].flag;
365 365 if ((flag != TD_FLAG_FREE) &&
366 366 (flag != TD_FLAG_DUMMY) && (td->tw != NULL)) {
367 367 tw = td->tw;
368 368 uhci_free_tw(uhcip, tw);
369 369 }
370 370
371 371 }
372 372
373 373 if (uhcip->uhci_dma_addr_bind_flag & UHCI_TD_POOL_BOUND) {
374 374 rval = ddi_dma_unbind_handle(
375 375 uhcip->uhci_td_pool_dma_handle);
376 376 ASSERT(rval == DDI_SUCCESS);
377 377 }
378 378
379 379 ddi_dma_mem_free(&uhcip->uhci_td_pool_mem_handle);
380 380 }
381 381
382 382 /* Free the TD pool */
383 383 if (uhcip->uhci_td_pool_dma_handle) {
384 384 ddi_dma_free_handle(&uhcip->uhci_td_pool_dma_handle);
385 385 }
386 386
387 387 if (uhcip->uhci_qh_pool_addr && uhcip->uhci_qh_pool_mem_handle) {
388 388 if (uhcip->uhci_dma_addr_bind_flag & UHCI_QH_POOL_BOUND) {
389 389 rval = ddi_dma_unbind_handle(
390 390 uhcip->uhci_qh_pool_dma_handle);
391 391 ASSERT(rval == DDI_SUCCESS);
392 392 }
393 393 ddi_dma_mem_free(&uhcip->uhci_qh_pool_mem_handle);
394 394 }
395 395
396 396 /* Free the QH pool */
397 397 if (uhcip->uhci_qh_pool_dma_handle) {
398 398 ddi_dma_free_handle(&uhcip->uhci_qh_pool_dma_handle);
399 399 }
400 400
401 401 /* Free the Frame list Table area */
402 402 if (uhcip->uhci_frame_lst_tablep && uhcip->uhci_flt_mem_handle) {
403 403 if (uhcip->uhci_dma_addr_bind_flag & UHCI_FLA_POOL_BOUND) {
404 404 rval = ddi_dma_unbind_handle(
405 405 uhcip->uhci_flt_dma_handle);
406 406 ASSERT(rval == DDI_SUCCESS);
407 407 }
408 408 ddi_dma_mem_free(&uhcip->uhci_flt_mem_handle);
409 409 }
410 410
411 411 if (uhcip->uhci_flt_dma_handle) {
412 412 ddi_dma_free_handle(&uhcip->uhci_flt_dma_handle);
413 413 }
414 414 }
415 415
416 416
417 417 /*
418 418 * uhci_decode_ddi_dma_addr_bind_handle_result:
419 419 * Process the return values of ddi_dma_addr_bind_handle()
420 420 */
421 421 void
422 422 uhci_decode_ddi_dma_addr_bind_handle_result(uhci_state_t *uhcip, int result)
423 423 {
424 424 char *msg;
425 425
426 426 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
427 427 "uhci_decode_ddi_dma_addr_bind_handle_result:");
428 428
429 429 switch (result) {
430 430 case DDI_DMA_PARTIAL_MAP:
431 431 msg = "Partial transfers not allowed";
432 432 break;
433 433 case DDI_DMA_INUSE:
434 434 msg = "Handle is in use";
435 435 break;
436 436 case DDI_DMA_NORESOURCES:
437 437 msg = "No resources";
438 438 break;
439 439 case DDI_DMA_NOMAPPING:
440 440 msg = "No mapping";
441 441 break;
442 442 case DDI_DMA_TOOBIG:
443 443 msg = "Object is too big";
444 444 break;
445 445 default:
446 446 msg = "Unknown dma error";
447 447 }
448 448
449 449 USB_DPRINTF_L4(PRINT_MASK_ALL, uhcip->uhci_log_hdl, "%s", msg);
450 450 }
451 451
452 452
453 453 /*
454 454 * uhci_init_ctlr:
455 455 * Initialize the Host Controller (HC).
456 456 */
457 457 int
458 458 uhci_init_ctlr(uhci_state_t *uhcip)
459 459 {
460 460 dev_info_t *dip = uhcip->uhci_dip;
461 461 uint_t cmd_reg;
462 462 uint_t frame_base_addr;
463 463
464 464 mutex_enter(&uhcip->uhci_int_mutex);
465 465
466 466 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, "uhci_init_ctlr:");
467 467
468 468 /*
469 469 * When USB legacy mode is enabled, the BIOS manages the USB keyboard
470 470 * attached to the UHCI controller. It has been observed that some
471 471 * times the BIOS does not clear the interrupts in the legacy mode
472 472 * register in the PCI configuration space. So, disable the SMI intrs
473 473 * and route the intrs to PIRQD here.
474 474 */
475 475 pci_config_put16(uhcip->uhci_config_handle,
476 476 LEGACYMODE_REG_OFFSET, LEGACYMODE_REG_INIT_VALUE);
477 477
478 478 /*
479 479 * Disable all the interrupts.
480 480 */
481 481 Set_OpReg16(USBINTR, DISABLE_ALL_INTRS);
482 482
483 483 cmd_reg = Get_OpReg16(USBCMD);
484 484 cmd_reg &= (~USBCMD_REG_HC_RUN);
485 485
486 486 /* Stop the controller */
487 487 Set_OpReg16(USBCMD, cmd_reg);
488 488
489 489 /* Reset the host controller */
490 490 Set_OpReg16(USBCMD, USBCMD_REG_GBL_RESET);
491 491
492 492 /* Wait 10ms for reset to complete */
493 493 mutex_exit(&uhcip->uhci_int_mutex);
494 494 delay(drv_usectohz(UHCI_RESET_DELAY));
495 495 mutex_enter(&uhcip->uhci_int_mutex);
496 496
497 497 Set_OpReg16(USBCMD, 0);
498 498
499 499 /* Set the frame number to zero */
500 500 Set_OpReg16(FRNUM, 0);
501 501
502 502 if (uhcip->uhci_hc_soft_state == UHCI_CTLR_INIT_STATE) {
503 503 /* Initialize the Frame list base address area */
504 504 if (uhci_init_frame_lst_table(dip, uhcip) != USB_SUCCESS) {
505 505 mutex_exit(&uhcip->uhci_int_mutex);
506 506
507 507 return (USB_FAILURE);
508 508 }
509 509 }
510 510
511 511 /* Save the contents of the Frame Interval Registers */
512 512 uhcip->uhci_frame_interval = Get_OpReg8(SOFMOD);
513 513
514 514 frame_base_addr = uhcip->uhci_flt_cookie.dmac_address;
515 515
516 516 /* Set the Frame list base address */
517 517 Set_OpReg32(FRBASEADD, frame_base_addr);
518 518
519 519 /*
520 520 * Begin sending SOFs
521 521 * Set the Host Controller Functional State to Operational
522 522 */
523 523 cmd_reg = Get_OpReg16(USBCMD);
524 524 cmd_reg |= (USBCMD_REG_HC_RUN | USBCMD_REG_MAXPKT_64 |
525 525 USBCMD_REG_CONFIG_FLAG);
526 526
527 527 Set_OpReg16(USBCMD, cmd_reg);
528 528
529 529 /*
530 530 * Verify the Command and interrupt enable registers,
531 531 * a sanity check whether actually initialized or not
532 532 */
533 533 cmd_reg = Get_OpReg16(USBCMD);
534 534
535 535 if (!(cmd_reg & (USBCMD_REG_HC_RUN | USBCMD_REG_MAXPKT_64 |
536 536 USBCMD_REG_CONFIG_FLAG))) {
537 537 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
538 538 "uhci_init_ctlr: Controller initialization failed");
539 539 mutex_exit(&uhcip->uhci_int_mutex);
540 540
541 541 return (USB_FAILURE);
542 542 }
543 543
544 544 /*
545 545 * Set the ioc bit of the isoc intr td. This enables
546 546 * the generation of an interrupt for every 1024 frames.
547 547 */
548 548 SetTD_ioc(uhcip, uhcip->uhci_isoc_td, 1);
549 549
550 550 /* Set host controller soft state to operational */
551 551 uhcip->uhci_hc_soft_state = UHCI_CTLR_OPERATIONAL_STATE;
552 552 mutex_exit(&uhcip->uhci_int_mutex);
553 553
554 554 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
555 555 "uhci_init_ctlr: Completed");
556 556
557 557 return (USB_SUCCESS);
558 558 }
559 559
560 560
561 561 /*
562 562 * uhci_uninit_ctlr:
563 563 * uninitialize the Host Controller (HC).
564 564 */
565 565 void
566 566 uhci_uninit_ctlr(uhci_state_t *uhcip)
567 567 {
568 568 if (uhcip->uhci_regs_handle) {
569 569 /* Disable all the interrupts. */
570 570 Set_OpReg16(USBINTR, DISABLE_ALL_INTRS);
571 571
572 572 /* Complete the current transaction and then halt. */
573 573 Set_OpReg16(USBCMD, 0);
574 574
575 575 /* Wait for sometime */
576 576 mutex_exit(&uhcip->uhci_int_mutex);
577 577 delay(drv_usectohz(UHCI_TIMEWAIT));
578 578 mutex_enter(&uhcip->uhci_int_mutex);
579 579 }
580 580 }
581 581
582 582
583 583 /*
584 584 * uhci_map_regs:
585 585 * The Host Controller (HC) contains a set of on-chip operational
586 586 * registers and which should be mapped into a non-cacheable
587 587 * portion of the system addressable space.
588 588 */
589 589 int
590 590 uhci_map_regs(uhci_state_t *uhcip)
591 591 {
592 592 dev_info_t *dip = uhcip->uhci_dip;
593 593 int index;
594 594 uint32_t regs_prop_len;
595 595 int32_t *regs_list;
596 596 uint16_t command_reg;
597 597 ddi_device_acc_attr_t attr;
598 598
599 599 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, "uhci_map_regs:");
600 600
601 601 /* The host controller will be little endian */
602 602 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
603 603 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
604 604 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
605 605
606 606 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, uhcip->uhci_dip,
607 607 DDI_PROP_DONTPASS, "reg", ®s_list, ®s_prop_len) !=
608 608 DDI_PROP_SUCCESS) {
609 609
610 610 return (USB_FAILURE);
611 611 }
612 612
613 613 for (index = 0; index * 5 < regs_prop_len; index++) {
614 614 if (regs_list[index * 5] & UHCI_PROP_MASK) {
615 615 break;
616 616 }
617 617 }
618 618
619 619 /*
620 620 * Deallocate the memory allocated by the ddi_prop_lookup_int_array
621 621 */
622 622 ddi_prop_free(regs_list);
623 623
624 624 if (index * 5 >= regs_prop_len) {
625 625
626 626 return (USB_FAILURE);
627 627 }
628 628
629 629 /* Map in operational registers */
630 630 if (ddi_regs_map_setup(dip, index, (caddr_t *)&uhcip->uhci_regsp,
631 631 0, sizeof (hc_regs_t), &attr, &uhcip->uhci_regs_handle) !=
632 632 DDI_SUCCESS) {
633 633 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
634 634 "ddi_regs_map_setup: failed");
635 635
636 636 return (USB_FAILURE);
637 637 }
638 638
639 639 if (pci_config_setup(dip, &uhcip->uhci_config_handle) != DDI_SUCCESS) {
640 640 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
641 641 "uhci_map_regs: Config error");
642 642
643 643 return (USB_FAILURE);
644 644 }
645 645
646 646 /* Make sure Memory Access Enable and Master Enable are set */
647 647 command_reg = pci_config_get16(uhcip->uhci_config_handle,
648 648 PCI_CONF_COMM);
649 649 if (!(command_reg & (PCI_COMM_MAE | PCI_COMM_ME))) {
650 650 USB_DPRINTF_L3(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
651 651 "uhci_map_regs: No MAE/ME");
652 652 }
653 653
654 654 command_reg |= PCI_COMM_MAE | PCI_COMM_ME;
655 655 pci_config_put16(uhcip->uhci_config_handle, PCI_CONF_COMM, command_reg);
656 656
657 657 /*
658 658 * Check whether I/O base address is configured and enabled.
659 659 */
660 660 if (!(command_reg & PCI_COMM_IO)) {
661 661 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
662 662 "I/O Base address access disabled");
663 663
664 664 return (USB_FAILURE);
665 665 }
666 666 /*
667 667 * Get the IO base address of the controller
668 668 */
669 669 uhcip->uhci_iobase = (pci_config_get16(uhcip->uhci_config_handle,
670 670 PCI_CONF_IOBASE) & PCI_CONF_IOBASE_MASK);
671 671
672 672 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
673 673 "uhci_map_regs: Completed");
674 674
675 675 return (USB_SUCCESS);
676 676 }
677 677
678 678
679 679 void
680 680 uhci_unmap_regs(uhci_state_t *uhcip)
681 681 {
682 682 /* Unmap the UHCI registers */
683 683 if (uhcip->uhci_regs_handle) {
684 684 /* Reset the host controller */
685 685 Set_OpReg16(USBCMD, USBCMD_REG_GBL_RESET);
686 686
687 687 ddi_regs_map_free(&uhcip->uhci_regs_handle);
688 688 }
689 689
690 690 if (uhcip->uhci_config_handle) {
691 691 pci_config_teardown(&uhcip->uhci_config_handle);
692 692 }
693 693 }
694 694
695 695
696 696 /*
697 697 * uhci_set_dma_attributes:
698 698 * Set the limits in the DMA attributes structure. Most of the values used
699 699 * in the DMA limit structres are the default values as specified by the
700 700 * Writing PCI device drivers document.
701 701 */
702 702 void
703 703 uhci_set_dma_attributes(uhci_state_t *uhcip)
704 704 {
705 705 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
706 706 "uhci_set_dma_attributes:");
707 707
708 708 /* Initialize the DMA attributes */
709 709 uhcip->uhci_dma_attr.dma_attr_version = DMA_ATTR_V0;
710 710 uhcip->uhci_dma_attr.dma_attr_addr_lo = 0x00000000ull;
711 711 uhcip->uhci_dma_attr.dma_attr_addr_hi = 0xfffffff0ull;
712 712
713 713 /* 32 bit addressing */
714 714 uhcip->uhci_dma_attr.dma_attr_count_max = 0xffffffull;
715 715
716 716 /*
717 717 * Setting the dam_att_align to 512, some times fails the
718 718 * binding handle. I dont know why ? But setting to 16 will
719 719 * be right for our case (16 byte alignment required per
720 720 * UHCI spec for TD descriptors).
721 721 */
722 722
723 723 /* 16 byte alignment */
724 724 uhcip->uhci_dma_attr.dma_attr_align = 0x10;
725 725
726 726 /*
727 727 * Since PCI specification is byte alignment, the
728 728 * burstsize field should be set to 1 for PCI devices.
729 729 */
730 730 uhcip->uhci_dma_attr.dma_attr_burstsizes = 0x1;
731 731
732 732 uhcip->uhci_dma_attr.dma_attr_minxfer = 0x1;
733 733 uhcip->uhci_dma_attr.dma_attr_maxxfer = 0xffffffull;
734 734 uhcip->uhci_dma_attr.dma_attr_seg = 0xffffffffull;
735 735 uhcip->uhci_dma_attr.dma_attr_sgllen = 1;
736 736 uhcip->uhci_dma_attr.dma_attr_granular = 1;
737 737 uhcip->uhci_dma_attr.dma_attr_flags = 0;
738 738 }
739 739
740 740
741 741 uint_t
742 742 pow_2(uint_t x)
743 743 {
744 744 return ((x == 0) ? 1 : (1 << x));
745 745 }
746 746
747 747
748 748 uint_t
749 749 log_2(uint_t x)
750 750 {
751 751 int ret_val = 0;
752 752
753 753 while (x != 1) {
754 754 ret_val++;
755 755 x = x >> 1;
756 756 }
757 757
758 758 return (ret_val);
759 759 }
760 760
761 761
762 762 /*
763 763 * uhci_obtain_state:
764 764 */
765 765 uhci_state_t *
766 766 uhci_obtain_state(dev_info_t *dip)
767 767 {
768 768 int instance = ddi_get_instance(dip);
769 769 uhci_state_t *state = ddi_get_soft_state(uhci_statep, instance);
770 770
771 771 ASSERT(state != NULL);
772 772
773 773 return (state);
774 774 }
775 775
776 776
777 777 /*
778 778 * uhci_alloc_hcdi_ops:
779 779 * The HCDI interfaces or entry points are the software interfaces used by
780 780 * the Universal Serial Bus Driver (USBA) to access the services of the
781 781 * Host Controller Driver (HCD). During HCD initialization, inform USBA
782 782 * about all available HCDI interfaces or entry points.
783 783 */
784 784 usba_hcdi_ops_t *
785 785 uhci_alloc_hcdi_ops(uhci_state_t *uhcip)
786 786 {
787 787 usba_hcdi_ops_t *hcdi_ops;
788 788
789 789 USB_DPRINTF_L4(PRINT_MASK_HCDI, uhcip->uhci_log_hdl,
790 790 "uhci_alloc_hcdi_ops:");
791 791
792 792 hcdi_ops = usba_alloc_hcdi_ops();
793 793
794 794 hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION_1;
795 795
796 796 hcdi_ops->usba_hcdi_pipe_open = uhci_hcdi_pipe_open;
797 797 hcdi_ops->usba_hcdi_pipe_close = uhci_hcdi_pipe_close;
798 798 hcdi_ops->usba_hcdi_pipe_reset = uhci_hcdi_pipe_reset;
799 799 hcdi_ops->usba_hcdi_pipe_reset_data_toggle =
800 800 uhci_hcdi_pipe_reset_data_toggle;
801 801
802 802 hcdi_ops->usba_hcdi_pipe_ctrl_xfer = uhci_hcdi_pipe_ctrl_xfer;
803 803 hcdi_ops->usba_hcdi_pipe_bulk_xfer = uhci_hcdi_pipe_bulk_xfer;
804 804 hcdi_ops->usba_hcdi_pipe_intr_xfer = uhci_hcdi_pipe_intr_xfer;
805 805 hcdi_ops->usba_hcdi_pipe_isoc_xfer = uhci_hcdi_pipe_isoc_xfer;
806 806
807 807 hcdi_ops->usba_hcdi_bulk_transfer_size = uhci_hcdi_bulk_transfer_size;
808 808 hcdi_ops->usba_hcdi_pipe_stop_intr_polling =
809 809 uhci_hcdi_pipe_stop_intr_polling;
810 810 hcdi_ops->usba_hcdi_pipe_stop_isoc_polling =
811 811 uhci_hcdi_pipe_stop_isoc_polling;
812 812
813 813 hcdi_ops->usba_hcdi_get_current_frame_number =
814 814 uhci_hcdi_get_current_frame_number;
815 815 hcdi_ops->usba_hcdi_get_max_isoc_pkts = uhci_hcdi_get_max_isoc_pkts;
816 816
817 817 hcdi_ops->usba_hcdi_console_input_init = uhci_hcdi_polled_input_init;
818 818 hcdi_ops->usba_hcdi_console_input_enter = uhci_hcdi_polled_input_enter;
819 819 hcdi_ops->usba_hcdi_console_read = uhci_hcdi_polled_read;
820 820 hcdi_ops->usba_hcdi_console_input_exit = uhci_hcdi_polled_input_exit;
821 821 hcdi_ops->usba_hcdi_console_input_fini = uhci_hcdi_polled_input_fini;
822 822
823 823 hcdi_ops->usba_hcdi_console_output_init = uhci_hcdi_polled_output_init;
824 824 hcdi_ops->usba_hcdi_console_output_enter =
825 825 uhci_hcdi_polled_output_enter;
826 826 hcdi_ops->usba_hcdi_console_write = uhci_hcdi_polled_write;
827 827 hcdi_ops->usba_hcdi_console_output_exit = uhci_hcdi_polled_output_exit;
828 828 hcdi_ops->usba_hcdi_console_output_fini = uhci_hcdi_polled_output_fini;
829 829
830 830 return (hcdi_ops);
831 831 }
832 832
833 833
834 834 /*
835 835 * uhci_init_frame_lst_table :
836 836 * Allocate the system memory and initialize Host Controller
837 837 * Frame list table area The starting of the Frame list Table
838 838 * area must be 4096 byte aligned.
839 839 */
840 840 static int
841 841 uhci_init_frame_lst_table(dev_info_t *dip, uhci_state_t *uhcip)
842 842 {
843 843 int result;
844 844 uint_t ccount;
845 845 size_t real_length;
846 846 ddi_device_acc_attr_t dev_attr;
847 847
848 848 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
849 849
850 850 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
851 851 "uhci_init_frame_lst_table:");
852 852
853 853 /* The host controller will be little endian */
854 854 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
855 855 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
856 856 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
857 857
858 858 /* 4K alignment required */
859 859 uhcip->uhci_dma_attr.dma_attr_align = 0x1000;
860 860
861 861 /* Create space for the HCCA block */
862 862 if (ddi_dma_alloc_handle(dip, &uhcip->uhci_dma_attr, DDI_DMA_SLEEP,
863 863 0, &uhcip->uhci_flt_dma_handle) != DDI_SUCCESS) {
864 864
865 865 return (USB_FAILURE);
866 866 }
867 867
868 868 /* Reset to default 16 bytes */
869 869 uhcip->uhci_dma_attr.dma_attr_align = 0x10;
870 870
871 871 if (ddi_dma_mem_alloc(uhcip->uhci_flt_dma_handle,
872 872 SIZE_OF_FRAME_LST_TABLE, &dev_attr, DDI_DMA_CONSISTENT,
873 873 DDI_DMA_SLEEP, 0, (caddr_t *)&uhcip->uhci_frame_lst_tablep,
874 874 &real_length, &uhcip->uhci_flt_mem_handle)) {
875 875
876 876 return (USB_FAILURE);
877 877 }
878 878
879 879 /* Map the whole Frame list base area into the I/O address space */
880 880 result = ddi_dma_addr_bind_handle(uhcip->uhci_flt_dma_handle,
881 881 NULL, (caddr_t)uhcip->uhci_frame_lst_tablep, real_length,
882 882 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
883 883 &uhcip->uhci_flt_cookie, &ccount);
884 884
885 885 if (result == DDI_DMA_MAPPED) {
886 886 /* The cookie count should be 1 */
887 887 if (ccount != 1) {
888 888 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
889 889 "uhci_init_frame_list_table: More than 1 cookie");
890 890
891 891 return (USB_FAILURE);
892 892 }
893 893 } else {
894 894 uhci_decode_ddi_dma_addr_bind_handle_result(uhcip, result);
895 895
896 896 return (USB_FAILURE);
897 897 }
898 898
899 899 uhcip->uhci_dma_addr_bind_flag |= UHCI_FLA_POOL_BOUND;
900 900
901 901 bzero((void *)uhcip->uhci_frame_lst_tablep, real_length);
902 902
903 903 /* Initialize the interrupt lists */
904 904 uhci_build_interrupt_lattice(uhcip);
905 905
906 906 return (USB_SUCCESS);
907 907 }
908 908
909 909
910 910 /*
911 911 * uhci_alloc_queue_head:
912 912 * Allocate a queue head
913 913 */
914 914 queue_head_t *
915 915 uhci_alloc_queue_head(uhci_state_t *uhcip)
916 916 {
917 917 int index;
918 918 uhci_td_t *dummy_td;
919 919 queue_head_t *queue_head;
920 920
921 921 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
922 922 "uhci_alloc_queue_head");
923 923
924 924 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
925 925
926 926 /* Allocate a dummy td first. */
927 927 if ((dummy_td = uhci_allocate_td_from_pool(uhcip)) == NULL) {
928 928
929 929 USB_DPRINTF_L2(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
930 930 "uhci_alloc_queue_head: allocate td from pool failed");
931 931
932 932 return (NULL);
933 933 }
934 934
935 935 /*
936 936 * The first 63 queue heads in the Queue Head (QH)
937 937 * buffer pool are reserved for building interrupt lattice
938 938 * tree. Search for a blank Queue head in the QH buffer pool.
939 939 */
940 940 for (index = NUM_STATIC_NODES; index < uhci_qh_pool_size; index++) {
941 941 if (uhcip->uhci_qh_pool_addr[index].qh_flag ==
942 942 QUEUE_HEAD_FLAG_FREE) {
943 943 break;
944 944 }
945 945 }
946 946
947 947 USB_DPRINTF_L3(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
948 948 "uhci_alloc_queue_head: Allocated %d", index);
949 949
950 950 if (index == uhci_qh_pool_size) {
951 951 USB_DPRINTF_L2(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
952 952 "uhci_alloc_queue_head: All QH exhausted");
953 953
954 954 /* Free the dummy td allocated for this qh. */
955 955 dummy_td->flag = TD_FLAG_FREE;
956 956
957 957 return (NULL);
958 958 }
959 959
960 960 queue_head = &uhcip->uhci_qh_pool_addr[index];
961 961 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
962 962 "uhci_alloc_queue_head: Allocated address 0x%p",
963 963 (void *)queue_head);
964 964
965 965 bzero((void *)queue_head, sizeof (queue_head_t));
966 966 SetQH32(uhcip, queue_head->link_ptr, HC_END_OF_LIST);
967 967 SetQH32(uhcip, queue_head->element_ptr, HC_END_OF_LIST);
968 968 queue_head->prev_qh = NULL;
969 969 queue_head->qh_flag = QUEUE_HEAD_FLAG_BUSY;
970 970
971 971 bzero((char *)dummy_td, sizeof (uhci_td_t));
972 972 queue_head->td_tailp = dummy_td;
973 973 SetQH32(uhcip, queue_head->element_ptr, TD_PADDR(dummy_td));
974 974
975 975 return (queue_head);
976 976 }
977 977
978 978
979 979 /*
980 980 * uhci_allocate_bandwidth:
981 981 * Figure out whether or not this interval may be supported. Return
982 982 * the index into the lattice if it can be supported. Return
983 983 * allocation failure if it can not be supported.
984 984 */
985 985 int
986 986 uhci_allocate_bandwidth(
987 987 uhci_state_t *uhcip,
988 988 usba_pipe_handle_data_t *pipe_handle,
989 989 uint_t *node)
990 990 {
991 991 int bandwidth; /* Requested bandwidth */
992 992 uint_t min, min_index;
993 993 uint_t i;
994 994 uint_t height; /* Bandwidth's height in the tree */
995 995 uint_t leftmost;
996 996 uint_t length;
997 997 uint32_t paddr;
998 998 queue_head_t *tmp_qh;
999 999 usb_ep_descr_t *endpoint = &pipe_handle->p_ep;
1000 1000
1001 1001 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
1002 1002
1003 1003 /*
1004 1004 * Calculate the length in bytes of a transaction on this
1005 1005 * periodic endpoint.
1006 1006 */
1007 1007 mutex_enter(&pipe_handle->p_usba_device->usb_mutex);
1008 1008
1009 1009 length = uhci_compute_total_bandwidth(endpoint,
1010 1010 pipe_handle->p_usba_device->usb_port_status);
1011 1011 mutex_exit(&pipe_handle->p_usba_device->usb_mutex);
1012 1012
1013 1013 /*
1014 1014 * If the length in bytes plus the allocated bandwidth exceeds
1015 1015 * the maximum, return bandwidth allocation failure.
1016 1016 */
1017 1017 if ((length + uhcip->uhci_bandwidth_intr_min +
1018 1018 uhcip->uhci_bandwidth_isoch_sum) > (MAX_PERIODIC_BANDWIDTH)) {
1019 1019 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1020 1020 "uhci_allocate_bandwidth: "
1021 1021 "Reached maximum bandwidth value and cannot allocate "
1022 1022 "bandwidth for a given Interrupt/Isoch endpoint");
1023 1023
1024 1024 return (USB_NO_BANDWIDTH);
1025 1025 }
1026 1026
1027 1027 /*
1028 1028 * ISOC xfers are not supported at this point type
1029 1029 */
1030 1030 if (UHCI_XFER_TYPE(endpoint) == USB_EP_ATTR_ISOCH) {
1031 1031 uhcip->uhci_bandwidth_isoch_sum += length;
1032 1032
1033 1033 return (USB_SUCCESS);
1034 1034 }
1035 1035
1036 1036 /*
1037 1037 * This is an interrupt endpoint.
1038 1038 * Adjust bandwidth to be a power of 2
1039 1039 */
1040 1040 mutex_enter(&pipe_handle->p_usba_device->usb_mutex);
1041 1041 bandwidth = uhci_bandwidth_adjust(uhcip, endpoint,
1042 1042 pipe_handle->p_usba_device->usb_port_status);
1043 1043 mutex_exit(&pipe_handle->p_usba_device->usb_mutex);
1044 1044
1045 1045 /*
1046 1046 * If this bandwidth can't be supported,
1047 1047 * return allocation failure.
1048 1048 */
1049 1049 if (bandwidth == USB_FAILURE) {
1050 1050
1051 1051 return (USB_FAILURE);
1052 1052 }
1053 1053
1054 1054 USB_DPRINTF_L3(PRINT_MASK_BW, uhcip->uhci_log_hdl,
1055 1055 "The new bandwidth is %d", bandwidth);
1056 1056
1057 1057 /* Find the leaf with the smallest allocated bandwidth */
1058 1058 min_index = 0;
1059 1059 min = uhcip->uhci_bandwidth[0];
1060 1060
1061 1061 for (i = 1; i < NUM_FRAME_LST_ENTRIES; i++) {
1062 1062 if (uhcip->uhci_bandwidth[i] < min) {
1063 1063 min_index = i;
1064 1064 min = uhcip->uhci_bandwidth[i];
1065 1065 }
1066 1066 }
1067 1067
1068 1068 USB_DPRINTF_L3(PRINT_MASK_BW, uhcip->uhci_log_hdl,
1069 1069 "The leaf with minimal bandwidth %d, "
1070 1070 "The smallest bandwidth %d", min_index, min);
1071 1071
1072 1072 /*
1073 1073 * Find the index into the lattice given the
1074 1074 * leaf with the smallest allocated bandwidth.
1075 1075 */
1076 1076 height = uhci_lattice_height(bandwidth);
1077 1077 USB_DPRINTF_L3(PRINT_MASK_BW, uhcip->uhci_log_hdl,
1078 1078 "The height is %d", height);
1079 1079
1080 1080 *node = uhci_tree_bottom_nodes[min_index];
1081 1081
1082 1082 /* check if there are isocs TDs scheduled for this frame */
1083 1083 if (uhcip->uhci_isoc_q_tailp[*node]) {
1084 1084 paddr = (uhcip->uhci_isoc_q_tailp[*node]->link_ptr &
1085 1085 FRAME_LST_PTR_MASK);
1086 1086 } else {
1087 1087 paddr = (uhcip->uhci_frame_lst_tablep[*node] &
1088 1088 FRAME_LST_PTR_MASK);
1089 1089 }
1090 1090
1091 1091 tmp_qh = QH_VADDR(paddr);
1092 1092 *node = tmp_qh->node;
1093 1093 for (i = 0; i < height; i++) {
1094 1094 *node = uhci_lattice_parent(*node);
1095 1095 }
1096 1096
1097 1097 USB_DPRINTF_L3(PRINT_MASK_BW, uhcip->uhci_log_hdl,
1098 1098 "The real node is %d", *node);
1099 1099
1100 1100 /*
1101 1101 * Find the leftmost leaf in the subtree specified by the node.
1102 1102 */
1103 1103 leftmost = uhci_leftmost_leaf(*node, height);
1104 1104 USB_DPRINTF_L3(PRINT_MASK_BW, uhcip->uhci_log_hdl,
1105 1105 "Leftmost %d", leftmost);
1106 1106
1107 1107 for (i = leftmost; i < leftmost +
1108 1108 (NUM_FRAME_LST_ENTRIES/bandwidth); i ++) {
1109 1109
1110 1110 if ((length + uhcip->uhci_bandwidth_isoch_sum +
1111 1111 uhcip->uhci_bandwidth[i]) > MAX_PERIODIC_BANDWIDTH) {
1112 1112
1113 1113 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1114 1114 "uhci_allocate_bandwidth: "
1115 1115 "Reached maximum bandwidth value and cannot "
1116 1116 "allocate bandwidth for Interrupt endpoint");
1117 1117
1118 1118 return (USB_NO_BANDWIDTH);
1119 1119 }
1120 1120 }
1121 1121
1122 1122 /*
1123 1123 * All the leaves for this node must be updated with the bandwidth.
1124 1124 */
1125 1125 for (i = leftmost; i < leftmost +
1126 1126 (NUM_FRAME_LST_ENTRIES/bandwidth); i ++) {
1127 1127 uhcip->uhci_bandwidth[i] += length;
1128 1128 }
1129 1129
1130 1130 /* Find the leaf with the smallest allocated bandwidth */
1131 1131 min_index = 0;
1132 1132 min = uhcip->uhci_bandwidth[0];
1133 1133
1134 1134 for (i = 1; i < NUM_FRAME_LST_ENTRIES; i++) {
1135 1135 if (uhcip->uhci_bandwidth[i] < min) {
1136 1136 min_index = i;
1137 1137 min = uhcip->uhci_bandwidth[i];
1138 1138 }
1139 1139 }
1140 1140
1141 1141 /* Save the minimum for later use */
1142 1142 uhcip->uhci_bandwidth_intr_min = min;
1143 1143
1144 1144 return (USB_SUCCESS);
1145 1145 }
1146 1146
1147 1147
1148 1148 /*
1149 1149 * uhci_deallocate_bandwidth:
1150 1150 * Deallocate bandwidth for the given node in the lattice
1151 1151 * and the length of transfer.
1152 1152 */
1153 1153 void
1154 1154 uhci_deallocate_bandwidth(uhci_state_t *uhcip,
1155 1155 usba_pipe_handle_data_t *pipe_handle)
1156 1156 {
1157 1157 uint_t bandwidth;
1158 1158 uint_t height;
1159 1159 uint_t leftmost;
1160 1160 uint_t i;
1161 1161 uint_t min;
1162 1162 usb_ep_descr_t *endpoint = &pipe_handle->p_ep;
1163 1163 uint_t node, length;
1164 1164 uhci_pipe_private_t *pp =
1165 1165 (uhci_pipe_private_t *)pipe_handle->p_hcd_private;
1166 1166
1167 1167 /* This routine is protected by the uhci_int_mutex */
1168 1168 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
1169 1169
1170 1170 /* Obtain the length */
1171 1171 mutex_enter(&pipe_handle->p_usba_device->usb_mutex);
1172 1172 length = uhci_compute_total_bandwidth(endpoint,
1173 1173 pipe_handle->p_usba_device->usb_port_status);
1174 1174 mutex_exit(&pipe_handle->p_usba_device->usb_mutex);
1175 1175
1176 1176 /*
1177 1177 * If this is an isochronous endpoint, just delete endpoint's
1178 1178 * bandwidth from the total allocated isochronous bandwidth.
1179 1179 */
1180 1180 if (UHCI_XFER_TYPE(endpoint) == USB_EP_ATTR_ISOCH) {
1181 1181 uhcip->uhci_bandwidth_isoch_sum -= length;
1182 1182
1183 1183 return;
1184 1184 }
1185 1185
1186 1186 /* Obtain the node */
1187 1187 node = pp->pp_node;
1188 1188
1189 1189 /* Adjust bandwidth to be a power of 2 */
1190 1190 mutex_enter(&pipe_handle->p_usba_device->usb_mutex);
1191 1191 bandwidth = uhci_bandwidth_adjust(uhcip, endpoint,
1192 1192 pipe_handle->p_usba_device->usb_port_status);
1193 1193 mutex_exit(&pipe_handle->p_usba_device->usb_mutex);
1194 1194
1195 1195 /* Find the height in the tree */
1196 1196 height = uhci_lattice_height(bandwidth);
1197 1197
1198 1198 /*
1199 1199 * Find the leftmost leaf in the subtree specified by the node
1200 1200 */
1201 1201 leftmost = uhci_leftmost_leaf(node, height);
1202 1202
1203 1203 /* Delete the bandwith from the appropriate lists */
1204 1204 for (i = leftmost; i < leftmost + (NUM_FRAME_LST_ENTRIES/bandwidth);
1205 1205 i ++) {
1206 1206 uhcip->uhci_bandwidth[i] -= length;
1207 1207 }
1208 1208
1209 1209 min = uhcip->uhci_bandwidth[0];
1210 1210
1211 1211 /* Recompute the minimum */
1212 1212 for (i = 1; i < NUM_FRAME_LST_ENTRIES; i++) {
1213 1213 if (uhcip->uhci_bandwidth[i] < min) {
1214 1214 min = uhcip->uhci_bandwidth[i];
1215 1215 }
1216 1216 }
1217 1217
1218 1218 /* Save the minimum for later use */
1219 1219 uhcip->uhci_bandwidth_intr_min = min;
1220 1220 }
1221 1221
1222 1222
1223 1223 /*
1224 1224 * uhci_compute_total_bandwidth:
1225 1225 *
1226 1226 * Given a periodic endpoint (interrupt or isochronous) determine the total
1227 1227 * bandwidth for one transaction. The UHCI host controller traverses the
1228 1228 * endpoint descriptor lists on a first-come-first-serve basis. When the HC
1229 1229 * services an endpoint, only a single transaction attempt is made. The HC
1230 1230 * moves to the next Endpoint Descriptor after the first transaction attempt
1231 1231 * rather than finishing the entire Transfer Descriptor. Therefore, when a
1232 1232 * Transfer Descriptor is inserted into the lattice, we will only count the
1233 1233 * number of bytes for one transaction.
1234 1234 *
1235 1235 * The following are the formulas used for calculating bandwidth in terms
1236 1236 * bytes and it is for the single USB full speed and low speed transaction
1237 1237 * respectively. The protocol overheads will be different for each of type
1238 1238 * of USB transfer and all these formulas & protocol overheads are derived
1239 1239 * from the 5.9.3 section of USB Specification & with the help of Bandwidth
1240 1240 * Analysis white paper which is posted on the USB developer forum.
1241 1241 *
1242 1242 * Full-Speed:
1243 1243 * Protocol overhead + ((MaxPacketSize * 7)/6 ) + Host_Delay
1244 1244 *
1245 1245 * Low-Speed:
1246 1246 * Protocol overhead + Hub LS overhead +
1247 1247 * (Low-Speed clock * ((MaxPacketSize * 7)/6 )) + Host_Delay
1248 1248 */
1249 1249 static uint_t
1250 1250 uhci_compute_total_bandwidth(usb_ep_descr_t *endpoint,
1251 1251 usb_port_status_t port_status)
1252 1252 {
1253 1253 uint_t bandwidth;
1254 1254 ushort_t MaxPacketSize = endpoint->wMaxPacketSize;
1255 1255
1256 1256 /* Add Host Controller specific delay to required bandwidth */
1257 1257 bandwidth = HOST_CONTROLLER_DELAY;
1258 1258
1259 1259 /* Add bit-stuffing overhead */
1260 1260 MaxPacketSize = (ushort_t)((MaxPacketSize * 7) / 6);
1261 1261
1262 1262 /* Low Speed interrupt transaction */
1263 1263 if (port_status == USBA_LOW_SPEED_DEV) {
1264 1264 /* Low Speed interrupt transaction */
1265 1265 bandwidth += (LOW_SPEED_PROTO_OVERHEAD +
1266 1266 HUB_LOW_SPEED_PROTO_OVERHEAD +
1267 1267 (LOW_SPEED_CLOCK * MaxPacketSize));
1268 1268 } else {
1269 1269 /* Full Speed transaction */
1270 1270 bandwidth += MaxPacketSize;
1271 1271
1272 1272 if (UHCI_XFER_TYPE(endpoint) == USB_EP_ATTR_INTR) {
1273 1273 /* Full Speed interrupt transaction */
1274 1274 bandwidth += FS_NON_ISOC_PROTO_OVERHEAD;
1275 1275 } else {
1276 1276 /* Isochronus and input transaction */
1277 1277 if (UHCI_XFER_DIR(endpoint) == USB_EP_DIR_IN) {
1278 1278 bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD;
1279 1279 } else {
1280 1280 /* Isochronus and output transaction */
1281 1281 bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD;
1282 1282 }
1283 1283 }
1284 1284 }
1285 1285
1286 1286 return (bandwidth);
1287 1287 }
1288 1288
1289 1289
1290 1290 /*
1291 1291 * uhci_bandwidth_adjust:
1292 1292 */
1293 1293 static int
1294 1294 uhci_bandwidth_adjust(
1295 1295 uhci_state_t *uhcip,
1296 1296 usb_ep_descr_t *endpoint,
1297 1297 usb_port_status_t port_status)
1298 1298 {
1299 1299 int i = 0;
1300 1300 uint_t interval;
1301 1301
1302 1302 /*
1303 1303 * Get the polling interval from the endpoint descriptor
1304 1304 */
1305 1305 interval = endpoint->bInterval;
1306 1306
1307 1307 /*
1308 1308 * The bInterval value in the endpoint descriptor can range
1309 1309 * from 1 to 255ms. The interrupt lattice has 32 leaf nodes,
1310 1310 * and the host controller cycles through these nodes every
1311 1311 * 32ms. The longest polling interval that the controller
1312 1312 * supports is 32ms.
1313 1313 */
1314 1314
1315 1315 /*
1316 1316 * Return an error if the polling interval is less than 1ms
1317 1317 * and greater than 255ms
1318 1318 */
1319 1319 if ((interval < MIN_POLL_INTERVAL) || (interval > MAX_POLL_INTERVAL)) {
1320 1320 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1321 1321 "uhci_bandwidth_adjust: Endpoint's poll interval must be "
1322 1322 "between %d and %d ms", MIN_POLL_INTERVAL,
1323 1323 MAX_POLL_INTERVAL);
1324 1324
1325 1325 return (USB_FAILURE);
1326 1326 }
1327 1327
1328 1328 /*
1329 1329 * According USB Specifications, a full-speed endpoint can
1330 1330 * specify a desired polling interval 1ms to 255ms and a low
1331 1331 * speed endpoints are limited to specifying only 10ms to
1332 1332 * 255ms. But some old keyboards & mice uses polling interval
1333 1333 * of 8ms. For compatibility purpose, we are using polling
1334 1334 * interval between 8ms & 255ms for low speed endpoints.
1335 1335 */
1336 1336 if ((port_status == USBA_LOW_SPEED_DEV) &&
1337 1337 (interval < MIN_LOW_SPEED_POLL_INTERVAL)) {
1338 1338 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1339 1339 "uhci_bandwidth_adjust: Low speed endpoint's poll interval "
1340 1340 "must be >= %d ms, adjusted",
1341 1341 MIN_LOW_SPEED_POLL_INTERVAL);
1342 1342
1343 1343 interval = MIN_LOW_SPEED_POLL_INTERVAL;
1344 1344 }
1345 1345
1346 1346 /*
1347 1347 * If polling interval is greater than 32ms,
1348 1348 * adjust polling interval equal to 32ms.
1349 1349 */
1350 1350 if (interval > 32) {
1351 1351 interval = 32;
1352 1352 }
1353 1353
1354 1354 /*
1355 1355 * Find the nearest power of 2 that's less
1356 1356 * than interval.
1357 1357 */
1358 1358 while ((pow_2(i)) <= interval) {
1359 1359 i++;
1360 1360 }
1361 1361
1362 1362 return (pow_2((i - 1)));
1363 1363 }
1364 1364
1365 1365
1366 1366 /*
1367 1367 * uhci_lattice_height:
1368 1368 * Given the requested bandwidth, find the height in the tree at
1369 1369 * which the nodes for this bandwidth fall. The height is measured
1370 1370 * as the number of nodes from the leaf to the level specified by
1371 1371 * bandwidth The root of the tree is at height TREE_HEIGHT.
1372 1372 */
1373 1373 static uint_t
1374 1374 uhci_lattice_height(uint_t bandwidth)
1375 1375 {
1376 1376 return (TREE_HEIGHT - (log_2(bandwidth)));
1377 1377 }
1378 1378
1379 1379
1380 1380 static uint_t
1381 1381 uhci_lattice_parent(uint_t node)
1382 1382 {
1383 1383 return (((node % 2) == 0) ? ((node/2) - 1) : (node/2));
1384 1384 }
1385 1385
1386 1386
1387 1387 /*
1388 1388 * uhci_leftmost_leaf:
1389 1389 * Find the leftmost leaf in the subtree specified by the node.
1390 1390 * Height refers to number of nodes from the bottom of the tree
1391 1391 * to the node, including the node.
1392 1392 */
1393 1393 static uint_t
1394 1394 uhci_leftmost_leaf(uint_t node, uint_t height)
1395 1395 {
1396 1396 node = pow_2(height + VIRTUAL_TREE_HEIGHT) * (node+1) -
1397 1397 NUM_FRAME_LST_ENTRIES;
1398 1398 return (node);
1399 1399 }
1400 1400
1401 1401
1402 1402 /*
1403 1403 * uhci_insert_qh:
1404 1404 * Add the Queue Head (QH) into the Host Controller's (HC)
1405 1405 * appropriate queue head list.
1406 1406 */
1407 1407 void
1408 1408 uhci_insert_qh(uhci_state_t *uhcip, usba_pipe_handle_data_t *ph)
1409 1409 {
1410 1410 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private;
1411 1411
1412 1412 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1413 1413 "uhci_insert_qh:");
1414 1414
1415 1415 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
1416 1416
1417 1417 switch (UHCI_XFER_TYPE(&ph->p_ep)) {
1418 1418 case USB_EP_ATTR_CONTROL:
1419 1419 uhci_insert_ctrl_qh(uhcip, pp);
1420 1420 break;
1421 1421 case USB_EP_ATTR_BULK:
1422 1422 uhci_insert_bulk_qh(uhcip, pp);
1423 1423 break;
1424 1424 case USB_EP_ATTR_INTR:
1425 1425 uhci_insert_intr_qh(uhcip, pp);
1426 1426 break;
1427 1427 case USB_EP_ATTR_ISOCH:
1428 1428 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
1429 1429 "uhci_insert_qh: Illegal request");
1430 1430 break;
1431 1431 }
1432 1432 }
1433 1433
1434 1434
1435 1435 /*
1436 1436 * uhci_insert_ctrl_qh:
1437 1437 * Insert a control QH into the Host Controller's (HC) control QH list.
1438 1438 */
1439 1439 static void
1440 1440 uhci_insert_ctrl_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp)
1441 1441 {
1442 1442 queue_head_t *qh = pp->pp_qh;
1443 1443
1444 1444 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1445 1445 "uhci_insert_ctrl_qh:");
1446 1446
1447 1447 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
1448 1448
1449 1449 if (uhcip->uhci_ctrl_xfers_q_head == uhcip->uhci_ctrl_xfers_q_tail) {
1450 1450 uhcip->uhci_ctrl_xfers_q_head->prev_qh = UHCI_INVALID_PTR;
1451 1451 }
1452 1452
1453 1453 SetQH32(uhcip, qh->link_ptr,
1454 1454 GetQH32(uhcip, uhcip->uhci_ctrl_xfers_q_tail->link_ptr));
1455 1455 qh->prev_qh = uhcip->uhci_ctrl_xfers_q_tail;
1456 1456 SetQH32(uhcip, uhcip->uhci_ctrl_xfers_q_tail->link_ptr,
1457 1457 QH_PADDR(qh) | HC_QUEUE_HEAD);
1458 1458 uhcip->uhci_ctrl_xfers_q_tail = qh;
1459 1459
1460 1460 }
1461 1461
1462 1462
1463 1463 /*
1464 1464 * uhci_insert_bulk_qh:
1465 1465 * Insert a bulk QH into the Host Controller's (HC) bulk QH list.
1466 1466 */
1467 1467 static void
1468 1468 uhci_insert_bulk_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp)
1469 1469 {
1470 1470 queue_head_t *qh = pp->pp_qh;
1471 1471
1472 1472 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1473 1473 "uhci_insert_bulk_qh:");
1474 1474
1475 1475 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
1476 1476
1477 1477 if (uhcip->uhci_bulk_xfers_q_head == uhcip->uhci_bulk_xfers_q_tail) {
1478 1478 uhcip->uhci_bulk_xfers_q_head->prev_qh = UHCI_INVALID_PTR;
1479 1479 } else if (uhcip->uhci_bulk_xfers_q_head->link_ptr ==
1480 1480 uhcip->uhci_bulk_xfers_q_tail->link_ptr) {
1481 1481
1482 1482 /* If there is already a loop, we should keep the loop. */
1483 1483 qh->link_ptr = uhcip->uhci_bulk_xfers_q_tail->link_ptr;
1484 1484 }
1485 1485
1486 1486 qh->prev_qh = uhcip->uhci_bulk_xfers_q_tail;
1487 1487 SetQH32(uhcip, uhcip->uhci_bulk_xfers_q_tail->link_ptr,
1488 1488 QH_PADDR(qh) | HC_QUEUE_HEAD);
1489 1489 uhcip->uhci_bulk_xfers_q_tail = qh;
1490 1490 }
1491 1491
1492 1492
1493 1493 /*
1494 1494 * uhci_insert_intr_qh:
1495 1495 * Insert a periodic Queue head i.e Interrupt queue head into the
1496 1496 * Host Controller's (HC) interrupt lattice tree.
1497 1497 */
1498 1498 static void
1499 1499 uhci_insert_intr_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp)
1500 1500 {
1501 1501 uint_t node = pp->pp_node; /* The appropriate node was */
1502 1502 /* found during the opening */
1503 1503 /* of the pipe. */
1504 1504 queue_head_t *qh = pp->pp_qh;
1505 1505 queue_head_t *next_lattice_qh, *lattice_qh;
1506 1506
1507 1507 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1508 1508 "uhci_insert_intr_qh:");
1509 1509
1510 1510 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
1511 1511
1512 1512 /* Find the lattice queue head */
1513 1513 lattice_qh = &uhcip->uhci_qh_pool_addr[node];
1514 1514 next_lattice_qh =
1515 1515 QH_VADDR(GetQH32(uhcip, lattice_qh->link_ptr) & QH_LINK_PTR_MASK);
1516 1516
1517 1517 next_lattice_qh->prev_qh = qh;
1518 1518 qh->link_ptr = lattice_qh->link_ptr;
1519 1519 qh->prev_qh = lattice_qh;
1520 1520 SetQH32(uhcip, lattice_qh->link_ptr, QH_PADDR(qh) | HC_QUEUE_HEAD);
1521 1521 pp->pp_data_toggle = 0;
1522 1522 }
1523 1523
1524 1524
1525 1525 /*
1526 1526 * uhci_insert_intr_td:
1527 1527 * Create a TD and a data buffer for an interrupt endpoint.
1528 1528 */
1529 1529 int
1530 1530 uhci_insert_intr_td(
1531 1531 uhci_state_t *uhcip,
1532 1532 usba_pipe_handle_data_t *ph,
1533 1533 usb_intr_req_t *req,
1534 1534 usb_flags_t flags)
1535 1535 {
1536 1536 int error, pipe_dir;
1537 1537 uint_t length, mps;
1538 1538 uint32_t buf_offs;
1539 1539 uhci_td_t *tmp_td;
1540 1540 usb_intr_req_t *intr_reqp;
1541 1541 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private;
1542 1542 uhci_trans_wrapper_t *tw;
1543 1543
1544 1544 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1545 1545 "uhci_insert_intr_td: req: 0x%p", (void *)req);
1546 1546
1547 1547 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
1548 1548
1549 1549 /* Get the interrupt pipe direction */
1550 1550 pipe_dir = UHCI_XFER_DIR(&ph->p_ep);
1551 1551
1552 1552 /* Get the current interrupt request pointer */
1553 1553 if (req) {
1554 1554 length = req->intr_len;
1555 1555 } else {
1556 1556 ASSERT(pipe_dir == USB_EP_DIR_IN);
1557 1557 length = (pp->pp_client_periodic_in_reqp) ?
1558 1558 (((usb_intr_req_t *)pp->
1559 1559 pp_client_periodic_in_reqp)->intr_len) :
1560 1560 ph->p_ep.wMaxPacketSize;
1561 1561 }
1562 1562
1563 1563 /* Check the size of interrupt request */
1564 1564 if (length > UHCI_MAX_TD_XFER_SIZE) {
1565 1565
1566 1566 /* the length shouldn't exceed 8K */
1567 1567 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1568 1568 "uhci_insert_intr_td: Intr request size 0x%x is "
1569 1569 "more than 0x%x", length, UHCI_MAX_TD_XFER_SIZE);
1570 1570
1571 1571 return (USB_INVALID_REQUEST);
1572 1572 }
1573 1573
1574 1574 USB_DPRINTF_L3(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1575 1575 "uhci_insert_intr_td: length: 0x%x", length);
1576 1576
1577 1577 /* Allocate a transaction wrapper */
1578 1578 if ((tw = uhci_create_transfer_wrapper(uhcip, pp, length, flags)) ==
1579 1579 NULL) {
1580 1580
1581 1581 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1582 1582 "uhci_insert_intr_td: TW allocation failed");
1583 1583
1584 1584 return (USB_NO_RESOURCES);
1585 1585 }
1586 1586
1587 1587 /*
1588 1588 * Initialize the callback and any callback
1589 1589 * data for when the td completes.
1590 1590 */
1591 1591 tw->tw_handle_td = uhci_handle_intr_td;
1592 1592 tw->tw_handle_callback_value = NULL;
1593 1593 tw->tw_direction = (pipe_dir == USB_EP_DIR_OUT) ?
1594 1594 PID_OUT : PID_IN;
1595 1595 tw->tw_curr_xfer_reqp = (usb_opaque_t)req;
1596 1596
1597 1597 /*
1598 1598 * If it is an Interrupt IN request and interrupt request is NULL,
1599 1599 * allocate the usb interrupt request structure for the current
1600 1600 * interrupt polling request.
1601 1601 */
1602 1602 if (tw->tw_direction == PID_IN) {
1603 1603 if ((error = uhci_allocate_periodic_in_resource(uhcip,
1604 1604 pp, tw, flags)) != USB_SUCCESS) {
1605 1605 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1606 1606 "uhci_insert_intr_td: Interrupt request structure "
1607 1607 "allocation failed");
1608 1608
1609 1609 /* free the transfer wrapper */
1610 1610 uhci_deallocate_tw(uhcip, pp, tw);
1611 1611
1612 1612 return (error);
1613 1613 }
1614 1614 }
1615 1615
1616 1616 intr_reqp = (usb_intr_req_t *)tw->tw_curr_xfer_reqp;
1617 1617 ASSERT(tw->tw_curr_xfer_reqp != NULL);
1618 1618
1619 1619 tw->tw_timeout_cnt = (intr_reqp->intr_attributes & USB_ATTRS_ONE_XFER) ?
1620 1620 intr_reqp->intr_timeout : 0;
1621 1621
1622 1622 /* DATA IN */
1623 1623 if (tw->tw_direction == PID_IN) {
1624 1624 /* Insert the td onto the queue head */
1625 1625 error = uhci_insert_hc_td(uhcip, 0,
1626 1626 length, pp, tw, PID_IN, intr_reqp->intr_attributes);
1627 1627
1628 1628 if (error != USB_SUCCESS) {
1629 1629
1630 1630 uhci_deallocate_periodic_in_resource(uhcip, pp, tw);
1631 1631 /* free the transfer wrapper */
1632 1632 uhci_deallocate_tw(uhcip, pp, tw);
1633 1633
1634 1634 return (USB_NO_RESOURCES);
1635 1635 }
1636 1636 tw->tw_bytes_xfered = 0;
1637 1637
1638 1638 return (USB_SUCCESS);
1639 1639 }
1640 1640
1641 1641 if (req->intr_len) {
1642 1642 /* DATA OUT */
1643 1643 ASSERT(req->intr_data != NULL);
1644 1644
1645 1645 /* Copy the data into the message */
1646 1646 ddi_rep_put8(tw->tw_accesshandle, req->intr_data->b_rptr,
1647 1647 (uint8_t *)tw->tw_buf, req->intr_len, DDI_DEV_AUTOINCR);
1648 1648 }
1649 1649
1650 1650 /* set tw->tw_claim flag, so that nobody else works on this tw. */
1651 1651 tw->tw_claim = UHCI_INTR_HDLR_CLAIMED;
1652 1652
1653 1653 mps = ph->p_ep.wMaxPacketSize;
1654 1654 buf_offs = 0;
1655 1655
1656 1656 /* Insert tds onto the queue head */
1657 1657 while (length > 0) {
1658 1658
1659 1659 error = uhci_insert_hc_td(uhcip, buf_offs,
1660 1660 (length > mps) ? mps : length,
1661 1661 pp, tw, PID_OUT,
1662 1662 intr_reqp->intr_attributes);
1663 1663
1664 1664 if (error != USB_SUCCESS) {
1665 1665 /* no resource. */
1666 1666 break;
1667 1667 }
1668 1668
1669 1669 if (length <= mps) {
1670 1670 /* inserted all data. */
1671 1671 length = 0;
1672 1672
1673 1673 } else {
1674 1674
1675 1675 buf_offs += mps;
1676 1676 length -= mps;
1677 1677 }
1678 1678 }
1679 1679
1680 1680 if (error != USB_SUCCESS) {
1681 1681
1682 1682 USB_DPRINTF_L2(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
1683 1683 "uhci_insert_intr_td: allocate td failed, free resource");
1684 1684
1685 1685 /* remove all the tds */
1686 1686 while (tw->tw_hctd_head != NULL) {
1687 1687 uhci_delete_td(uhcip, tw->tw_hctd_head);
1688 1688 }
1689 1689
1690 1690 tw->tw_claim = UHCI_NOT_CLAIMED;
1691 1691 uhci_deallocate_tw(uhcip, pp, tw);
1692 1692
1693 1693 return (error);
1694 1694 }
1695 1695
1696 1696 /* allow HC to xfer the tds of this tw */
1697 1697 tmp_td = tw->tw_hctd_head;
1698 1698 while (tmp_td != NULL) {
1699 1699
1700 1700 SetTD_status(uhcip, tmp_td, UHCI_TD_ACTIVE);
1701 1701 tmp_td = tmp_td->tw_td_next;
1702 1702 }
1703 1703
1704 1704 tw->tw_bytes_xfered = 0;
1705 1705 tw->tw_claim = UHCI_NOT_CLAIMED;
1706 1706
1707 1707 return (error);
1708 1708 }
1709 1709
1710 1710
1711 1711 /*
1712 1712 * uhci_create_transfer_wrapper:
1713 1713 * Create a Transaction Wrapper (TW) for non-isoc transfer types.
1714 1714 * This involves the allocating of DMA resources.
1715 1715 *
1716 1716 * For non-isoc transfers, one DMA handle and one DMA buffer are
1717 1717 * allocated per transfer. The DMA buffer may contain multiple
1718 1718 * DMA cookies and the cookies should meet certain alignment
1719 1719 * requirement to be able to fit in the multiple TDs. The alignment
1720 1720 * needs to ensure:
1721 1721 * 1. the size of a cookie be larger than max TD length (0x500)
1722 1722 * 2. the size of a cookie be a multiple of wMaxPacketSize of the
1723 1723 * ctrl/bulk pipes
1724 1724 *
1725 1725 * wMaxPacketSize for ctrl and bulk pipes may be 8, 16, 32 or 64 bytes.
1726 1726 * So the alignment should be a multiple of 64. wMaxPacketSize for intr
1727 1727 * pipes is a little different since it only specifies the max to be
1728 1728 * 64 bytes, but as long as an intr transfer is limited to max TD length,
1729 1729 * any alignment can work if the cookie size is larger than max TD length.
1730 1730 *
1731 1731 * Considering the above conditions, 2K alignment is used. 4K alignment
1732 1732 * should also be fine.
1733 1733 */
1734 1734 static uhci_trans_wrapper_t *
1735 1735 uhci_create_transfer_wrapper(
1736 1736 uhci_state_t *uhcip,
1737 1737 uhci_pipe_private_t *pp,
1738 1738 size_t length,
1739 1739 usb_flags_t usb_flags)
1740 1740 {
1741 1741 size_t real_length;
1742 1742 uhci_trans_wrapper_t *tw;
1743 1743 ddi_device_acc_attr_t dev_attr;
1744 1744 ddi_dma_attr_t dma_attr;
1745 1745 int kmem_flag;
1746 1746 int (*dmamem_wait)(caddr_t);
1747 1747 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle;
1748 1748
1749 1749 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1750 1750 "uhci_create_transfer_wrapper: length = 0x%lx flags = 0x%x",
1751 1751 length, usb_flags);
1752 1752
1753 1753 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
1754 1754
1755 1755 /* isochronous pipe should not call into this function */
1756 1756 if (UHCI_XFER_TYPE(&ph->p_ep) == USB_EP_ATTR_ISOCH) {
1757 1757
1758 1758 return (NULL);
1759 1759 }
1760 1760
1761 1761 /* SLEEP flag should not be used while holding mutex */
1762 1762 kmem_flag = KM_NOSLEEP;
1763 1763 dmamem_wait = DDI_DMA_DONTWAIT;
1764 1764
1765 1765 /* Allocate space for the transfer wrapper */
1766 1766 if ((tw = kmem_zalloc(sizeof (uhci_trans_wrapper_t), kmem_flag)) ==
1767 1767 NULL) {
1768 1768 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1769 1769 "uhci_create_transfer_wrapper: kmem_alloc failed");
1770 1770
1771 1771 return (NULL);
1772 1772 }
1773 1773
1774 1774 /* zero-length packet doesn't need to allocate dma memory */
1775 1775 if (length == 0) {
1776 1776
1777 1777 goto dmadone;
1778 1778 }
1779 1779
1780 1780 /* allow sg lists for transfer wrapper dma memory */
1781 1781 bcopy(&uhcip->uhci_dma_attr, &dma_attr, sizeof (ddi_dma_attr_t));
1782 1782 dma_attr.dma_attr_sgllen = UHCI_DMA_ATTR_SGLLEN;
1783 1783 dma_attr.dma_attr_align = UHCI_DMA_ATTR_ALIGN;
1784 1784
1785 1785 /* Store the transfer length */
1786 1786 tw->tw_length = length;
1787 1787
1788 1788 /* Allocate the DMA handle */
1789 1789 if (ddi_dma_alloc_handle(uhcip->uhci_dip, &dma_attr, dmamem_wait,
1790 1790 0, &tw->tw_dmahandle) != DDI_SUCCESS) {
1791 1791 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1792 1792 "uhci_create_transfer_wrapper: Alloc handle failed");
1793 1793 kmem_free(tw, sizeof (uhci_trans_wrapper_t));
1794 1794
1795 1795 return (NULL);
1796 1796 }
1797 1797
1798 1798 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
1799 1799 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
1800 1800 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
1801 1801
1802 1802 /* Allocate the memory */
1803 1803 if (ddi_dma_mem_alloc(tw->tw_dmahandle, tw->tw_length, &dev_attr,
1804 1804 DDI_DMA_CONSISTENT, dmamem_wait, NULL, (caddr_t *)&tw->tw_buf,
1805 1805 &real_length, &tw->tw_accesshandle) != DDI_SUCCESS) {
1806 1806 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1807 1807 "uhci_create_transfer_wrapper: dma_mem_alloc fail");
1808 1808 ddi_dma_free_handle(&tw->tw_dmahandle);
1809 1809 kmem_free(tw, sizeof (uhci_trans_wrapper_t));
1810 1810
1811 1811 return (NULL);
1812 1812 }
1813 1813
1814 1814 ASSERT(real_length >= length);
1815 1815
1816 1816 /* Bind the handle */
1817 1817 if (ddi_dma_addr_bind_handle(tw->tw_dmahandle, NULL,
1818 1818 (caddr_t)tw->tw_buf, real_length, DDI_DMA_RDWR|DDI_DMA_CONSISTENT,
1819 1819 dmamem_wait, NULL, &tw->tw_cookie, &tw->tw_ncookies) !=
1820 1820 DDI_DMA_MAPPED) {
1821 1821 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1822 1822 "uhci_create_transfer_wrapper: Bind handle failed");
1823 1823 ddi_dma_mem_free(&tw->tw_accesshandle);
1824 1824 ddi_dma_free_handle(&tw->tw_dmahandle);
1825 1825 kmem_free(tw, sizeof (uhci_trans_wrapper_t));
1826 1826
1827 1827 return (NULL);
1828 1828 }
1829 1829
1830 1830 tw->tw_cookie_idx = 0;
1831 1831 tw->tw_dma_offs = 0;
1832 1832
1833 1833 dmadone:
1834 1834 /*
1835 1835 * Only allow one wrapper to be added at a time. Insert the
1836 1836 * new transaction wrapper into the list for this pipe.
1837 1837 */
1838 1838 if (pp->pp_tw_head == NULL) {
1839 1839 pp->pp_tw_head = tw;
1840 1840 pp->pp_tw_tail = tw;
1841 1841 } else {
1842 1842 pp->pp_tw_tail->tw_next = tw;
1843 1843 pp->pp_tw_tail = tw;
1844 1844 ASSERT(tw->tw_next == NULL);
1845 1845 }
1846 1846
1847 1847 /* Store a back pointer to the pipe private structure */
1848 1848 tw->tw_pipe_private = pp;
1849 1849
1850 1850 /* Store the transfer type - synchronous or asynchronous */
1851 1851 tw->tw_flags = usb_flags;
1852 1852
1853 1853 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
1854 1854 "uhci_create_transfer_wrapper: tw = 0x%p, ncookies = %u",
1855 1855 (void *)tw, tw->tw_ncookies);
1856 1856
1857 1857 return (tw);
1858 1858 }
1859 1859
1860 1860
1861 1861 /*
1862 1862 * uhci_insert_hc_td:
1863 1863 * Insert a Transfer Descriptor (TD) on an QH.
1864 1864 */
1865 1865 int
1866 1866 uhci_insert_hc_td(
1867 1867 uhci_state_t *uhcip,
1868 1868 uint32_t buffer_offset,
1869 1869 size_t hcgtd_length,
1870 1870 uhci_pipe_private_t *pp,
1871 1871 uhci_trans_wrapper_t *tw,
1872 1872 uchar_t PID,
1873 1873 usb_req_attrs_t attrs)
1874 1874 {
1875 1875 uhci_td_t *td, *current_dummy;
1876 1876 queue_head_t *qh = pp->pp_qh;
1877 1877
1878 1878 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
1879 1879
1880 1880 if ((td = uhci_allocate_td_from_pool(uhcip)) == NULL) {
1881 1881
1882 1882 return (USB_NO_RESOURCES);
1883 1883 }
1884 1884
1885 1885 current_dummy = qh->td_tailp;
1886 1886
1887 1887 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
1888 1888 "uhci_insert_hc_td: td %p, attrs = 0x%x", (void *)td, attrs);
1889 1889
1890 1890 /*
1891 1891 * Fill in the current dummy td and
1892 1892 * add the new dummy to the end.
1893 1893 */
1894 1894 uhci_fill_in_td(uhcip, td, current_dummy, buffer_offset,
1895 1895 hcgtd_length, pp, PID, attrs, tw);
1896 1896
1897 1897 /*
1898 1898 * Allow HC hardware xfer the td, except interrupt out td.
1899 1899 */
1900 1900 if ((tw->tw_handle_td != uhci_handle_intr_td) || (PID != PID_OUT)) {
1901 1901
1902 1902 SetTD_status(uhcip, current_dummy, UHCI_TD_ACTIVE);
1903 1903 }
1904 1904
1905 1905 /* Insert this td onto the tw */
1906 1906
1907 1907 if (tw->tw_hctd_head == NULL) {
1908 1908 ASSERT(tw->tw_hctd_tail == NULL);
1909 1909 tw->tw_hctd_head = current_dummy;
1910 1910 tw->tw_hctd_tail = current_dummy;
1911 1911 } else {
1912 1912 /* Add the td to the end of the list */
1913 1913 tw->tw_hctd_tail->tw_td_next = current_dummy;
1914 1914 tw->tw_hctd_tail = current_dummy;
1915 1915 }
1916 1916
1917 1917 /*
1918 1918 * Insert the TD on to the QH. When this occurs,
1919 1919 * the Host Controller will see the newly filled in TD
1920 1920 */
1921 1921 current_dummy->outst_td_next = NULL;
1922 1922 current_dummy->outst_td_prev = uhcip->uhci_outst_tds_tail;
1923 1923 if (uhcip->uhci_outst_tds_head == NULL) {
1924 1924 uhcip->uhci_outst_tds_head = current_dummy;
1925 1925 } else {
1926 1926 uhcip->uhci_outst_tds_tail->outst_td_next = current_dummy;
1927 1927 }
1928 1928 uhcip->uhci_outst_tds_tail = current_dummy;
1929 1929 current_dummy->tw = tw;
1930 1930
1931 1931 return (USB_SUCCESS);
1932 1932 }
1933 1933
1934 1934
1935 1935 /*
1936 1936 * uhci_fill_in_td:
1937 1937 * Fill in the fields of a Transfer Descriptor (TD).
1938 1938 */
1939 1939 static void
1940 1940 uhci_fill_in_td(
1941 1941 uhci_state_t *uhcip,
1942 1942 uhci_td_t *td,
1943 1943 uhci_td_t *current_dummy,
1944 1944 uint32_t buffer_offset,
1945 1945 size_t length,
1946 1946 uhci_pipe_private_t *pp,
1947 1947 uchar_t PID,
1948 1948 usb_req_attrs_t attrs,
1949 1949 uhci_trans_wrapper_t *tw)
1950 1950 {
1951 1951 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle;
1952 1952 uint32_t buf_addr;
1953 1953
1954 1954 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
1955 1955 "uhci_fill_in_td: td 0x%p buf_offs 0x%x len 0x%lx "
1956 1956 "attrs 0x%x", (void *)td, buffer_offset, length, attrs);
1957 1957
1958 1958 /*
1959 1959 * If this is an isochronous TD, just return
1960 1960 */
1961 1961 if (UHCI_XFER_TYPE(&ph->p_ep) == USB_EP_ATTR_ISOCH) {
1962 1962
1963 1963 return;
1964 1964 }
1965 1965
1966 1966 /* The maximum transfer length of UHCI cannot exceed 0x500 bytes */
1967 1967 ASSERT(length <= UHCI_MAX_TD_XFER_SIZE);
1968 1968
1969 1969 bzero((char *)td, sizeof (uhci_td_t)); /* Clear the TD */
1970 1970 SetTD32(uhcip, current_dummy->link_ptr, TD_PADDR(td));
1971 1971
1972 1972 if (attrs & USB_ATTRS_SHORT_XFER_OK) {
1973 1973 SetTD_spd(uhcip, current_dummy, 1);
1974 1974 }
1975 1975
1976 1976 mutex_enter(&ph->p_usba_device->usb_mutex);
1977 1977 if (ph->p_usba_device->usb_port_status == USBA_LOW_SPEED_DEV) {
1978 1978 SetTD_ls(uhcip, current_dummy, LOW_SPEED_DEVICE);
1979 1979 }
1980 1980
1981 1981 SetTD_c_err(uhcip, current_dummy, UHCI_MAX_ERR_COUNT);
1982 1982 SetTD_mlen(uhcip, current_dummy,
1983 1983 (length == 0) ? ZERO_LENGTH : (length - 1));
1984 1984 SetTD_dtogg(uhcip, current_dummy, pp->pp_data_toggle);
1985 1985
1986 1986 /* Adjust the data toggle bit */
1987 1987 ADJ_DATA_TOGGLE(pp);
1988 1988
1989 1989 SetTD_devaddr(uhcip, current_dummy, ph->p_usba_device->usb_addr);
1990 1990 SetTD_endpt(uhcip, current_dummy,
1991 1991 ph->p_ep.bEndpointAddress & END_POINT_ADDRESS_MASK);
1992 1992 SetTD_PID(uhcip, current_dummy, PID);
1993 1993 SetTD_ioc(uhcip, current_dummy, INTERRUPT_ON_COMPLETION);
1994 1994
1995 1995 buf_addr = uhci_get_tw_paddr_by_offs(uhcip, buffer_offset, length, tw);
1996 1996 SetTD32(uhcip, current_dummy->buffer_address, buf_addr);
1997 1997
1998 1998 td->qh_td_prev = current_dummy;
1999 1999 current_dummy->qh_td_prev = NULL;
2000 2000 pp->pp_qh->td_tailp = td;
2001 2001 mutex_exit(&ph->p_usba_device->usb_mutex);
2002 2002 }
2003 2003
2004 2004 /*
2005 2005 * uhci_get_tw_paddr_by_offs:
2006 2006 * Walk through the DMA cookies of a TW buffer to retrieve
2007 2007 * the device address used for a TD.
2008 2008 *
2009 2009 * buffer_offset - the starting offset into the TW buffer, where the
2010 2010 * TD should transfer from. When a TW has more than
2011 2011 * one TD, the TDs must be filled in increasing order.
2012 2012 */
2013 2013 static uint32_t
2014 2014 uhci_get_tw_paddr_by_offs(
2015 2015 uhci_state_t *uhcip,
2016 2016 uint32_t buffer_offset,
2017 2017 size_t length,
2018 2018 uhci_trans_wrapper_t *tw)
2019 2019 {
2020 2020 uint32_t buf_addr;
2021 2021 int rem_len;
2022 2022
2023 2023 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
2024 2024 "uhci_get_tw_paddr_by_offs: buf_offs 0x%x len 0x%lx",
2025 2025 buffer_offset, length);
2026 2026
2027 2027 /*
2028 2028 * TDs must be filled in increasing DMA offset order.
2029 2029 * tw_dma_offs is initialized to be 0 at TW creation and
2030 2030 * is only increased in this function.
2031 2031 */
2032 2032 ASSERT(length == 0 || buffer_offset >= tw->tw_dma_offs);
2033 2033
2034 2034 if (length == 0) {
2035 2035 buf_addr = 0;
2036 2036
2037 2037 return (buf_addr);
2038 2038 }
2039 2039
2040 2040 /*
2041 2041 * Advance to the next DMA cookie until finding the cookie
2042 2042 * that buffer_offset falls in.
2043 2043 * It is very likely this loop will never repeat more than
2044 2044 * once. It is here just to accommodate the case buffer_offset
2045 2045 * is increased by multiple cookies during two consecutive
2046 2046 * calls into this function. In that case, the interim DMA
2047 2047 * buffer is allowed to be skipped.
2048 2048 */
2049 2049 while ((tw->tw_dma_offs + tw->tw_cookie.dmac_size) <=
2050 2050 buffer_offset) {
2051 2051 /*
2052 2052 * tw_dma_offs always points to the starting offset
2053 2053 * of a cookie
2054 2054 */
2055 2055 tw->tw_dma_offs += tw->tw_cookie.dmac_size;
2056 2056 ddi_dma_nextcookie(tw->tw_dmahandle, &tw->tw_cookie);
2057 2057 tw->tw_cookie_idx++;
2058 2058 ASSERT(tw->tw_cookie_idx < tw->tw_ncookies);
2059 2059 }
2060 2060
2061 2061 /*
2062 2062 * Counting the remained buffer length to be filled in
2063 2063 * the TDs for current DMA cookie
2064 2064 */
2065 2065 rem_len = (tw->tw_dma_offs + tw->tw_cookie.dmac_size) -
2066 2066 buffer_offset;
2067 2067
2068 2068 /* Calculate the beginning address of the buffer */
2069 2069 ASSERT(length <= rem_len);
2070 2070 buf_addr = (buffer_offset - tw->tw_dma_offs) +
2071 2071 tw->tw_cookie.dmac_address;
2072 2072
2073 2073 USB_DPRINTF_L3(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
2074 2074 "uhci_get_tw_paddr_by_offs: dmac_addr 0x%x dmac_size "
2075 2075 "0x%lx idx %d", buf_addr, tw->tw_cookie.dmac_size,
2076 2076 tw->tw_cookie_idx);
2077 2077
2078 2078 return (buf_addr);
2079 2079 }
2080 2080
2081 2081
2082 2082 /*
2083 2083 * uhci_modify_td_active_bits:
2084 2084 * Sets active bit in all the tds of QH to INACTIVE so that
2085 2085 * the HC stops processing the TD's related to the QH.
2086 2086 */
2087 2087 void
2088 2088 uhci_modify_td_active_bits(
2089 2089 uhci_state_t *uhcip,
2090 2090 uhci_pipe_private_t *pp)
2091 2091 {
2092 2092 uhci_td_t *td_head;
2093 2093 usb_ep_descr_t *ept = &pp->pp_pipe_handle->p_ep;
2094 2094 uhci_trans_wrapper_t *tw_head = pp->pp_tw_head;
2095 2095
2096 2096 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
2097 2097 "uhci_modify_td_active_bits: tw head %p", (void *)tw_head);
2098 2098
2099 2099 while (tw_head != NULL) {
2100 2100 tw_head->tw_claim = UHCI_MODIFY_TD_BITS_CLAIMED;
2101 2101 td_head = tw_head->tw_hctd_head;
2102 2102
2103 2103 while (td_head) {
2104 2104 if (UHCI_XFER_TYPE(ept) == USB_EP_ATTR_ISOCH) {
2105 2105 SetTD_status(uhcip, td_head,
2106 2106 GetTD_status(uhcip, td_head) & TD_INACTIVE);
2107 2107 } else {
2108 2108 SetTD32(uhcip, td_head->link_ptr,
2109 2109 GetTD32(uhcip, td_head->link_ptr) |
2110 2110 HC_END_OF_LIST);
2111 2111 }
2112 2112
2113 2113 td_head = td_head->tw_td_next;
2114 2114 }
2115 2115 tw_head = tw_head->tw_next;
2116 2116 }
2117 2117 }
2118 2118
2119 2119
2120 2120 /*
2121 2121 * uhci_insert_ctrl_td:
2122 2122 * Create a TD and a data buffer for a control Queue Head.
2123 2123 */
2124 2124 int
2125 2125 uhci_insert_ctrl_td(
2126 2126 uhci_state_t *uhcip,
2127 2127 usba_pipe_handle_data_t *ph,
2128 2128 usb_ctrl_req_t *ctrl_reqp,
2129 2129 usb_flags_t flags)
2130 2130 {
2131 2131 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private;
2132 2132 uhci_trans_wrapper_t *tw;
2133 2133 size_t ctrl_buf_size;
2134 2134
2135 2135 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
2136 2136 "uhci_insert_ctrl_td: timeout: 0x%x", ctrl_reqp->ctrl_timeout);
2137 2137
2138 2138 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
2139 2139
2140 2140 /*
2141 2141 * If we have a control data phase, make the data buffer start
2142 2142 * on the next 64-byte boundary so as to ensure the DMA cookie
2143 2143 * can fit in the multiple TDs. The buffer in the range of
2144 2144 * [SETUP_SIZE, UHCI_CTRL_EPT_MAX_SIZE) is just for padding
2145 2145 * and not to be transferred.
2146 2146 */
2147 2147 if (ctrl_reqp->ctrl_wLength) {
2148 2148 ctrl_buf_size = UHCI_CTRL_EPT_MAX_SIZE +
2149 2149 ctrl_reqp->ctrl_wLength;
2150 2150 } else {
2151 2151 ctrl_buf_size = SETUP_SIZE;
2152 2152 }
2153 2153
2154 2154 /* Allocate a transaction wrapper */
2155 2155 if ((tw = uhci_create_transfer_wrapper(uhcip, pp,
2156 2156 ctrl_buf_size, flags)) == NULL) {
2157 2157 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
2158 2158 "uhci_insert_ctrl_td: TW allocation failed");
2159 2159
2160 2160 return (USB_NO_RESOURCES);
2161 2161 }
2162 2162
2163 2163 pp->pp_data_toggle = 0;
2164 2164
2165 2165 tw->tw_curr_xfer_reqp = (usb_opaque_t)ctrl_reqp;
2166 2166 tw->tw_bytes_xfered = 0;
2167 2167 tw->tw_bytes_pending = ctrl_reqp->ctrl_wLength;
2168 2168 tw->tw_timeout_cnt = max(UHCI_CTRL_TIMEOUT, ctrl_reqp->ctrl_timeout);
2169 2169
2170 2170 /*
2171 2171 * Initialize the callback and any callback
2172 2172 * data for when the td completes.
2173 2173 */
2174 2174 tw->tw_handle_td = uhci_handle_ctrl_td;
2175 2175 tw->tw_handle_callback_value = NULL;
2176 2176
2177 2177 if ((uhci_create_setup_pkt(uhcip, pp, tw)) != USB_SUCCESS) {
2178 2178 tw->tw_ctrl_state = 0;
2179 2179
2180 2180 /* free the transfer wrapper */
2181 2181 uhci_deallocate_tw(uhcip, pp, tw);
2182 2182
2183 2183 return (USB_NO_RESOURCES);
2184 2184 }
2185 2185
2186 2186 tw->tw_ctrl_state = SETUP;
2187 2187
2188 2188 return (USB_SUCCESS);
2189 2189 }
2190 2190
2191 2191
2192 2192 /*
2193 2193 * uhci_create_setup_pkt:
2194 2194 * create a setup packet to initiate a control transfer.
2195 2195 *
2196 2196 * OHCI driver has seen the case where devices fail if there is
2197 2197 * more than one control transfer to the device within a frame.
2198 2198 * So, the UHCI ensures that only one TD will be put on the control
2199 2199 * pipe to one device (to be consistent with OHCI driver).
2200 2200 */
2201 2201 static int
2202 2202 uhci_create_setup_pkt(
2203 2203 uhci_state_t *uhcip,
2204 2204 uhci_pipe_private_t *pp,
2205 2205 uhci_trans_wrapper_t *tw)
2206 2206 {
2207 2207 int sdata;
2208 2208 usb_ctrl_req_t *req = (usb_ctrl_req_t *)tw->tw_curr_xfer_reqp;
2209 2209
2210 2210 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
2211 2211 "uhci_create_setup_pkt: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%p",
2212 2212 req->ctrl_bmRequestType, req->ctrl_bRequest, req->ctrl_wValue,
2213 2213 req->ctrl_wIndex, req->ctrl_wLength, (void *)req->ctrl_data);
2214 2214
2215 2215 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
2216 2216 ASSERT(tw != NULL);
2217 2217
2218 2218 /* Create the first four bytes of the setup packet */
2219 2219 sdata = (req->ctrl_bmRequestType | (req->ctrl_bRequest << 8) |
2220 2220 (req->ctrl_wValue << 16));
2221 2221 ddi_put32(tw->tw_accesshandle, (uint_t *)tw->tw_buf, sdata);
2222 2222
2223 2223 /* Create the second four bytes */
2224 2224 sdata = (uint32_t)(req->ctrl_wIndex | (req->ctrl_wLength << 16));
2225 2225 ddi_put32(tw->tw_accesshandle,
2226 2226 (uint_t *)(tw->tw_buf + sizeof (uint_t)), sdata);
2227 2227
2228 2228 /*
2229 2229 * The TD's are placed on the QH one at a time.
2230 2230 * Once this TD is placed on the done list, the
2231 2231 * data or status phase TD will be enqueued.
2232 2232 */
2233 2233 if ((uhci_insert_hc_td(uhcip, 0, SETUP_SIZE,
2234 2234 pp, tw, PID_SETUP, req->ctrl_attributes)) != USB_SUCCESS) {
2235 2235
2236 2236 return (USB_NO_RESOURCES);
2237 2237 }
2238 2238
2239 2239 USB_DPRINTF_L3(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
2240 2240 "Create_setup: pp = 0x%p, attrs = 0x%x", (void *)pp,
2241 2241 req->ctrl_attributes);
2242 2242
2243 2243 /*
2244 2244 * If this control transfer has a data phase, record the
2245 2245 * direction. If the data phase is an OUT transaction ,
2246 2246 * copy the data into the buffer of the transfer wrapper.
2247 2247 */
2248 2248 if (req->ctrl_wLength != 0) {
2249 2249 /* There is a data stage. Find the direction */
2250 2250 if (req->ctrl_bmRequestType & USB_DEV_REQ_DEV_TO_HOST) {
2251 2251 tw->tw_direction = PID_IN;
2252 2252 } else {
2253 2253 tw->tw_direction = PID_OUT;
2254 2254
2255 2255 /* Copy the data into the buffer */
2256 2256 ddi_rep_put8(tw->tw_accesshandle,
2257 2257 req->ctrl_data->b_rptr,
2258 2258 (uint8_t *)(tw->tw_buf + UHCI_CTRL_EPT_MAX_SIZE),
2259 2259 req->ctrl_wLength,
2260 2260 DDI_DEV_AUTOINCR);
2261 2261 }
2262 2262 }
2263 2263
2264 2264 return (USB_SUCCESS);
2265 2265 }
2266 2266
2267 2267
2268 2268 /*
2269 2269 * uhci_create_stats:
2270 2270 * Allocate and initialize the uhci kstat structures
2271 2271 */
2272 2272 void
2273 2273 uhci_create_stats(uhci_state_t *uhcip)
2274 2274 {
2275 2275 int i;
2276 2276 char kstatname[KSTAT_STRLEN];
2277 2277 char *usbtypes[USB_N_COUNT_KSTATS] =
2278 2278 {"ctrl", "isoch", "bulk", "intr"};
2279 2279 uint_t instance = uhcip->uhci_instance;
2280 2280 const char *dname = ddi_driver_name(uhcip->uhci_dip);
2281 2281 uhci_intrs_stats_t *isp;
2282 2282
2283 2283 if (UHCI_INTRS_STATS(uhcip) == NULL) {
2284 2284 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs",
2285 2285 dname, instance);
2286 2286 UHCI_INTRS_STATS(uhcip) = kstat_create("usba", instance,
2287 2287 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED,
2288 2288 sizeof (uhci_intrs_stats_t) / sizeof (kstat_named_t),
2289 2289 KSTAT_FLAG_PERSISTENT);
2290 2290
2291 2291 if (UHCI_INTRS_STATS(uhcip) != NULL) {
2292 2292 isp = UHCI_INTRS_STATS_DATA(uhcip);
2293 2293 kstat_named_init(&isp->uhci_intrs_hc_halted,
2294 2294 "HC Halted", KSTAT_DATA_UINT64);
2295 2295 kstat_named_init(&isp->uhci_intrs_hc_process_err,
2296 2296 "HC Process Errors", KSTAT_DATA_UINT64);
2297 2297 kstat_named_init(&isp->uhci_intrs_host_sys_err,
2298 2298 "Host Sys Errors", KSTAT_DATA_UINT64);
2299 2299 kstat_named_init(&isp->uhci_intrs_resume_detected,
2300 2300 "Resume Detected", KSTAT_DATA_UINT64);
2301 2301 kstat_named_init(&isp->uhci_intrs_usb_err_intr,
2302 2302 "USB Error", KSTAT_DATA_UINT64);
2303 2303 kstat_named_init(&isp->uhci_intrs_usb_intr,
2304 2304 "USB Interrupts", KSTAT_DATA_UINT64);
2305 2305 kstat_named_init(&isp->uhci_intrs_total,
2306 2306 "Total Interrupts", KSTAT_DATA_UINT64);
2307 2307 kstat_named_init(&isp->uhci_intrs_not_claimed,
2308 2308 "Not Claimed", KSTAT_DATA_UINT64);
2309 2309
2310 2310 UHCI_INTRS_STATS(uhcip)->ks_private = uhcip;
2311 2311 UHCI_INTRS_STATS(uhcip)->ks_update = nulldev;
2312 2312 kstat_install(UHCI_INTRS_STATS(uhcip));
2313 2313 }
2314 2314 }
2315 2315
2316 2316 if (UHCI_TOTAL_STATS(uhcip) == NULL) {
2317 2317 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total",
2318 2318 dname, instance);
2319 2319 UHCI_TOTAL_STATS(uhcip) = kstat_create("usba", instance,
2320 2320 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1,
2321 2321 KSTAT_FLAG_PERSISTENT);
2322 2322
2323 2323 if (UHCI_TOTAL_STATS(uhcip) != NULL) {
2324 2324 kstat_install(UHCI_TOTAL_STATS(uhcip));
2325 2325 }
2326 2326 }
2327 2327
2328 2328 for (i = 0; i < USB_N_COUNT_KSTATS; i++) {
2329 2329 if (uhcip->uhci_count_stats[i] == NULL) {
2330 2330 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s",
2331 2331 dname, instance, usbtypes[i]);
2332 2332 uhcip->uhci_count_stats[i] = kstat_create("usba",
2333 2333 instance, kstatname, "usb_byte_count",
2334 2334 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT);
2335 2335
2336 2336 if (uhcip->uhci_count_stats[i] != NULL) {
2337 2337 kstat_install(uhcip->uhci_count_stats[i]);
2338 2338 }
2339 2339 }
2340 2340 }
2341 2341 }
2342 2342
2343 2343
2344 2344 /*
2345 2345 * uhci_destroy_stats:
2346 2346 * Clean up uhci kstat structures
2347 2347 */
2348 2348 void
2349 2349 uhci_destroy_stats(uhci_state_t *uhcip)
2350 2350 {
2351 2351 int i;
2352 2352
2353 2353 if (UHCI_INTRS_STATS(uhcip)) {
2354 2354 kstat_delete(UHCI_INTRS_STATS(uhcip));
2355 2355 UHCI_INTRS_STATS(uhcip) = NULL;
2356 2356 }
2357 2357
2358 2358 if (UHCI_TOTAL_STATS(uhcip)) {
2359 2359 kstat_delete(UHCI_TOTAL_STATS(uhcip));
2360 2360 UHCI_TOTAL_STATS(uhcip) = NULL;
2361 2361 }
2362 2362
2363 2363 for (i = 0; i < USB_N_COUNT_KSTATS; i++) {
2364 2364 if (uhcip->uhci_count_stats[i]) {
2365 2365 kstat_delete(uhcip->uhci_count_stats[i]);
2366 2366 uhcip->uhci_count_stats[i] = NULL;
2367 2367 }
2368 2368 }
2369 2369 }
2370 2370
2371 2371
2372 2372 void
2373 2373 uhci_do_intrs_stats(uhci_state_t *uhcip, int val)
2374 2374 {
2375 2375 if (UHCI_INTRS_STATS(uhcip) == NULL) {
2376 2376
2377 2377 return;
2378 2378 }
2379 2379
2380 2380 UHCI_INTRS_STATS_DATA(uhcip)->uhci_intrs_total.value.ui64++;
2381 2381 switch (val) {
2382 2382 case USBSTS_REG_HC_HALTED:
2383 2383 UHCI_INTRS_STATS_DATA(uhcip)->uhci_intrs_hc_halted.value.ui64++;
2384 2384 break;
2385 2385 case USBSTS_REG_HC_PROCESS_ERR:
2386 2386 UHCI_INTRS_STATS_DATA(uhcip)->
2387 2387 uhci_intrs_hc_process_err.value.ui64++;
2388 2388 break;
2389 2389 case USBSTS_REG_HOST_SYS_ERR:
2390 2390 UHCI_INTRS_STATS_DATA(uhcip)->
2391 2391 uhci_intrs_host_sys_err.value.ui64++;
2392 2392 break;
2393 2393 case USBSTS_REG_RESUME_DETECT:
2394 2394 UHCI_INTRS_STATS_DATA(uhcip)->
2395 2395 uhci_intrs_resume_detected.value.ui64++;
2396 2396 break;
2397 2397 case USBSTS_REG_USB_ERR_INTR:
2398 2398 UHCI_INTRS_STATS_DATA(uhcip)->
2399 2399 uhci_intrs_usb_err_intr.value.ui64++;
2400 2400 break;
2401 2401 case USBSTS_REG_USB_INTR:
2402 2402 UHCI_INTRS_STATS_DATA(uhcip)->uhci_intrs_usb_intr.value.ui64++;
2403 2403 break;
2404 2404 default:
2405 2405 UHCI_INTRS_STATS_DATA(uhcip)->
2406 2406 uhci_intrs_not_claimed.value.ui64++;
2407 2407 break;
2408 2408 }
2409 2409 }
2410 2410
2411 2411
2412 2412 void
2413 2413 uhci_do_byte_stats(uhci_state_t *uhcip, size_t len, uint8_t attr, uint8_t addr)
2414 2414 {
2415 2415 uint8_t type = attr & USB_EP_ATTR_MASK;
2416 2416 uint8_t dir = addr & USB_EP_DIR_MASK;
2417 2417
2418 2418 switch (dir) {
2419 2419 case USB_EP_DIR_IN:
2420 2420 UHCI_TOTAL_STATS_DATA(uhcip)->reads++;
2421 2421 UHCI_TOTAL_STATS_DATA(uhcip)->nread += len;
2422 2422 switch (type) {
2423 2423 case USB_EP_ATTR_CONTROL:
2424 2424 UHCI_CTRL_STATS(uhcip)->reads++;
2425 2425 UHCI_CTRL_STATS(uhcip)->nread += len;
2426 2426 break;
2427 2427 case USB_EP_ATTR_BULK:
2428 2428 UHCI_BULK_STATS(uhcip)->reads++;
2429 2429 UHCI_BULK_STATS(uhcip)->nread += len;
2430 2430 break;
2431 2431 case USB_EP_ATTR_INTR:
2432 2432 UHCI_INTR_STATS(uhcip)->reads++;
2433 2433 UHCI_INTR_STATS(uhcip)->nread += len;
2434 2434 break;
2435 2435 case USB_EP_ATTR_ISOCH:
2436 2436 UHCI_ISOC_STATS(uhcip)->reads++;
2437 2437 UHCI_ISOC_STATS(uhcip)->nread += len;
2438 2438 break;
2439 2439 }
2440 2440 break;
2441 2441 case USB_EP_DIR_OUT:
2442 2442 UHCI_TOTAL_STATS_DATA(uhcip)->writes++;
2443 2443 UHCI_TOTAL_STATS_DATA(uhcip)->nwritten += len;
2444 2444 switch (type) {
2445 2445 case USB_EP_ATTR_CONTROL:
2446 2446 UHCI_CTRL_STATS(uhcip)->writes++;
2447 2447 UHCI_CTRL_STATS(uhcip)->nwritten += len;
2448 2448 break;
2449 2449 case USB_EP_ATTR_BULK:
2450 2450 UHCI_BULK_STATS(uhcip)->writes++;
2451 2451 UHCI_BULK_STATS(uhcip)->nwritten += len;
2452 2452 break;
2453 2453 case USB_EP_ATTR_INTR:
2454 2454 UHCI_INTR_STATS(uhcip)->writes++;
2455 2455 UHCI_INTR_STATS(uhcip)->nwritten += len;
2456 2456 break;
2457 2457 case USB_EP_ATTR_ISOCH:
2458 2458 UHCI_ISOC_STATS(uhcip)->writes++;
2459 2459 UHCI_ISOC_STATS(uhcip)->nwritten += len;
2460 2460 break;
2461 2461 }
2462 2462 break;
2463 2463 }
2464 2464 }
2465 2465
2466 2466
2467 2467 /*
2468 2468 * uhci_free_tw:
2469 2469 * Free the Transfer Wrapper (TW).
2470 2470 */
2471 2471 void
2472 2472 uhci_free_tw(uhci_state_t *uhcip, uhci_trans_wrapper_t *tw)
2473 2473 {
2474 2474 int rval, i;
2475 2475
2476 2476 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, "uhci_free_tw:");
2477 2477
2478 2478 ASSERT(tw != NULL);
2479 2479
2480 2480 if (tw->tw_isoc_strtlen > 0) {
2481 2481 ASSERT(tw->tw_isoc_bufs != NULL);
2482 2482 for (i = 0; i < tw->tw_ncookies; i++) {
2483 2483 rval = ddi_dma_unbind_handle(
2484 2484 tw->tw_isoc_bufs[i].dma_handle);
2485 2485 ASSERT(rval == USB_SUCCESS);
2486 2486 ddi_dma_mem_free(&tw->tw_isoc_bufs[i].mem_handle);
2487 2487 ddi_dma_free_handle(&tw->tw_isoc_bufs[i].dma_handle);
2488 2488 }
2489 2489 kmem_free(tw->tw_isoc_bufs, tw->tw_isoc_strtlen);
2490 2490 } else if (tw->tw_dmahandle != NULL) {
2491 2491 rval = ddi_dma_unbind_handle(tw->tw_dmahandle);
2492 2492 ASSERT(rval == DDI_SUCCESS);
2493 2493
2494 2494 ddi_dma_mem_free(&tw->tw_accesshandle);
2495 2495 ddi_dma_free_handle(&tw->tw_dmahandle);
2496 2496 }
2497 2497
2498 2498 kmem_free(tw, sizeof (uhci_trans_wrapper_t));
2499 2499 }
2500 2500
2501 2501
2502 2502 /*
2503 2503 * uhci_deallocate_tw:
2504 2504 * Deallocate of a Transaction Wrapper (TW) and this involves
2505 2505 * the freeing of DMA resources.
2506 2506 */
2507 2507 void
2508 2508 uhci_deallocate_tw(uhci_state_t *uhcip,
2509 2509 uhci_pipe_private_t *pp, uhci_trans_wrapper_t *tw)
2510 2510 {
2511 2511 uhci_trans_wrapper_t *head;
2512 2512
2513 2513 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
2514 2514 "uhci_deallocate_tw:");
2515 2515
2516 2516 /*
2517 2517 * If the transfer wrapper has no Host Controller (HC)
2518 2518 * Transfer Descriptors (TD) associated with it, then
2519 2519 * remove the transfer wrapper. The transfers are done
2520 2520 * in FIFO order, so this should be the first transfer
2521 2521 * wrapper on the list.
2522 2522 */
2523 2523 if (tw->tw_hctd_head != NULL) {
2524 2524 ASSERT(tw->tw_hctd_tail != NULL);
2525 2525
2526 2526 return;
2527 2527 }
2528 2528
2529 2529 ASSERT(tw->tw_hctd_tail == NULL);
2530 2530 ASSERT(pp->pp_tw_head != NULL);
2531 2531
2532 2532 /*
2533 2533 * If pp->pp_tw_head is NULL, set the tail also to NULL.
2534 2534 */
2535 2535 head = pp->pp_tw_head;
2536 2536
2537 2537 if (head == tw) {
2538 2538 pp->pp_tw_head = head->tw_next;
2539 2539 if (pp->pp_tw_head == NULL) {
2540 2540 pp->pp_tw_tail = NULL;
2541 2541 }
2542 2542 } else {
2543 2543 while (head->tw_next != tw)
2544 2544 head = head->tw_next;
2545 2545 head->tw_next = tw->tw_next;
2546 2546 if (tw->tw_next == NULL) {
2547 2547 pp->pp_tw_tail = head;
2548 2548 }
2549 2549 }
2550 2550 uhci_free_tw(uhcip, tw);
2551 2551 }
2552 2552
2553 2553
2554 2554 void
2555 2555 uhci_delete_td(uhci_state_t *uhcip, uhci_td_t *td)
2556 2556 {
2557 2557 uhci_td_t *tmp_td;
2558 2558 uhci_trans_wrapper_t *tw = td->tw;
2559 2559
2560 2560 if ((td->outst_td_next == NULL) && (td->outst_td_prev == NULL)) {
2561 2561 uhcip->uhci_outst_tds_head = NULL;
2562 2562 uhcip->uhci_outst_tds_tail = NULL;
2563 2563 } else if (td->outst_td_next == NULL) {
2564 2564 td->outst_td_prev->outst_td_next = NULL;
2565 2565 uhcip->uhci_outst_tds_tail = td->outst_td_prev;
2566 2566 } else if (td->outst_td_prev == NULL) {
2567 2567 td->outst_td_next->outst_td_prev = NULL;
2568 2568 uhcip->uhci_outst_tds_head = td->outst_td_next;
2569 2569 } else {
2570 2570 td->outst_td_prev->outst_td_next = td->outst_td_next;
2571 2571 td->outst_td_next->outst_td_prev = td->outst_td_prev;
2572 2572 }
2573 2573
2574 2574 tmp_td = tw->tw_hctd_head;
2575 2575
2576 2576 if (tmp_td != td) {
2577 2577 while (tmp_td->tw_td_next != td) {
2578 2578 tmp_td = tmp_td->tw_td_next;
2579 2579 }
2580 2580 ASSERT(tmp_td);
2581 2581 tmp_td->tw_td_next = td->tw_td_next;
2582 2582 if (td->tw_td_next == NULL) {
2583 2583 tw->tw_hctd_tail = tmp_td;
2584 2584 }
2585 2585 } else {
2586 2586 tw->tw_hctd_head = tw->tw_hctd_head->tw_td_next;
2587 2587 if (tw->tw_hctd_head == NULL) {
2588 2588 tw->tw_hctd_tail = NULL;
2589 2589 }
2590 2590 }
2591 2591
2592 2592 td->flag = TD_FLAG_FREE;
2593 2593 }
2594 2594
2595 2595
2596 2596 void
2597 2597 uhci_remove_tds_tws(
2598 2598 uhci_state_t *uhcip,
2599 2599 usba_pipe_handle_data_t *ph)
2600 2600 {
2601 2601 usb_opaque_t curr_reqp;
2602 2602 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private;
2603 2603 usb_ep_descr_t *ept = &pp->pp_pipe_handle->p_ep;
2604 2604 uhci_trans_wrapper_t *tw_tmp;
2605 2605 uhci_trans_wrapper_t *tw_head = pp->pp_tw_head;
2606 2606
2607 2607 while (tw_head != NULL) {
2608 2608 tw_tmp = tw_head;
2609 2609 tw_head = tw_head->tw_next;
2610 2610
2611 2611 curr_reqp = tw_tmp->tw_curr_xfer_reqp;
2612 2612 if (curr_reqp) {
2613 2613 /* do this for control/bulk/intr */
2614 2614 if ((tw_tmp->tw_direction == PID_IN) &&
2615 2615 (UHCI_XFER_TYPE(ept) == USB_EP_ATTR_INTR)) {
2616 2616 uhci_deallocate_periodic_in_resource(uhcip,
2617 2617 pp, tw_tmp);
2618 2618 } else {
2619 2619 uhci_hcdi_callback(uhcip, pp,
2620 2620 pp->pp_pipe_handle, tw_tmp, USB_CR_FLUSHED);
2621 2621 }
2622 2622 } /* end of curr_reqp */
2623 2623
2624 2624 if (tw_tmp->tw_claim != UHCI_MODIFY_TD_BITS_CLAIMED) {
2625 2625 continue;
2626 2626 }
2627 2627
2628 2628 while (tw_tmp->tw_hctd_head != NULL) {
2629 2629 uhci_delete_td(uhcip, tw_tmp->tw_hctd_head);
2630 2630 }
2631 2631
2632 2632 uhci_deallocate_tw(uhcip, pp, tw_tmp);
2633 2633 }
2634 2634 }
2635 2635
2636 2636
2637 2637 /*
2638 2638 * uhci_remove_qh:
2639 2639 * Remove the Queue Head from the Host Controller's
2640 2640 * appropriate QH list.
2641 2641 */
2642 2642 void
2643 2643 uhci_remove_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp)
2644 2644 {
2645 2645 uhci_td_t *dummy_td;
2646 2646
2647 2647 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
2648 2648
2649 2649 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
2650 2650 "uhci_remove_qh:");
2651 2651
2652 2652 dummy_td = pp->pp_qh->td_tailp;
2653 2653 dummy_td->flag = TD_FLAG_FREE;
2654 2654
2655 2655 switch (UHCI_XFER_TYPE(&pp->pp_pipe_handle->p_ep)) {
2656 2656 case USB_EP_ATTR_CONTROL:
2657 2657 uhci_remove_ctrl_qh(uhcip, pp);
2658 2658 break;
2659 2659 case USB_EP_ATTR_BULK:
2660 2660 uhci_remove_bulk_qh(uhcip, pp);
2661 2661 break;
2662 2662 case USB_EP_ATTR_INTR:
2663 2663 uhci_remove_intr_qh(uhcip, pp);
2664 2664 break;
2665 2665 }
2666 2666 }
2667 2667
2668 2668
2669 2669 static void
2670 2670 uhci_remove_intr_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp)
2671 2671 {
2672 2672 queue_head_t *qh = pp->pp_qh;
2673 2673 queue_head_t *next_lattice_qh =
2674 2674 QH_VADDR(GetQH32(uhcip, qh->link_ptr) & QH_LINK_PTR_MASK);
2675 2675
2676 2676 qh->prev_qh->link_ptr = qh->link_ptr;
2677 2677 next_lattice_qh->prev_qh = qh->prev_qh;
2678 2678 qh->qh_flag = QUEUE_HEAD_FLAG_FREE;
2679 2679
2680 2680 }
2681 2681
2682 2682 /*
2683 2683 * uhci_remove_bulk_qh:
2684 2684 * Remove a bulk QH from the Host Controller's QH list. There may be a
2685 2685 * loop for bulk QHs, we must care about this while removing a bulk QH.
2686 2686 */
2687 2687 static void
2688 2688 uhci_remove_bulk_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp)
2689 2689 {
2690 2690 queue_head_t *qh = pp->pp_qh;
2691 2691 queue_head_t *next_lattice_qh;
2692 2692 uint32_t paddr;
2693 2693
2694 2694 paddr = (GetQH32(uhcip, qh->link_ptr) & QH_LINK_PTR_MASK);
2695 2695 next_lattice_qh = (qh == uhcip->uhci_bulk_xfers_q_tail) ?
2696 2696 0 : QH_VADDR(paddr);
2697 2697
2698 2698 if ((qh == uhcip->uhci_bulk_xfers_q_tail) &&
2699 2699 (qh->prev_qh == uhcip->uhci_bulk_xfers_q_head)) {
2700 2700 SetQH32(uhcip, qh->prev_qh->link_ptr, HC_END_OF_LIST);
2701 2701 } else {
2702 2702 qh->prev_qh->link_ptr = qh->link_ptr;
2703 2703 }
2704 2704
2705 2705 if (next_lattice_qh == NULL) {
2706 2706 uhcip->uhci_bulk_xfers_q_tail = qh->prev_qh;
2707 2707 } else {
2708 2708 next_lattice_qh->prev_qh = qh->prev_qh;
2709 2709 }
2710 2710
2711 2711 qh->qh_flag = QUEUE_HEAD_FLAG_FREE;
2712 2712
2713 2713 }
2714 2714
2715 2715
2716 2716 static void
2717 2717 uhci_remove_ctrl_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp)
2718 2718 {
2719 2719 queue_head_t *qh = pp->pp_qh;
2720 2720 queue_head_t *next_lattice_qh =
2721 2721 QH_VADDR(GetQH32(uhcip, qh->link_ptr) & QH_LINK_PTR_MASK);
2722 2722
2723 2723 qh->prev_qh->link_ptr = qh->link_ptr;
2724 2724 if (next_lattice_qh->prev_qh != NULL) {
2725 2725 next_lattice_qh->prev_qh = qh->prev_qh;
2726 2726 } else {
2727 2727 uhcip->uhci_ctrl_xfers_q_tail = qh->prev_qh;
2728 2728 }
2729 2729
2730 2730 qh->qh_flag = QUEUE_HEAD_FLAG_FREE;
2731 2731 }
2732 2732
2733 2733
2734 2734 /*
2735 2735 * uhci_allocate_td_from_pool:
2736 2736 * Allocate a Transfer Descriptor (TD) from the TD buffer pool.
2737 2737 */
2738 2738 static uhci_td_t *
2739 2739 uhci_allocate_td_from_pool(uhci_state_t *uhcip)
2740 2740 {
2741 2741 int index;
2742 2742 uhci_td_t *td;
2743 2743
2744 2744 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
2745 2745
2746 2746 /*
2747 2747 * Search for a blank Transfer Descriptor (TD)
2748 2748 * in the TD buffer pool.
2749 2749 */
2750 2750 for (index = 0; index < uhci_td_pool_size; index ++) {
2751 2751 if (uhcip->uhci_td_pool_addr[index].flag == TD_FLAG_FREE) {
2752 2752 break;
2753 2753 }
2754 2754 }
2755 2755
2756 2756 if (index == uhci_td_pool_size) {
2757 2757 USB_DPRINTF_L2(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
2758 2758 "uhci_allocate_td_from_pool: TD exhausted");
2759 2759
2760 2760 return (NULL);
2761 2761 }
2762 2762
2763 2763 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl,
2764 2764 "uhci_allocate_td_from_pool: Allocated %d", index);
2765 2765
2766 2766 /* Create a new dummy for the end of the TD list */
2767 2767 td = &uhcip->uhci_td_pool_addr[index];
2768 2768
2769 2769 /* Mark the newly allocated TD as a dummy */
2770 2770 td->flag = TD_FLAG_DUMMY;
2771 2771 td->qh_td_prev = NULL;
2772 2772
2773 2773 return (td);
2774 2774 }
2775 2775
2776 2776
2777 2777 /*
2778 2778 * uhci_insert_bulk_td:
2779 2779 */
2780 2780 int
2781 2781 uhci_insert_bulk_td(
2782 2782 uhci_state_t *uhcip,
2783 2783 usba_pipe_handle_data_t *ph,
2784 2784 usb_bulk_req_t *req,
2785 2785 usb_flags_t flags)
2786 2786 {
2787 2787 size_t length;
2788 2788 uint_t mps; /* MaxPacketSize */
2789 2789 uint_t num_bulk_tds, i, j;
2790 2790 uint32_t buf_offs;
2791 2791 uhci_td_t *bulk_td_ptr;
2792 2792 uhci_td_t *current_dummy, *tmp_td;
2793 2793 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private;
2794 2794 uhci_trans_wrapper_t *tw;
2795 2795 uhci_bulk_isoc_xfer_t *bulk_xfer_info;
2796 2796 uhci_bulk_isoc_td_pool_t *td_pool_ptr;
2797 2797
2798 2798 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
2799 2799 "uhci_insert_bulk_td: req: 0x%p, flags = 0x%x", (void *)req, flags);
2800 2800
2801 2801 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
2802 2802
2803 2803 /*
2804 2804 * Create transfer wrapper
2805 2805 */
2806 2806 if ((tw = uhci_create_transfer_wrapper(uhcip, pp, req->bulk_len,
2807 2807 flags)) == NULL) {
2808 2808 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
2809 2809 "uhci_insert_bulk_td: TW allocation failed");
2810 2810
2811 2811 return (USB_NO_RESOURCES);
2812 2812 }
2813 2813
2814 2814 tw->tw_bytes_xfered = 0;
2815 2815 tw->tw_bytes_pending = req->bulk_len;
2816 2816 tw->tw_handle_td = uhci_handle_bulk_td;
2817 2817 tw->tw_handle_callback_value = (usb_opaque_t)req->bulk_data;
2818 2818 tw->tw_timeout_cnt = req->bulk_timeout;
2819 2819 tw->tw_data = req->bulk_data;
2820 2820 tw->tw_curr_xfer_reqp = (usb_opaque_t)req;
2821 2821
2822 2822 /* Get the bulk pipe direction */
2823 2823 tw->tw_direction = (UHCI_XFER_DIR(&ph->p_ep) == USB_EP_DIR_OUT) ?
2824 2824 PID_OUT : PID_IN;
2825 2825
2826 2826 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
2827 2827 "uhci_insert_bulk_td: direction: 0x%x", tw->tw_direction);
2828 2828
2829 2829 /* If the DATA OUT, copy the data into transfer buffer. */
2830 2830 if (tw->tw_direction == PID_OUT) {
2831 2831 if (req->bulk_len) {
2832 2832 ASSERT(req->bulk_data != NULL);
2833 2833
2834 2834 /* Copy the data into the message */
2835 2835 ddi_rep_put8(tw->tw_accesshandle,
2836 2836 req->bulk_data->b_rptr,
2837 2837 (uint8_t *)tw->tw_buf,
2838 2838 req->bulk_len, DDI_DEV_AUTOINCR);
2839 2839 }
2840 2840 }
2841 2841
2842 2842 /* Get the max packet size. */
2843 2843 length = mps = pp->pp_pipe_handle->p_ep.wMaxPacketSize;
2844 2844
2845 2845 /*
2846 2846 * Calculate number of TD's to insert in the current frame interval.
2847 2847 * Max number TD's allowed (driver implementation) is 128
2848 2848 * in one frame interval. Once all the TD's are completed
2849 2849 * then the remaining TD's will be inserted into the lattice
2850 2850 * in the uhci_handle_bulk_td().
2851 2851 */
2852 2852 if ((tw->tw_bytes_pending / mps) >= MAX_NUM_BULK_TDS_PER_XFER) {
2853 2853 num_bulk_tds = MAX_NUM_BULK_TDS_PER_XFER;
2854 2854 } else {
2855 2855 num_bulk_tds = (tw->tw_bytes_pending / mps);
2856 2856
2857 2857 if (tw->tw_bytes_pending % mps || tw->tw_bytes_pending == 0) {
2858 2858 num_bulk_tds++;
2859 2859 length = (tw->tw_bytes_pending % mps);
2860 2860 }
2861 2861 }
2862 2862
2863 2863 /*
2864 2864 * Allocate memory for the bulk xfer information structure
2865 2865 */
2866 2866 if ((bulk_xfer_info = kmem_zalloc(
2867 2867 sizeof (uhci_bulk_isoc_xfer_t), KM_NOSLEEP)) == NULL) {
2868 2868 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
2869 2869 "uhci_insert_bulk_td: kmem_zalloc failed");
2870 2870
2871 2871 /* Free the transfer wrapper */
2872 2872 uhci_deallocate_tw(uhcip, pp, tw);
2873 2873
2874 2874 return (USB_FAILURE);
2875 2875 }
2876 2876
2877 2877 /* Allocate memory for the bulk TD's */
2878 2878 if (uhci_alloc_bulk_isoc_tds(uhcip, num_bulk_tds, bulk_xfer_info) !=
2879 2879 USB_SUCCESS) {
2880 2880 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
2881 2881 "uhci_insert_bulk_td: alloc_bulk_isoc_tds failed");
2882 2882
2883 2883 kmem_free(bulk_xfer_info, sizeof (uhci_bulk_isoc_xfer_t));
2884 2884
2885 2885 /* Free the transfer wrapper */
2886 2886 uhci_deallocate_tw(uhcip, pp, tw);
2887 2887
2888 2888 return (USB_FAILURE);
2889 2889 }
2890 2890
2891 2891 td_pool_ptr = &bulk_xfer_info->td_pools[0];
2892 2892 bulk_td_ptr = (uhci_td_t *)td_pool_ptr->pool_addr;
2893 2893 bulk_td_ptr[0].qh_td_prev = NULL;
2894 2894 current_dummy = pp->pp_qh->td_tailp;
2895 2895 buf_offs = 0;
2896 2896 pp->pp_qh->bulk_xfer_info = bulk_xfer_info;
2897 2897
2898 2898 /* Fill up all the bulk TD's */
2899 2899 for (i = 0; i < bulk_xfer_info->num_pools; i++) {
2900 2900 for (j = 0; j < (td_pool_ptr->num_tds - 1); j++) {
2901 2901 uhci_fill_in_bulk_isoc_td(uhcip, &bulk_td_ptr[j],
2902 2902 &bulk_td_ptr[j+1], BULKTD_PADDR(td_pool_ptr,
2903 2903 &bulk_td_ptr[j+1]), ph, buf_offs, mps, tw);
2904 2904 buf_offs += mps;
2905 2905 }
2906 2906
2907 2907 /* fill in the last TD */
2908 2908 if (i == (bulk_xfer_info->num_pools - 1)) {
2909 2909 uhci_fill_in_bulk_isoc_td(uhcip, &bulk_td_ptr[j],
2910 2910 current_dummy, TD_PADDR(current_dummy),
2911 2911 ph, buf_offs, length, tw);
2912 2912 } else {
2913 2913 /* fill in the TD at the tail of a pool */
2914 2914 tmp_td = &bulk_td_ptr[j];
2915 2915 td_pool_ptr = &bulk_xfer_info->td_pools[i + 1];
2916 2916 bulk_td_ptr = (uhci_td_t *)td_pool_ptr->pool_addr;
2917 2917 uhci_fill_in_bulk_isoc_td(uhcip, tmp_td,
2918 2918 &bulk_td_ptr[0], BULKTD_PADDR(td_pool_ptr,
2919 2919 &bulk_td_ptr[0]), ph, buf_offs, mps, tw);
2920 2920 buf_offs += mps;
2921 2921 }
2922 2922 }
2923 2923
2924 2924 bulk_xfer_info->num_tds = (ushort_t)num_bulk_tds;
2925 2925
2926 2926 /*
2927 2927 * Point the end of the lattice tree to the start of the bulk xfers
2928 2928 * queue head. This allows the HC to execute the same Queue Head/TD
2929 2929 * in the same frame. There are some bulk devices, which NAKs after
2930 2930 * completing each TD. As a result, the performance on such devices
2931 2931 * is very bad. This loop will provide a chance to execute NAk'ed
2932 2932 * bulk TDs again in the same frame.
2933 2933 */
2934 2934 if (uhcip->uhci_pending_bulk_cmds++ == 0) {
2935 2935 uhcip->uhci_bulk_xfers_q_tail->link_ptr =
2936 2936 uhcip->uhci_bulk_xfers_q_head->link_ptr;
2937 2937 USB_DPRINTF_L3(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
2938 2938 "uhci_insert_bulk_td: count = %d no tds %d",
2939 2939 uhcip->uhci_pending_bulk_cmds, num_bulk_tds);
2940 2940 }
2941 2941
2942 2942 /* Insert on the bulk queue head for the execution by HC */
2943 2943 SetQH32(uhcip, pp->pp_qh->element_ptr,
2944 2944 bulk_xfer_info->td_pools[0].cookie.dmac_address);
2945 2945
2946 2946 return (USB_SUCCESS);
2947 2947 }
2948 2948
2949 2949
2950 2950 /*
2951 2951 * uhci_fill_in_bulk_isoc_td
2952 2952 * Fills the bulk/isoc TD
2953 2953 *
2954 2954 * offset - different meanings for bulk and isoc TDs:
2955 2955 * starting offset into the TW buffer for a bulk TD
2956 2956 * and the index into the isoc packet list for an isoc TD
2957 2957 */
2958 2958 void
2959 2959 uhci_fill_in_bulk_isoc_td(uhci_state_t *uhcip, uhci_td_t *current_td,
2960 2960 uhci_td_t *next_td,
2961 2961 uint32_t next_td_paddr,
2962 2962 usba_pipe_handle_data_t *ph,
2963 2963 uint_t offset,
2964 2964 uint_t length,
2965 2965 uhci_trans_wrapper_t *tw)
2966 2966 {
2967 2967 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private;
2968 2968 usb_ep_descr_t *ept = &pp->pp_pipe_handle->p_ep;
2969 2969 uint32_t buf_addr;
2970 2970
2971 2971 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
2972 2972 "uhci_fill_in_bulk_isoc_td: tw 0x%p offs 0x%x length 0x%x",
2973 2973 (void *)tw, offset, length);
2974 2974
2975 2975 bzero((char *)current_td, sizeof (uhci_td_t));
2976 2976 SetTD32(uhcip, current_td->link_ptr, next_td_paddr | HC_DEPTH_FIRST);
2977 2977
2978 2978 switch (UHCI_XFER_TYPE(ept)) {
2979 2979 case USB_EP_ATTR_ISOCH:
2980 2980 if (((usb_isoc_req_t *)tw->tw_curr_xfer_reqp)->isoc_attributes
2981 2981 & USB_ATTRS_SHORT_XFER_OK) {
2982 2982 SetTD_spd(uhcip, current_td, 1);
2983 2983 }
2984 2984 break;
2985 2985 case USB_EP_ATTR_BULK:
2986 2986 if (((usb_bulk_req_t *)tw->tw_curr_xfer_reqp)->bulk_attributes
2987 2987 & USB_ATTRS_SHORT_XFER_OK) {
2988 2988 SetTD_spd(uhcip, current_td, 1);
2989 2989 }
2990 2990 break;
2991 2991 }
2992 2992
2993 2993 mutex_enter(&ph->p_usba_device->usb_mutex);
2994 2994
2995 2995 SetTD_c_err(uhcip, current_td, UHCI_MAX_ERR_COUNT);
2996 2996 SetTD_status(uhcip, current_td, UHCI_TD_ACTIVE);
2997 2997 SetTD_ioc(uhcip, current_td, INTERRUPT_ON_COMPLETION);
2998 2998 SetTD_mlen(uhcip, current_td,
2999 2999 (length == 0) ? ZERO_LENGTH : (length - 1));
3000 3000 SetTD_dtogg(uhcip, current_td, pp->pp_data_toggle);
3001 3001 SetTD_devaddr(uhcip, current_td, ph->p_usba_device->usb_addr);
3002 3002 SetTD_endpt(uhcip, current_td, ph->p_ep.bEndpointAddress &
3003 3003 END_POINT_ADDRESS_MASK);
3004 3004 SetTD_PID(uhcip, current_td, tw->tw_direction);
3005 3005
3006 3006 /* Get the right buffer address for the current TD */
3007 3007 switch (UHCI_XFER_TYPE(ept)) {
3008 3008 case USB_EP_ATTR_ISOCH:
3009 3009 buf_addr = tw->tw_isoc_bufs[offset].cookie.dmac_address;
3010 3010 break;
3011 3011 case USB_EP_ATTR_BULK:
3012 3012 buf_addr = uhci_get_tw_paddr_by_offs(uhcip, offset,
3013 3013 length, tw);
3014 3014 break;
3015 3015 }
3016 3016 SetTD32(uhcip, current_td->buffer_address, buf_addr);
3017 3017
3018 3018 /*
3019 3019 * Adjust the data toggle.
3020 3020 * The data toggle bit must always be 0 for isoc transfers.
3021 3021 * And set the "iso" bit in the TD for isoc transfers.
3022 3022 */
3023 3023 if (UHCI_XFER_TYPE(ept) == USB_EP_ATTR_ISOCH) {
3024 3024 pp->pp_data_toggle = 0;
3025 3025 SetTD_iso(uhcip, current_td, 1);
3026 3026 } else {
3027 3027 ADJ_DATA_TOGGLE(pp);
3028 3028 next_td->qh_td_prev = current_td;
3029 3029 pp->pp_qh->td_tailp = next_td;
3030 3030 }
3031 3031
3032 3032 current_td->outst_td_next = NULL;
3033 3033 current_td->outst_td_prev = uhcip->uhci_outst_tds_tail;
3034 3034 if (uhcip->uhci_outst_tds_head == NULL) {
3035 3035 uhcip->uhci_outst_tds_head = current_td;
3036 3036 } else {
3037 3037 uhcip->uhci_outst_tds_tail->outst_td_next = current_td;
3038 3038 }
3039 3039 uhcip->uhci_outst_tds_tail = current_td;
3040 3040 current_td->tw = tw;
3041 3041
3042 3042 if (tw->tw_hctd_head == NULL) {
3043 3043 ASSERT(tw->tw_hctd_tail == NULL);
3044 3044 tw->tw_hctd_head = current_td;
3045 3045 tw->tw_hctd_tail = current_td;
3046 3046 } else {
3047 3047 /* Add the td to the end of the list */
3048 3048 tw->tw_hctd_tail->tw_td_next = current_td;
3049 3049 tw->tw_hctd_tail = current_td;
3050 3050 }
3051 3051
3052 3052 mutex_exit(&ph->p_usba_device->usb_mutex);
3053 3053 }
3054 3054
3055 3055
3056 3056 /*
3057 3057 * uhci_alloc_bulk_isoc_tds:
3058 3058 * - Allocates the isoc/bulk TD pools. It will allocate one whole
3059 3059 * pool to store all the TDs if the system allows. Only when the
3060 3060 * first allocation fails, it tries to allocate several small
3061 3061 * pools with each pool limited in physical page size.
3062 3062 */
3063 3063 static int
3064 3064 uhci_alloc_bulk_isoc_tds(
3065 3065 uhci_state_t *uhcip,
3066 3066 uint_t num_tds,
3067 3067 uhci_bulk_isoc_xfer_t *info)
3068 3068 {
3069 3069 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
3070 3070 "uhci_alloc_bulk_isoc_tds: num_tds: 0x%x info: 0x%p",
3071 3071 num_tds, (void *)info);
3072 3072
3073 3073 info->num_pools = 1;
3074 3074 /* allocate as a whole pool at the first time */
3075 3075 if (uhci_alloc_memory_for_tds(uhcip, num_tds, info) !=
3076 3076 USB_SUCCESS) {
3077 3077 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
3078 3078 "alloc_memory_for_tds failed: num_tds %d num_pools %d",
3079 3079 num_tds, info->num_pools);
3080 3080
3081 3081 /* reduce the td number per pool and alloc again */
3082 3082 info->num_pools = num_tds / UHCI_MAX_TD_NUM_PER_POOL;
3083 3083 if (num_tds % UHCI_MAX_TD_NUM_PER_POOL) {
3084 3084 info->num_pools++;
3085 3085 }
3086 3086
3087 3087 if (uhci_alloc_memory_for_tds(uhcip, num_tds, info) !=
3088 3088 USB_SUCCESS) {
3089 3089 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
3090 3090 "alloc_memory_for_tds failed: num_tds %d "
3091 3091 "num_pools %d", num_tds, info->num_pools);
3092 3092
3093 3093 return (USB_NO_RESOURCES);
3094 3094 }
3095 3095 }
3096 3096
3097 3097 return (USB_SUCCESS);
3098 3098 }
3099 3099
3100 3100
3101 3101 /*
3102 3102 * uhci_alloc_memory_for_tds:
3103 3103 * - Allocates memory for the isoc/bulk td pools.
3104 3104 */
3105 3105 static int
3106 3106 uhci_alloc_memory_for_tds(
3107 3107 uhci_state_t *uhcip,
3108 3108 uint_t num_tds,
3109 3109 uhci_bulk_isoc_xfer_t *info)
3110 3110 {
3111 3111 int result, i, j, err;
3112 3112 size_t real_length;
3113 3113 uint_t ccount, num;
3114 3114 ddi_device_acc_attr_t dev_attr;
3115 3115 uhci_bulk_isoc_td_pool_t *td_pool_ptr1, *td_pool_ptr2;
3116 3116
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3117 3117 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
3118 3118 "uhci_alloc_memory_for_tds: num_tds: 0x%x info: 0x%p "
3119 3119 "num_pools: %u", num_tds, (void *)info, info->num_pools);
3120 3120
3121 3121 /* The host controller will be little endian */
3122 3122 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
3123 3123 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
3124 3124 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
3125 3125
3126 3126 /* Allocate the TD pool structures */
3127 - if ((info->td_pools = kmem_zalloc(
3128 - (sizeof (uhci_bulk_isoc_td_pool_t) * info->num_pools),
3129 - KM_SLEEP)) == NULL) {
3130 - USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
3131 - "uhci_alloc_memory_for_tds: alloc td_pools failed");
3132 -
3133 - return (USB_FAILURE);
3134 - }
3127 + info->td_pools = kmem_zalloc((sizeof (uhci_bulk_isoc_td_pool_t) *
3128 + info->num_pools), KM_SLEEP);
3135 3129
3136 3130 for (i = 0; i < info->num_pools; i++) {
3137 3131 if (info->num_pools == 1) {
3138 3132 num = num_tds;
3139 3133 } else if (i < (info->num_pools - 1)) {
3140 3134 num = UHCI_MAX_TD_NUM_PER_POOL;
3141 3135 } else {
3142 3136 num = (num_tds % UHCI_MAX_TD_NUM_PER_POOL);
3143 3137 }
3144 3138
3145 3139 td_pool_ptr1 = &info->td_pools[i];
3146 3140
3147 3141 /* Allocate the bulk TD pool DMA handle */
3148 3142 if (ddi_dma_alloc_handle(uhcip->uhci_dip,
3149 3143 &uhcip->uhci_dma_attr, DDI_DMA_SLEEP, 0,
3150 3144 &td_pool_ptr1->dma_handle) != DDI_SUCCESS) {
3151 3145
3152 3146 for (j = 0; j < i; j++) {
3153 3147 td_pool_ptr2 = &info->td_pools[j];
3154 3148 result = ddi_dma_unbind_handle(
3155 3149 td_pool_ptr2->dma_handle);
3156 3150 ASSERT(result == DDI_SUCCESS);
3157 3151 ddi_dma_mem_free(&td_pool_ptr2->mem_handle);
3158 3152 ddi_dma_free_handle(&td_pool_ptr2->dma_handle);
3159 3153 }
3160 3154
3161 3155 kmem_free(info->td_pools,
3162 3156 (sizeof (uhci_bulk_isoc_td_pool_t) *
3163 3157 info->num_pools));
3164 3158
3165 3159 return (USB_FAILURE);
3166 3160 }
3167 3161
3168 3162 /* Allocate the memory for the bulk TD pool */
3169 3163 if (ddi_dma_mem_alloc(td_pool_ptr1->dma_handle,
3170 3164 num * sizeof (uhci_td_t), &dev_attr,
3171 3165 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 0,
3172 3166 &td_pool_ptr1->pool_addr, &real_length,
3173 3167 &td_pool_ptr1->mem_handle) != DDI_SUCCESS) {
3174 3168
3175 3169 ddi_dma_free_handle(&td_pool_ptr1->dma_handle);
3176 3170
3177 3171 for (j = 0; j < i; j++) {
3178 3172 td_pool_ptr2 = &info->td_pools[j];
3179 3173 result = ddi_dma_unbind_handle(
3180 3174 td_pool_ptr2->dma_handle);
3181 3175 ASSERT(result == DDI_SUCCESS);
3182 3176 ddi_dma_mem_free(&td_pool_ptr2->mem_handle);
3183 3177 ddi_dma_free_handle(&td_pool_ptr2->dma_handle);
3184 3178 }
3185 3179
3186 3180 kmem_free(info->td_pools,
3187 3181 (sizeof (uhci_bulk_isoc_td_pool_t) *
3188 3182 info->num_pools));
3189 3183
3190 3184 return (USB_FAILURE);
3191 3185 }
3192 3186
3193 3187 /* Map the bulk TD pool into the I/O address space */
3194 3188 result = ddi_dma_addr_bind_handle(td_pool_ptr1->dma_handle,
3195 3189 NULL, (caddr_t)td_pool_ptr1->pool_addr, real_length,
3196 3190 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
3197 3191 &td_pool_ptr1->cookie, &ccount);
3198 3192
3199 3193 /* Process the result */
3200 3194 err = USB_SUCCESS;
3201 3195
3202 3196 if (result != DDI_DMA_MAPPED) {
3203 3197 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
3204 3198 "uhci_allocate_memory_for_tds: Result = %d",
3205 3199 result);
3206 3200 uhci_decode_ddi_dma_addr_bind_handle_result(uhcip,
3207 3201 result);
3208 3202
3209 3203 err = USB_FAILURE;
3210 3204 }
3211 3205
3212 3206 if ((result == DDI_DMA_MAPPED) && (ccount != 1)) {
3213 3207 /* The cookie count should be 1 */
3214 3208 USB_DPRINTF_L2(PRINT_MASK_ATTA,
3215 3209 uhcip->uhci_log_hdl,
3216 3210 "uhci_allocate_memory_for_tds: "
3217 3211 "More than 1 cookie");
3218 3212
3219 3213 result = ddi_dma_unbind_handle(
3220 3214 td_pool_ptr1->dma_handle);
3221 3215 ASSERT(result == DDI_SUCCESS);
3222 3216
3223 3217 err = USB_FAILURE;
3224 3218 }
3225 3219
3226 3220 if (err == USB_FAILURE) {
3227 3221
3228 3222 ddi_dma_mem_free(&td_pool_ptr1->mem_handle);
3229 3223 ddi_dma_free_handle(&td_pool_ptr1->dma_handle);
3230 3224
3231 3225 for (j = 0; j < i; j++) {
3232 3226 td_pool_ptr2 = &info->td_pools[j];
3233 3227 result = ddi_dma_unbind_handle(
3234 3228 td_pool_ptr2->dma_handle);
3235 3229 ASSERT(result == DDI_SUCCESS);
3236 3230 ddi_dma_mem_free(&td_pool_ptr2->mem_handle);
3237 3231 ddi_dma_free_handle(&td_pool_ptr2->dma_handle);
3238 3232 }
3239 3233
3240 3234 kmem_free(info->td_pools,
3241 3235 (sizeof (uhci_bulk_isoc_td_pool_t) *
3242 3236 info->num_pools));
3243 3237
3244 3238 return (USB_FAILURE);
3245 3239 }
3246 3240
3247 3241 bzero((void *)td_pool_ptr1->pool_addr,
3248 3242 num * sizeof (uhci_td_t));
3249 3243 td_pool_ptr1->num_tds = (ushort_t)num;
3250 3244 }
3251 3245
3252 3246 return (USB_SUCCESS);
3253 3247 }
3254 3248
3255 3249
3256 3250 /*
3257 3251 * uhci_handle_bulk_td:
3258 3252 *
3259 3253 * Handles the completed bulk transfer descriptors
3260 3254 */
3261 3255 void
3262 3256 uhci_handle_bulk_td(uhci_state_t *uhcip, uhci_td_t *td)
3263 3257 {
3264 3258 uint_t num_bulk_tds, index, td_count, j;
3265 3259 usb_cr_t error;
3266 3260 uint_t length, bytes_xfered;
3267 3261 ushort_t MaxPacketSize;
3268 3262 uint32_t buf_offs, paddr;
3269 3263 uhci_td_t *bulk_td_ptr, *current_dummy, *td_head;
3270 3264 uhci_td_t *tmp_td;
3271 3265 queue_head_t *qh, *next_qh;
3272 3266 uhci_trans_wrapper_t *tw = td->tw;
3273 3267 uhci_pipe_private_t *pp = tw->tw_pipe_private;
3274 3268 uhci_bulk_isoc_xfer_t *bulk_xfer_info;
3275 3269 uhci_bulk_isoc_td_pool_t *td_pool_ptr;
3276 3270 usba_pipe_handle_data_t *ph;
3277 3271
3278 3272 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
3279 3273 "uhci_handle_bulk_td: td = 0x%p tw = 0x%p", (void *)td, (void *)tw);
3280 3274
3281 3275 /*
3282 3276 * Update the tw_bytes_pending, and tw_bytes_xfered
3283 3277 */
3284 3278 bytes_xfered = ZERO_LENGTH;
3285 3279
3286 3280 /*
3287 3281 * Check whether there are any errors occurred in the xfer.
3288 3282 * If so, update the data_toggle for the queue head and
3289 3283 * return error to the upper layer.
3290 3284 */
3291 3285 if (GetTD_status(uhcip, td) & TD_STATUS_MASK) {
3292 3286 uhci_handle_bulk_td_errors(uhcip, td);
3293 3287
3294 3288 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
3295 3289 "uhci_handle_bulk_td: error; data toggle: 0x%x",
3296 3290 pp->pp_data_toggle);
3297 3291
3298 3292 return;
3299 3293 }
3300 3294
3301 3295 /*
3302 3296 * Update the tw_bytes_pending, and tw_bytes_xfered
3303 3297 */
3304 3298 bytes_xfered = GetTD_alen(uhcip, td);
3305 3299 if (bytes_xfered != ZERO_LENGTH) {
3306 3300 tw->tw_bytes_pending -= (bytes_xfered + 1);
3307 3301 tw->tw_bytes_xfered += (bytes_xfered + 1);
3308 3302 }
3309 3303
3310 3304 /*
3311 3305 * Get Bulk pipe information and pipe handle
3312 3306 */
3313 3307 bulk_xfer_info = pp->pp_qh->bulk_xfer_info;
3314 3308 ph = tw->tw_pipe_private->pp_pipe_handle;
3315 3309
3316 3310 /*
3317 3311 * Check whether data underrun occurred.
3318 3312 * If so, complete the transfer
3319 3313 * Update the data toggle bit
3320 3314 */
3321 3315 if (bytes_xfered != GetTD_mlen(uhcip, td)) {
3322 3316 bulk_xfer_info->num_tds = 1;
3323 3317 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
3324 3318 "uhci_handle_bulk_td: Data underrun occured");
3325 3319
3326 3320 pp->pp_data_toggle = GetTD_dtogg(uhcip, td) == 0 ? 1 : 0;
3327 3321 }
3328 3322
3329 3323 /*
3330 3324 * If the TD's in the current frame are completed, then check
3331 3325 * whether we have any more bytes to xfer. If so, insert TD's.
3332 3326 * If no more bytes needs to be transferred, then do callback to the
3333 3327 * upper layer.
3334 3328 * If the TD's in the current frame are not completed, then
3335 3329 * just delete the TD from the linked lists.
3336 3330 */
3337 3331 USB_DPRINTF_L3(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
3338 3332 "uhci_handle_bulk_td: completed TD data toggle: 0x%x",
3339 3333 GetTD_dtogg(uhcip, td));
3340 3334
3341 3335 if (--bulk_xfer_info->num_tds == 0) {
3342 3336 uhci_delete_td(uhcip, td);
3343 3337
3344 3338 if ((tw->tw_bytes_pending) &&
3345 3339 (GetTD_mlen(uhcip, td) - GetTD_alen(uhcip, td) == 0)) {
3346 3340
3347 3341 MaxPacketSize = pp->pp_pipe_handle->p_ep.wMaxPacketSize;
3348 3342 length = MaxPacketSize;
3349 3343
3350 3344 qh = pp->pp_qh;
3351 3345 paddr = GetQH32(uhcip, qh->link_ptr) & QH_LINK_PTR_MASK;
3352 3346 if (GetQH32(uhcip, qh->link_ptr) !=
3353 3347 GetQH32(uhcip,
3354 3348 uhcip->uhci_bulk_xfers_q_head->link_ptr)) {
3355 3349 next_qh = QH_VADDR(paddr);
3356 3350 SetQH32(uhcip, qh->prev_qh->link_ptr,
3357 3351 paddr|(0x2));
3358 3352 next_qh->prev_qh = qh->prev_qh;
3359 3353 SetQH32(uhcip, qh->link_ptr,
3360 3354 GetQH32(uhcip,
3361 3355 uhcip->uhci_bulk_xfers_q_head->link_ptr));
3362 3356 qh->prev_qh = uhcip->uhci_bulk_xfers_q_tail;
3363 3357 SetQH32(uhcip,
3364 3358 uhcip->uhci_bulk_xfers_q_tail->link_ptr,
3365 3359 QH_PADDR(qh) | 0x2);
3366 3360 uhcip->uhci_bulk_xfers_q_tail = qh;
3367 3361 }
3368 3362
3369 3363 if ((tw->tw_bytes_pending / MaxPacketSize) >=
3370 3364 MAX_NUM_BULK_TDS_PER_XFER) {
3371 3365 num_bulk_tds = MAX_NUM_BULK_TDS_PER_XFER;
3372 3366 } else {
3373 3367 num_bulk_tds =
3374 3368 (tw->tw_bytes_pending / MaxPacketSize);
3375 3369 if (tw->tw_bytes_pending % MaxPacketSize) {
3376 3370 num_bulk_tds++;
3377 3371 length = (tw->tw_bytes_pending %
3378 3372 MaxPacketSize);
3379 3373 }
3380 3374 }
3381 3375
3382 3376 current_dummy = pp->pp_qh->td_tailp;
3383 3377 td_pool_ptr = &bulk_xfer_info->td_pools[0];
3384 3378 bulk_td_ptr = (uhci_td_t *)td_pool_ptr->pool_addr;
3385 3379 buf_offs = tw->tw_bytes_xfered;
3386 3380 td_count = num_bulk_tds;
3387 3381 index = 0;
3388 3382
3389 3383 /* reuse the TDs to transfer more data */
3390 3384 while (td_count > 0) {
3391 3385 for (j = 0;
3392 3386 (j < (td_pool_ptr->num_tds - 1)) &&
3393 3387 (td_count > 1); j++, td_count--) {
3394 3388 uhci_fill_in_bulk_isoc_td(uhcip,
3395 3389 &bulk_td_ptr[j], &bulk_td_ptr[j+1],
3396 3390 BULKTD_PADDR(td_pool_ptr,
3397 3391 &bulk_td_ptr[j+1]), ph, buf_offs,
3398 3392 MaxPacketSize, tw);
3399 3393 buf_offs += MaxPacketSize;
3400 3394 }
3401 3395
3402 3396 if (td_count == 1) {
3403 3397 uhci_fill_in_bulk_isoc_td(uhcip,
3404 3398 &bulk_td_ptr[j], current_dummy,
3405 3399 TD_PADDR(current_dummy), ph,
3406 3400 buf_offs, length, tw);
3407 3401
3408 3402 break;
3409 3403 } else {
3410 3404 tmp_td = &bulk_td_ptr[j];
3411 3405 ASSERT(index <
3412 3406 (bulk_xfer_info->num_pools - 1));
3413 3407 td_pool_ptr = &bulk_xfer_info->
3414 3408 td_pools[index + 1];
3415 3409 bulk_td_ptr = (uhci_td_t *)
3416 3410 td_pool_ptr->pool_addr;
3417 3411 uhci_fill_in_bulk_isoc_td(uhcip,
3418 3412 tmp_td, &bulk_td_ptr[0],
3419 3413 BULKTD_PADDR(td_pool_ptr,
3420 3414 &bulk_td_ptr[0]), ph, buf_offs,
3421 3415 MaxPacketSize, tw);
3422 3416 buf_offs += MaxPacketSize;
3423 3417 td_count--;
3424 3418 index++;
3425 3419 }
3426 3420 }
3427 3421
3428 3422 pp->pp_qh->bulk_xfer_info = bulk_xfer_info;
3429 3423 bulk_xfer_info->num_tds = (ushort_t)num_bulk_tds;
3430 3424 SetQH32(uhcip, pp->pp_qh->element_ptr,
3431 3425 bulk_xfer_info->td_pools[0].cookie.dmac_address);
3432 3426 } else {
3433 3427 usba_pipe_handle_data_t *usb_pp = pp->pp_pipe_handle;
3434 3428
3435 3429 pp->pp_qh->bulk_xfer_info = NULL;
3436 3430
3437 3431 if (tw->tw_bytes_pending) {
3438 3432 /* Update the element pointer */
3439 3433 SetQH32(uhcip, pp->pp_qh->element_ptr,
3440 3434 TD_PADDR(pp->pp_qh->td_tailp));
3441 3435
3442 3436 /* Remove all the tds */
3443 3437 td_head = tw->tw_hctd_head;
3444 3438 while (td_head != NULL) {
3445 3439 uhci_delete_td(uhcip, td_head);
3446 3440 td_head = tw->tw_hctd_head;
3447 3441 }
3448 3442 }
3449 3443
3450 3444 if (tw->tw_direction == PID_IN) {
3451 3445 usb_req_attrs_t attrs = ((usb_bulk_req_t *)
3452 3446 tw->tw_curr_xfer_reqp)->bulk_attributes;
3453 3447
3454 3448 error = USB_CR_OK;
3455 3449
3456 3450 /* Data run occurred */
3457 3451 if (tw->tw_bytes_pending &&
3458 3452 (!(attrs & USB_ATTRS_SHORT_XFER_OK))) {
3459 3453 error = USB_CR_DATA_UNDERRUN;
3460 3454 }
3461 3455
3462 3456 uhci_sendup_td_message(uhcip, error, tw);
3463 3457 } else {
3464 3458 uhci_do_byte_stats(uhcip, tw->tw_length,
3465 3459 usb_pp->p_ep.bmAttributes,
3466 3460 usb_pp->p_ep.bEndpointAddress);
3467 3461
3468 3462 /* Data underrun occurred */
3469 3463 if (tw->tw_bytes_pending) {
3470 3464
3471 3465 tw->tw_data->b_rptr +=
3472 3466 tw->tw_bytes_xfered;
3473 3467
3474 3468 USB_DPRINTF_L2(PRINT_MASK_ATTA,
3475 3469 uhcip->uhci_log_hdl,
3476 3470 "uhci_handle_bulk_td: "
3477 3471 "data underrun occurred");
3478 3472
3479 3473 uhci_hcdi_callback(uhcip, pp,
3480 3474 tw->tw_pipe_private->pp_pipe_handle,
3481 3475 tw, USB_CR_DATA_UNDERRUN);
3482 3476 } else {
3483 3477 uhci_hcdi_callback(uhcip, pp,
3484 3478 tw->tw_pipe_private->pp_pipe_handle,
3485 3479 tw, USB_CR_OK);
3486 3480 }
3487 3481 } /* direction */
3488 3482
3489 3483 /* Deallocate DMA memory */
3490 3484 uhci_deallocate_tw(uhcip, pp, tw);
3491 3485 for (j = 0; j < bulk_xfer_info->num_pools; j++) {
3492 3486 td_pool_ptr = &bulk_xfer_info->td_pools[j];
3493 3487 (void) ddi_dma_unbind_handle(
3494 3488 td_pool_ptr->dma_handle);
3495 3489 ddi_dma_mem_free(&td_pool_ptr->mem_handle);
3496 3490 ddi_dma_free_handle(&td_pool_ptr->dma_handle);
3497 3491 }
3498 3492 kmem_free(bulk_xfer_info->td_pools,
3499 3493 (sizeof (uhci_bulk_isoc_td_pool_t) *
3500 3494 bulk_xfer_info->num_pools));
3501 3495 kmem_free(bulk_xfer_info,
3502 3496 sizeof (uhci_bulk_isoc_xfer_t));
3503 3497
3504 3498 /*
3505 3499 * When there are no pending bulk commands, point the
3506 3500 * end of the lattice tree to NULL. This will make sure
3507 3501 * that the HC control does not loop anymore and PCI
3508 3502 * bus is not affected.
3509 3503 */
3510 3504 if (--uhcip->uhci_pending_bulk_cmds == 0) {
3511 3505 uhcip->uhci_bulk_xfers_q_tail->link_ptr =
3512 3506 HC_END_OF_LIST;
3513 3507 USB_DPRINTF_L3(PRINT_MASK_ATTA,
3514 3508 uhcip->uhci_log_hdl,
3515 3509 "uhci_handle_bulk_td: count = %d",
3516 3510 uhcip->uhci_pending_bulk_cmds);
3517 3511 }
3518 3512 }
3519 3513 } else {
3520 3514 uhci_delete_td(uhcip, td);
3521 3515 }
3522 3516 }
3523 3517
3524 3518
3525 3519 void
3526 3520 uhci_handle_bulk_td_errors(uhci_state_t *uhcip, uhci_td_t *td)
3527 3521 {
3528 3522 usb_cr_t usb_err;
3529 3523 uint32_t paddr_tail, element_ptr, paddr;
3530 3524 uhci_td_t *next_td;
3531 3525 uhci_pipe_private_t *pp;
3532 3526 uhci_trans_wrapper_t *tw = td->tw;
3533 3527 usba_pipe_handle_data_t *ph;
3534 3528 uhci_bulk_isoc_td_pool_t *td_pool_ptr = NULL;
3535 3529
3536 3530 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
3537 3531 "uhci_handle_bulk_td_errors: td = %p", (void *)td);
3538 3532
3539 3533 #ifdef DEBUG
3540 3534 uhci_print_td(uhcip, td);
3541 3535 #endif
3542 3536
3543 3537 tw = td->tw;
3544 3538 ph = tw->tw_pipe_private->pp_pipe_handle;
3545 3539 pp = (uhci_pipe_private_t *)ph->p_hcd_private;
3546 3540
3547 3541 /*
3548 3542 * Find the type of error occurred and return the error
3549 3543 * to the upper layer. And adjust the data toggle.
3550 3544 */
3551 3545 element_ptr = GetQH32(uhcip, pp->pp_qh->element_ptr) &
3552 3546 QH_ELEMENT_PTR_MASK;
3553 3547 paddr_tail = TD_PADDR(pp->pp_qh->td_tailp);
3554 3548
3555 3549 /*
3556 3550 * If a timeout occurs before a transfer has completed,
3557 3551 * the timeout handler sets the CRC/Timeout bit and clears the Active
3558 3552 * bit in the link_ptr for each td in the transfer.
3559 3553 * It then waits (at least) 1 ms so that any tds the controller might
3560 3554 * have been executing will have completed.
3561 3555 * So at this point element_ptr will point to either:
3562 3556 * 1) the next td for the transfer (which has not been executed,
3563 3557 * and has the CRC/Timeout status bit set and Active bit cleared),
3564 3558 * 2) the dummy td for this qh.
3565 3559 * So if the element_ptr does not point to the dummy td, we know
3566 3560 * it points to the next td that would have been executed.
3567 3561 * That td has the data toggle we want to save.
3568 3562 * All outstanding tds have been marked as CRC/Timeout,
3569 3563 * so it doesn't matter which td we pass to uhci_parse_td_error
3570 3564 * for the error status.
3571 3565 */
3572 3566 if (element_ptr != paddr_tail) {
3573 3567 paddr = (element_ptr & QH_ELEMENT_PTR_MASK);
3574 3568 uhci_get_bulk_td_by_paddr(uhcip, pp->pp_qh->bulk_xfer_info,
3575 3569 paddr, &td_pool_ptr);
3576 3570 next_td = BULKTD_VADDR(td_pool_ptr, paddr);
3577 3571 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
3578 3572 "uhci_handle_bulk_td_errors: next td = %p",
3579 3573 (void *)next_td);
3580 3574
3581 3575 usb_err = uhci_parse_td_error(uhcip, pp, next_td);
3582 3576 } else {
3583 3577 usb_err = uhci_parse_td_error(uhcip, pp, td);
3584 3578 }
3585 3579
3586 3580 /*
3587 3581 * Update the link pointer.
3588 3582 */
3589 3583 SetQH32(uhcip, pp->pp_qh->element_ptr, TD_PADDR(pp->pp_qh->td_tailp));
3590 3584
3591 3585 /*
3592 3586 * Send up number of bytes transferred before the error condition.
3593 3587 */
3594 3588 if ((tw->tw_direction == PID_OUT) && tw->tw_data) {
3595 3589 tw->tw_data->b_rptr += tw->tw_bytes_xfered;
3596 3590 }
3597 3591
3598 3592 uhci_remove_bulk_tds_tws(uhcip, tw->tw_pipe_private, UHCI_IN_ERROR);
3599 3593
3600 3594 /*
3601 3595 * When there are no pending bulk commands, point the end of the
3602 3596 * lattice tree to NULL. This will make sure that the HC control
3603 3597 * does not loop anymore and PCI bus is not affected.
3604 3598 */
3605 3599 if (--uhcip->uhci_pending_bulk_cmds == 0) {
3606 3600 uhcip->uhci_bulk_xfers_q_tail->link_ptr = HC_END_OF_LIST;
3607 3601 USB_DPRINTF_L3(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
3608 3602 "uhci_handle_bulk_td_errors: count = %d",
3609 3603 uhcip->uhci_pending_bulk_cmds);
3610 3604 }
3611 3605
3612 3606 uhci_hcdi_callback(uhcip, pp, ph, tw, usb_err);
3613 3607 uhci_deallocate_tw(uhcip, pp, tw);
3614 3608 }
3615 3609
3616 3610
3617 3611 /*
3618 3612 * uhci_get_bulk_td_by_paddr:
3619 3613 * Obtain the address of the TD pool the physical address falls in.
3620 3614 *
3621 3615 * td_pool_pp - pointer to the address of the TD pool containing the paddr
3622 3616 */
3623 3617 /* ARGSUSED */
3624 3618 static void
3625 3619 uhci_get_bulk_td_by_paddr(
3626 3620 uhci_state_t *uhcip,
3627 3621 uhci_bulk_isoc_xfer_t *info,
3628 3622 uint32_t paddr,
3629 3623 uhci_bulk_isoc_td_pool_t **td_pool_pp)
3630 3624 {
3631 3625 uint_t i = 0;
3632 3626
3633 3627 while (i < info->num_pools) {
3634 3628 *td_pool_pp = &info->td_pools[i];
3635 3629 if (((*td_pool_pp)->cookie.dmac_address <= paddr) &&
3636 3630 (((*td_pool_pp)->cookie.dmac_address +
3637 3631 (*td_pool_pp)->cookie.dmac_size) > paddr)) {
3638 3632
3639 3633 break;
3640 3634 }
3641 3635 i++;
3642 3636 }
3643 3637
3644 3638 ASSERT(i < info->num_pools);
3645 3639 }
3646 3640
3647 3641
3648 3642 void
3649 3643 uhci_remove_bulk_tds_tws(
3650 3644 uhci_state_t *uhcip,
3651 3645 uhci_pipe_private_t *pp,
3652 3646 int what)
3653 3647 {
3654 3648 uint_t rval, i;
3655 3649 uhci_td_t *head;
3656 3650 uhci_td_t *head_next;
3657 3651 usb_opaque_t curr_reqp;
3658 3652 uhci_bulk_isoc_xfer_t *info;
3659 3653 uhci_bulk_isoc_td_pool_t *td_pool_ptr;
3660 3654
3661 3655 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
3662 3656
3663 3657 if ((info = pp->pp_qh->bulk_xfer_info) == NULL) {
3664 3658
3665 3659 return;
3666 3660 }
3667 3661
3668 3662 head = uhcip->uhci_outst_tds_head;
3669 3663
3670 3664 while (head) {
3671 3665 uhci_trans_wrapper_t *tw_tmp = head->tw;
3672 3666 head_next = head->outst_td_next;
3673 3667
3674 3668 if (pp->pp_qh == tw_tmp->tw_pipe_private->pp_qh) {
3675 3669 curr_reqp = tw_tmp->tw_curr_xfer_reqp;
3676 3670 if (curr_reqp &&
3677 3671 ((what == UHCI_IN_CLOSE) ||
3678 3672 (what == UHCI_IN_RESET))) {
3679 3673 uhci_hcdi_callback(uhcip, pp,
3680 3674 pp->pp_pipe_handle,
3681 3675 tw_tmp, USB_CR_FLUSHED);
3682 3676 } /* end of curr_reqp */
3683 3677
3684 3678 uhci_delete_td(uhcip, head);
3685 3679
3686 3680 if (what == UHCI_IN_CLOSE || what == UHCI_IN_RESET) {
3687 3681 ASSERT(info->num_tds > 0);
3688 3682 if (--info->num_tds == 0) {
3689 3683 uhci_deallocate_tw(uhcip, pp, tw_tmp);
3690 3684
3691 3685 /*
3692 3686 * This will make sure that the HC
3693 3687 * does not loop anymore when there
3694 3688 * are no pending bulk commands.
3695 3689 */
3696 3690 if (--uhcip->uhci_pending_bulk_cmds
3697 3691 == 0) {
3698 3692 uhcip->uhci_bulk_xfers_q_tail->
3699 3693 link_ptr = HC_END_OF_LIST;
3700 3694 USB_DPRINTF_L3(PRINT_MASK_ATTA,
3701 3695 uhcip->uhci_log_hdl,
3702 3696 "uhci_remove_bulk_tds_tws:"
3703 3697 " count = %d",
3704 3698 uhcip->
3705 3699 uhci_pending_bulk_cmds);
3706 3700 }
3707 3701 }
3708 3702 }
3709 3703 }
3710 3704
3711 3705 head = head_next;
3712 3706 }
3713 3707
3714 3708 if (what == UHCI_IN_CLOSE || what == UHCI_IN_RESET) {
3715 3709 ASSERT(info->num_tds == 0);
3716 3710 }
3717 3711
3718 3712 for (i = 0; i < info->num_pools; i++) {
3719 3713 td_pool_ptr = &info->td_pools[i];
3720 3714 rval = ddi_dma_unbind_handle(td_pool_ptr->dma_handle);
3721 3715 ASSERT(rval == DDI_SUCCESS);
3722 3716 ddi_dma_mem_free(&td_pool_ptr->mem_handle);
3723 3717 ddi_dma_free_handle(&td_pool_ptr->dma_handle);
3724 3718 }
3725 3719 kmem_free(info->td_pools, (sizeof (uhci_bulk_isoc_td_pool_t) *
3726 3720 info->num_pools));
3727 3721 kmem_free(info, sizeof (uhci_bulk_isoc_xfer_t));
3728 3722 pp->pp_qh->bulk_xfer_info = NULL;
3729 3723 }
3730 3724
3731 3725
3732 3726 /*
3733 3727 * uhci_save_data_toggle ()
3734 3728 * Save the data toggle in the usba_device structure
3735 3729 */
3736 3730 void
3737 3731 uhci_save_data_toggle(uhci_pipe_private_t *pp)
3738 3732 {
3739 3733 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle;
3740 3734
3741 3735 /* Save the data toggle in the usb devices structure. */
3742 3736 mutex_enter(&ph->p_mutex);
3743 3737 usba_hcdi_set_data_toggle(ph->p_usba_device, ph->p_ep.bEndpointAddress,
3744 3738 pp->pp_data_toggle);
3745 3739 mutex_exit(&ph->p_mutex);
3746 3740 }
3747 3741
3748 3742 /*
3749 3743 * uhci_create_isoc_transfer_wrapper:
3750 3744 * Create a Transaction Wrapper (TW) for isoc transfer.
3751 3745 * This involves the allocating of DMA resources.
3752 3746 *
3753 3747 * For isoc transfers, one isoc transfer includes multiple packets
3754 3748 * and each packet may have a different length. So each packet is
3755 3749 * transfered by one TD. We only know the individual packet length
3756 3750 * won't exceed 1023 bytes, but we don't know exactly the lengths.
3757 3751 * It is hard to make one physically discontiguous DMA buffer which
3758 3752 * can fit in all the TDs like what can be done to the ctrl/bulk/
3759 3753 * intr transfers. It is also undesirable to make one physically
3760 3754 * contiguous DMA buffer for all the packets, since this may easily
3761 3755 * fail when the system is in low memory. So an individual DMA
3762 3756 * buffer is allocated for an individual isoc packet and each DMA
3763 3757 * buffer is physically contiguous. An extra structure is allocated
3764 3758 * to save the multiple DMA handles.
3765 3759 */
3766 3760 static uhci_trans_wrapper_t *
3767 3761 uhci_create_isoc_transfer_wrapper(
3768 3762 uhci_state_t *uhcip,
3769 3763 uhci_pipe_private_t *pp,
3770 3764 usb_isoc_req_t *req,
3771 3765 size_t length,
3772 3766 usb_flags_t usb_flags)
3773 3767 {
3774 3768 int result;
3775 3769 size_t real_length, strtlen, xfer_size;
3776 3770 uhci_trans_wrapper_t *tw;
3777 3771 ddi_device_acc_attr_t dev_attr;
3778 3772 ddi_dma_attr_t dma_attr;
3779 3773 int kmem_flag;
3780 3774 int (*dmamem_wait)(caddr_t);
3781 3775 uint_t i, j, ccount;
3782 3776 usb_isoc_req_t *tmp_req = req;
3783 3777
3784 3778 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
3785 3779
3786 3780 if (UHCI_XFER_TYPE(&pp->pp_pipe_handle->p_ep) != USB_EP_ATTR_ISOCH) {
3787 3781
3788 3782 return (NULL);
3789 3783 }
3790 3784
3791 3785 if ((req == NULL) && (UHCI_XFER_DIR(&pp->pp_pipe_handle->p_ep) ==
3792 3786 USB_EP_DIR_IN)) {
3793 3787 tmp_req = (usb_isoc_req_t *)pp->pp_client_periodic_in_reqp;
3794 3788 }
3795 3789
3796 3790 if (tmp_req == NULL) {
3797 3791
3798 3792 return (NULL);
3799 3793 }
3800 3794
3801 3795
3802 3796 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
3803 3797 "uhci_create_isoc_transfer_wrapper: length = 0x%lx flags = 0x%x",
3804 3798 length, usb_flags);
3805 3799
3806 3800 /* SLEEP flag should not be used in interrupt context */
3807 3801 if (servicing_interrupt()) {
3808 3802 kmem_flag = KM_NOSLEEP;
3809 3803 dmamem_wait = DDI_DMA_DONTWAIT;
3810 3804 } else {
3811 3805 kmem_flag = KM_SLEEP;
3812 3806 dmamem_wait = DDI_DMA_SLEEP;
3813 3807 }
3814 3808
3815 3809 /* Allocate space for the transfer wrapper */
3816 3810 if ((tw = kmem_zalloc(sizeof (uhci_trans_wrapper_t), kmem_flag)) ==
3817 3811 NULL) {
3818 3812 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
3819 3813 "uhci_create_isoc_transfer_wrapper: kmem_alloc failed");
3820 3814
3821 3815 return (NULL);
3822 3816 }
3823 3817
3824 3818 /* Allocate space for the isoc buffer handles */
3825 3819 strtlen = sizeof (uhci_isoc_buf_t) * tmp_req->isoc_pkts_count;
3826 3820 if ((tw->tw_isoc_bufs = kmem_zalloc(strtlen, kmem_flag)) == NULL) {
3827 3821 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
3828 3822 "uhci_create_isoc_transfer_wrapper: kmem_alloc "
3829 3823 "isoc buffer failed");
3830 3824 kmem_free(tw, sizeof (uhci_trans_wrapper_t));
3831 3825
3832 3826 return (NULL);
3833 3827 }
3834 3828
3835 3829 bcopy(&uhcip->uhci_dma_attr, &dma_attr, sizeof (ddi_dma_attr_t));
3836 3830 dma_attr.dma_attr_sgllen = 1;
3837 3831
3838 3832 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
3839 3833 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
3840 3834 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
3841 3835
3842 3836 /* Store the transfer length */
3843 3837 tw->tw_length = length;
3844 3838
3845 3839 for (i = 0; i < tmp_req->isoc_pkts_count; i++) {
3846 3840 tw->tw_isoc_bufs[i].index = (ushort_t)i;
3847 3841
3848 3842 /* Allocate the DMA handle */
3849 3843 if ((result = ddi_dma_alloc_handle(uhcip->uhci_dip, &dma_attr,
3850 3844 dmamem_wait, 0, &tw->tw_isoc_bufs[i].dma_handle)) !=
3851 3845 DDI_SUCCESS) {
3852 3846 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
3853 3847 "uhci_create_isoc_transfer_wrapper: "
3854 3848 "Alloc handle %d failed", i);
3855 3849
3856 3850 for (j = 0; j < i; j++) {
3857 3851 result = ddi_dma_unbind_handle(
3858 3852 tw->tw_isoc_bufs[j].dma_handle);
3859 3853 ASSERT(result == USB_SUCCESS);
3860 3854 ddi_dma_mem_free(&tw->tw_isoc_bufs[j].
3861 3855 mem_handle);
3862 3856 ddi_dma_free_handle(&tw->tw_isoc_bufs[j].
3863 3857 dma_handle);
3864 3858 }
3865 3859 kmem_free(tw->tw_isoc_bufs, strtlen);
3866 3860 kmem_free(tw, sizeof (uhci_trans_wrapper_t));
3867 3861
3868 3862 return (NULL);
3869 3863 }
3870 3864
3871 3865 /* Allocate the memory */
3872 3866 xfer_size = tmp_req->isoc_pkt_descr[i].isoc_pkt_length;
3873 3867 if ((result = ddi_dma_mem_alloc(tw->tw_isoc_bufs[i].dma_handle,
3874 3868 xfer_size, &dev_attr, DDI_DMA_CONSISTENT, dmamem_wait,
3875 3869 NULL, (caddr_t *)&tw->tw_isoc_bufs[i].buf_addr,
3876 3870 &real_length, &tw->tw_isoc_bufs[i].mem_handle)) !=
3877 3871 DDI_SUCCESS) {
3878 3872 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
3879 3873 "uhci_create_isoc_transfer_wrapper: "
3880 3874 "dma_mem_alloc %d fail", i);
3881 3875 ddi_dma_free_handle(&tw->tw_isoc_bufs[i].dma_handle);
3882 3876
3883 3877 for (j = 0; j < i; j++) {
3884 3878 result = ddi_dma_unbind_handle(
3885 3879 tw->tw_isoc_bufs[j].dma_handle);
3886 3880 ASSERT(result == USB_SUCCESS);
3887 3881 ddi_dma_mem_free(&tw->tw_isoc_bufs[j].
3888 3882 mem_handle);
3889 3883 ddi_dma_free_handle(&tw->tw_isoc_bufs[j].
3890 3884 dma_handle);
3891 3885 }
3892 3886 kmem_free(tw->tw_isoc_bufs, strtlen);
3893 3887 kmem_free(tw, sizeof (uhci_trans_wrapper_t));
3894 3888
3895 3889 return (NULL);
3896 3890 }
3897 3891
3898 3892 ASSERT(real_length >= xfer_size);
3899 3893
3900 3894 /* Bind the handle */
3901 3895 result = ddi_dma_addr_bind_handle(
3902 3896 tw->tw_isoc_bufs[i].dma_handle, NULL,
3903 3897 (caddr_t)tw->tw_isoc_bufs[i].buf_addr, real_length,
3904 3898 DDI_DMA_RDWR|DDI_DMA_CONSISTENT, dmamem_wait, NULL,
3905 3899 &tw->tw_isoc_bufs[i].cookie, &ccount);
3906 3900
3907 3901 if ((result == DDI_DMA_MAPPED) && (ccount == 1)) {
3908 3902 tw->tw_isoc_bufs[i].length = xfer_size;
3909 3903
3910 3904 continue;
3911 3905 } else {
3912 3906 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
3913 3907 "uhci_create_isoc_transfer_wrapper: "
3914 3908 "Bind handle %d failed", i);
3915 3909 if (result == DDI_DMA_MAPPED) {
3916 3910 result = ddi_dma_unbind_handle(
3917 3911 tw->tw_isoc_bufs[i].dma_handle);
3918 3912 ASSERT(result == USB_SUCCESS);
3919 3913 }
3920 3914 ddi_dma_mem_free(&tw->tw_isoc_bufs[i].mem_handle);
3921 3915 ddi_dma_free_handle(&tw->tw_isoc_bufs[i].dma_handle);
3922 3916
3923 3917 for (j = 0; j < i; j++) {
3924 3918 result = ddi_dma_unbind_handle(
3925 3919 tw->tw_isoc_bufs[j].dma_handle);
3926 3920 ASSERT(result == USB_SUCCESS);
3927 3921 ddi_dma_mem_free(&tw->tw_isoc_bufs[j].
3928 3922 mem_handle);
3929 3923 ddi_dma_free_handle(&tw->tw_isoc_bufs[j].
3930 3924 dma_handle);
3931 3925 }
3932 3926 kmem_free(tw->tw_isoc_bufs, strtlen);
3933 3927 kmem_free(tw, sizeof (uhci_trans_wrapper_t));
3934 3928
3935 3929 return (NULL);
3936 3930 }
3937 3931 }
3938 3932
3939 3933 tw->tw_ncookies = tmp_req->isoc_pkts_count;
3940 3934 tw->tw_isoc_strtlen = strtlen;
3941 3935
3942 3936 /*
3943 3937 * Only allow one wrapper to be added at a time. Insert the
3944 3938 * new transaction wrapper into the list for this pipe.
3945 3939 */
3946 3940 if (pp->pp_tw_head == NULL) {
3947 3941 pp->pp_tw_head = tw;
3948 3942 pp->pp_tw_tail = tw;
3949 3943 } else {
3950 3944 pp->pp_tw_tail->tw_next = tw;
3951 3945 pp->pp_tw_tail = tw;
3952 3946 ASSERT(tw->tw_next == NULL);
3953 3947 }
3954 3948
3955 3949 /* Store a back pointer to the pipe private structure */
3956 3950 tw->tw_pipe_private = pp;
3957 3951
3958 3952 /* Store the transfer type - synchronous or asynchronous */
3959 3953 tw->tw_flags = usb_flags;
3960 3954
3961 3955 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
3962 3956 "uhci_create_isoc_transfer_wrapper: tw = 0x%p, ncookies = %u",
3963 3957 (void *)tw, tw->tw_ncookies);
3964 3958
3965 3959 return (tw);
3966 3960 }
3967 3961
3968 3962 /*
3969 3963 * uhci_insert_isoc_td:
3970 3964 * - Create transfer wrapper
3971 3965 * - Allocate memory for the isoc td's
3972 3966 * - Fill up all the TD's and submit to the HC
3973 3967 * - Update all the linked lists
3974 3968 */
3975 3969 int
3976 3970 uhci_insert_isoc_td(
3977 3971 uhci_state_t *uhcip,
3978 3972 usba_pipe_handle_data_t *ph,
3979 3973 usb_isoc_req_t *isoc_req,
3980 3974 size_t length,
3981 3975 usb_flags_t flags)
3982 3976 {
3983 3977 int rval = USB_SUCCESS;
3984 3978 int error;
3985 3979 uint_t ddic;
3986 3980 uint32_t i, j, index;
3987 3981 uint32_t bytes_to_xfer;
3988 3982 uint32_t expired_frames = 0;
3989 3983 usb_frame_number_t start_frame, end_frame, current_frame;
3990 3984 uhci_td_t *td_ptr;
3991 3985 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private;
3992 3986 uhci_trans_wrapper_t *tw;
3993 3987 uhci_bulk_isoc_xfer_t *isoc_xfer_info;
3994 3988 uhci_bulk_isoc_td_pool_t *td_pool_ptr;
3995 3989
3996 3990 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
3997 3991 "uhci_insert_isoc_td: ph = 0x%p isoc req = %p length = %lu",
3998 3992 (void *)ph, (void *)isoc_req, length);
3999 3993
4000 3994 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
4001 3995
4002 3996 /* Allocate a transfer wrapper */
4003 3997 if ((tw = uhci_create_isoc_transfer_wrapper(uhcip, pp, isoc_req,
4004 3998 length, flags)) == NULL) {
4005 3999 USB_DPRINTF_L2(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4006 4000 "uhci_insert_isoc_td: TW allocation failed");
4007 4001
4008 4002 return (USB_NO_RESOURCES);
4009 4003 }
4010 4004
4011 4005 /* Save current isochronous request pointer */
4012 4006 tw->tw_curr_xfer_reqp = (usb_opaque_t)isoc_req;
4013 4007
4014 4008 /*
4015 4009 * Initialize the transfer wrapper. These values are useful
4016 4010 * for sending back the reply.
4017 4011 */
4018 4012 tw->tw_handle_td = uhci_handle_isoc_td;
4019 4013 tw->tw_handle_callback_value = NULL;
4020 4014 tw->tw_direction = (UHCI_XFER_DIR(&ph->p_ep) == USB_EP_DIR_OUT) ?
4021 4015 PID_OUT : PID_IN;
4022 4016
4023 4017 /*
4024 4018 * If the transfer isoc send, then copy the data from the request
4025 4019 * to the transfer wrapper.
4026 4020 */
4027 4021 if ((tw->tw_direction == PID_OUT) && length) {
4028 4022 uchar_t *p;
4029 4023
4030 4024 ASSERT(isoc_req->isoc_data != NULL);
4031 4025 p = isoc_req->isoc_data->b_rptr;
4032 4026
4033 4027 /* Copy the data into the message */
4034 4028 for (i = 0; i < isoc_req->isoc_pkts_count; i++) {
4035 4029 ddi_rep_put8(tw->tw_isoc_bufs[i].mem_handle,
4036 4030 p, (uint8_t *)tw->tw_isoc_bufs[i].buf_addr,
4037 4031 isoc_req->isoc_pkt_descr[i].isoc_pkt_length,
4038 4032 DDI_DEV_AUTOINCR);
4039 4033 p += isoc_req->isoc_pkt_descr[i].isoc_pkt_length;
4040 4034 }
4041 4035 }
4042 4036
4043 4037 if (tw->tw_direction == PID_IN) {
4044 4038 if ((rval = uhci_allocate_periodic_in_resource(uhcip, pp, tw,
4045 4039 flags)) != USB_SUCCESS) {
4046 4040 USB_DPRINTF_L2(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4047 4041 "uhci_insert_isoc_td: isoc_req_t alloc failed");
4048 4042 uhci_deallocate_tw(uhcip, pp, tw);
4049 4043
4050 4044 return (rval);
4051 4045 }
4052 4046
4053 4047 isoc_req = (usb_isoc_req_t *)tw->tw_curr_xfer_reqp;
4054 4048 }
4055 4049
4056 4050 tw->tw_isoc_req = (usb_isoc_req_t *)tw->tw_curr_xfer_reqp;
4057 4051
4058 4052 /* Get the pointer to the isoc_xfer_info structure */
4059 4053 isoc_xfer_info = (uhci_bulk_isoc_xfer_t *)&tw->tw_xfer_info;
4060 4054 isoc_xfer_info->num_tds = isoc_req->isoc_pkts_count;
4061 4055
4062 4056 /*
4063 4057 * Allocate memory for isoc tds
4064 4058 */
4065 4059 if ((rval = uhci_alloc_bulk_isoc_tds(uhcip, isoc_req->isoc_pkts_count,
4066 4060 isoc_xfer_info)) != USB_SUCCESS) {
4067 4061 USB_DPRINTF_L2(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4068 4062 "uhci_alloc_bulk_isoc_td: Memory allocation failure");
4069 4063
4070 4064 if (tw->tw_direction == PID_IN) {
4071 4065 uhci_deallocate_periodic_in_resource(uhcip, pp, tw);
4072 4066 }
4073 4067 uhci_deallocate_tw(uhcip, pp, tw);
4074 4068
4075 4069 return (rval);
4076 4070 }
4077 4071
4078 4072 /*
4079 4073 * Get the isoc td pool address, buffer address and
4080 4074 * max packet size that the device supports.
4081 4075 */
4082 4076 td_pool_ptr = &isoc_xfer_info->td_pools[0];
4083 4077 td_ptr = (uhci_td_t *)td_pool_ptr->pool_addr;
4084 4078 index = 0;
4085 4079
4086 4080 /*
4087 4081 * Fill up the isoc tds
4088 4082 */
4089 4083 USB_DPRINTF_L3(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4090 4084 "uhci_insert_isoc_td : isoc pkts %d", isoc_req->isoc_pkts_count);
4091 4085
4092 4086 for (i = 0; i < isoc_xfer_info->num_pools; i++) {
4093 4087 for (j = 0; j < td_pool_ptr->num_tds; j++) {
4094 4088 bytes_to_xfer =
4095 4089 isoc_req->isoc_pkt_descr[index].isoc_pkt_length;
4096 4090
4097 4091 uhci_fill_in_bulk_isoc_td(uhcip, &td_ptr[j],
4098 4092 (uhci_td_t *)NULL, HC_END_OF_LIST, ph, index,
4099 4093 bytes_to_xfer, tw);
4100 4094 td_ptr[j].isoc_pkt_index = (ushort_t)index;
4101 4095 index++;
4102 4096 }
4103 4097
4104 4098 if (i < (isoc_xfer_info->num_pools - 1)) {
4105 4099 td_pool_ptr = &isoc_xfer_info->td_pools[i + 1];
4106 4100 td_ptr = (uhci_td_t *)td_pool_ptr->pool_addr;
4107 4101 }
4108 4102 }
4109 4103
4110 4104 /*
4111 4105 * Get the starting frame number.
4112 4106 * The client drivers sets the flag USB_ATTRS_ISOC_XFER_ASAP to inform
4113 4107 * the HCD to care of starting frame number.
4114 4108 *
4115 4109 * Following code is very time critical. So, perform atomic execution.
4116 4110 */
4117 4111 ddic = ddi_enter_critical();
4118 4112 current_frame = uhci_get_sw_frame_number(uhcip);
4119 4113
4120 4114 if (isoc_req->isoc_attributes & USB_ATTRS_ISOC_START_FRAME) {
4121 4115 start_frame = isoc_req->isoc_frame_no;
4122 4116 end_frame = start_frame + isoc_req->isoc_pkts_count;
4123 4117
4124 4118 /* Check available frames */
4125 4119 if ((end_frame - current_frame) < UHCI_MAX_ISOC_FRAMES) {
4126 4120 if (current_frame > start_frame) {
4127 4121 if ((current_frame + FRNUM_OFFSET) <
4128 4122 end_frame) {
4129 4123 expired_frames = current_frame +
4130 4124 FRNUM_OFFSET - start_frame;
4131 4125 start_frame = current_frame +
4132 4126 FRNUM_OFFSET;
4133 4127 } else {
4134 4128 rval = USB_INVALID_START_FRAME;
4135 4129 }
4136 4130 }
4137 4131 } else {
4138 4132 rval = USB_INVALID_START_FRAME;
4139 4133 }
4140 4134
4141 4135 } else if (isoc_req->isoc_attributes & USB_ATTRS_ISOC_XFER_ASAP) {
4142 4136 start_frame = pp->pp_frame_num;
4143 4137
4144 4138 if (start_frame == INVALID_FRNUM) {
4145 4139 start_frame = current_frame + FRNUM_OFFSET;
4146 4140 } else if (current_frame > start_frame) {
4147 4141 start_frame = current_frame + FRNUM_OFFSET;
4148 4142 }
4149 4143
4150 4144 end_frame = start_frame + isoc_req->isoc_pkts_count;
4151 4145 isoc_req->isoc_frame_no = start_frame;
4152 4146
4153 4147 }
4154 4148
4155 4149 if (rval != USB_SUCCESS) {
4156 4150
4157 4151 /* Exit the critical */
4158 4152 ddi_exit_critical(ddic);
4159 4153
4160 4154 USB_DPRINTF_L2(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4161 4155 "uhci_insert_isoc_td: Invalid starting frame number");
4162 4156
4163 4157 if (tw->tw_direction == PID_IN) {
4164 4158 uhci_deallocate_periodic_in_resource(uhcip, pp, tw);
4165 4159 }
4166 4160
4167 4161 while (tw->tw_hctd_head) {
4168 4162 uhci_delete_td(uhcip, tw->tw_hctd_head);
4169 4163 }
4170 4164
4171 4165 for (i = 0; i < isoc_xfer_info->num_pools; i++) {
4172 4166 td_pool_ptr = &isoc_xfer_info->td_pools[i];
4173 4167 error = ddi_dma_unbind_handle(td_pool_ptr->dma_handle);
4174 4168 ASSERT(error == DDI_SUCCESS);
4175 4169 ddi_dma_mem_free(&td_pool_ptr->mem_handle);
4176 4170 ddi_dma_free_handle(&td_pool_ptr->dma_handle);
4177 4171 }
4178 4172 kmem_free(isoc_xfer_info->td_pools,
4179 4173 (sizeof (uhci_bulk_isoc_td_pool_t) *
4180 4174 isoc_xfer_info->num_pools));
4181 4175
4182 4176 uhci_deallocate_tw(uhcip, pp, tw);
4183 4177
4184 4178 return (rval);
4185 4179 }
4186 4180
4187 4181 for (i = 0; i < expired_frames; i++) {
4188 4182 isoc_req->isoc_pkt_descr[i].isoc_pkt_status =
4189 4183 USB_CR_NOT_ACCESSED;
4190 4184 isoc_req->isoc_pkt_descr[i].isoc_pkt_actual_length =
4191 4185 isoc_req->isoc_pkt_descr[i].isoc_pkt_length;
4192 4186 uhci_get_isoc_td_by_index(uhcip, isoc_xfer_info, i,
4193 4187 &td_ptr, &td_pool_ptr);
4194 4188 uhci_delete_td(uhcip, td_ptr);
4195 4189 --isoc_xfer_info->num_tds;
4196 4190 }
4197 4191
4198 4192 /*
4199 4193 * Add the TD's to the HC list
4200 4194 */
4201 4195 start_frame = (start_frame & 0x3ff);
4202 4196 for (; i < isoc_req->isoc_pkts_count; i++) {
4203 4197 uhci_get_isoc_td_by_index(uhcip, isoc_xfer_info, i,
4204 4198 &td_ptr, &td_pool_ptr);
4205 4199 if (uhcip->uhci_isoc_q_tailp[start_frame]) {
4206 4200 td_ptr->isoc_prev =
4207 4201 uhcip->uhci_isoc_q_tailp[start_frame];
4208 4202 td_ptr->isoc_next = NULL;
4209 4203 td_ptr->link_ptr =
4210 4204 uhcip->uhci_isoc_q_tailp[start_frame]->link_ptr;
4211 4205 uhcip->uhci_isoc_q_tailp[start_frame]->isoc_next =
4212 4206 td_ptr;
4213 4207 SetTD32(uhcip,
4214 4208 uhcip->uhci_isoc_q_tailp[start_frame]->link_ptr,
4215 4209 ISOCTD_PADDR(td_pool_ptr, td_ptr));
4216 4210 uhcip->uhci_isoc_q_tailp[start_frame] = td_ptr;
4217 4211 } else {
4218 4212 uhcip->uhci_isoc_q_tailp[start_frame] = td_ptr;
4219 4213 td_ptr->isoc_next = NULL;
4220 4214 td_ptr->isoc_prev = NULL;
4221 4215 SetTD32(uhcip, td_ptr->link_ptr,
4222 4216 GetFL32(uhcip,
4223 4217 uhcip->uhci_frame_lst_tablep[start_frame]));
4224 4218 SetFL32(uhcip,
4225 4219 uhcip->uhci_frame_lst_tablep[start_frame],
4226 4220 ISOCTD_PADDR(td_pool_ptr, td_ptr));
4227 4221 }
4228 4222 td_ptr->starting_frame = (uint_t)start_frame;
4229 4223
4230 4224 if (++start_frame == NUM_FRAME_LST_ENTRIES)
4231 4225 start_frame = 0;
4232 4226 }
4233 4227
4234 4228 ddi_exit_critical(ddic);
4235 4229 pp->pp_frame_num = end_frame;
4236 4230
4237 4231 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4238 4232 "uhci_insert_isoc_td: current frame number 0x%llx, pipe frame num"
4239 4233 " 0x%llx", (unsigned long long)current_frame,
4240 4234 (unsigned long long)(pp->pp_frame_num));
4241 4235
4242 4236 return (rval);
4243 4237 }
4244 4238
4245 4239
4246 4240 /*
4247 4241 * uhci_get_isoc_td_by_index:
4248 4242 * Obtain the addresses of the TD pool and the TD at the index.
4249 4243 *
4250 4244 * tdpp - pointer to the address of the TD at the isoc packet index
4251 4245 * td_pool_pp - pointer to the address of the TD pool containing
4252 4246 * the specified TD
4253 4247 */
4254 4248 /* ARGSUSED */
4255 4249 static void
4256 4250 uhci_get_isoc_td_by_index(
4257 4251 uhci_state_t *uhcip,
4258 4252 uhci_bulk_isoc_xfer_t *info,
4259 4253 uint_t index,
4260 4254 uhci_td_t **tdpp,
4261 4255 uhci_bulk_isoc_td_pool_t **td_pool_pp)
4262 4256 {
4263 4257 uint_t i = 0, j = 0;
4264 4258 uhci_td_t *td_ptr;
4265 4259
4266 4260 while (j < info->num_pools) {
4267 4261 if ((i + info->td_pools[j].num_tds) <= index) {
4268 4262 i += info->td_pools[j].num_tds;
4269 4263 j++;
4270 4264 } else {
4271 4265 i = index - i;
4272 4266
4273 4267 break;
4274 4268 }
4275 4269 }
4276 4270
4277 4271 ASSERT(j < info->num_pools);
4278 4272 *td_pool_pp = &info->td_pools[j];
4279 4273 td_ptr = (uhci_td_t *)((*td_pool_pp)->pool_addr);
4280 4274 *tdpp = &td_ptr[i];
4281 4275 }
4282 4276
4283 4277
4284 4278 /*
4285 4279 * uhci_handle_isoc_td:
4286 4280 * Handles the completed isoc tds
4287 4281 */
4288 4282 void
4289 4283 uhci_handle_isoc_td(uhci_state_t *uhcip, uhci_td_t *td)
4290 4284 {
4291 4285 uint_t rval, i;
4292 4286 uint32_t pkt_index = td->isoc_pkt_index;
4293 4287 usb_cr_t cr;
4294 4288 uhci_trans_wrapper_t *tw = td->tw;
4295 4289 usb_isoc_req_t *isoc_req = (usb_isoc_req_t *)tw->tw_isoc_req;
4296 4290 uhci_pipe_private_t *pp = tw->tw_pipe_private;
4297 4291 uhci_bulk_isoc_xfer_t *isoc_xfer_info = &tw->tw_xfer_info;
4298 4292 usba_pipe_handle_data_t *usb_pp;
4299 4293 uhci_bulk_isoc_td_pool_t *td_pool_ptr;
4300 4294
4301 4295 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4302 4296 "uhci_handle_isoc_td: td = 0x%p, pp = 0x%p, tw = 0x%p, req = 0x%p, "
4303 4297 "index = %x", (void *)td, (void *)pp, (void *)tw, (void *)isoc_req,
4304 4298 pkt_index);
4305 4299
4306 4300 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
4307 4301
4308 4302 usb_pp = pp->pp_pipe_handle;
4309 4303
4310 4304 /*
4311 4305 * Check whether there are any errors occurred. If so, update error
4312 4306 * count and return it to the upper.But never return a non zero
4313 4307 * completion reason.
4314 4308 */
4315 4309 cr = USB_CR_OK;
4316 4310 if (GetTD_status(uhcip, td) & TD_STATUS_MASK) {
4317 4311 USB_DPRINTF_L2(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4318 4312 "uhci_handle_isoc_td: Error Occurred: TD Status = %x",
4319 4313 GetTD_status(uhcip, td));
4320 4314 isoc_req->isoc_error_count++;
4321 4315 }
4322 4316
4323 4317 if (isoc_req != NULL) {
4324 4318 isoc_req->isoc_pkt_descr[pkt_index].isoc_pkt_status = cr;
4325 4319 isoc_req->isoc_pkt_descr[pkt_index].isoc_pkt_actual_length =
4326 4320 (GetTD_alen(uhcip, td) == ZERO_LENGTH) ? 0 :
4327 4321 GetTD_alen(uhcip, td) + 1;
4328 4322 }
4329 4323
4330 4324 uhci_delete_isoc_td(uhcip, td);
4331 4325
4332 4326 if (--isoc_xfer_info->num_tds != 0) {
4333 4327 USB_DPRINTF_L3(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4334 4328 "uhci_handle_isoc_td: Number of TDs %d",
4335 4329 isoc_xfer_info->num_tds);
4336 4330
4337 4331 return;
4338 4332 }
4339 4333
4340 4334 tw->tw_claim = UHCI_INTR_HDLR_CLAIMED;
4341 4335 if (tw->tw_direction == PID_IN) {
4342 4336 uhci_sendup_td_message(uhcip, cr, tw);
4343 4337
4344 4338 if ((uhci_handle_isoc_receive(uhcip, pp, tw)) != USB_SUCCESS) {
4345 4339 USB_DPRINTF_L3(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4346 4340 "uhci_handle_isoc_td: Drop message");
4347 4341 }
4348 4342
4349 4343 } else {
4350 4344 /* update kstats only for OUT. sendup_td_msg() does it for IN */
4351 4345 uhci_do_byte_stats(uhcip, tw->tw_length,
4352 4346 usb_pp->p_ep.bmAttributes, usb_pp->p_ep.bEndpointAddress);
4353 4347
4354 4348 uhci_hcdi_callback(uhcip, pp, usb_pp, tw, USB_CR_OK);
4355 4349 }
4356 4350
4357 4351 for (i = 0; i < isoc_xfer_info->num_pools; i++) {
4358 4352 td_pool_ptr = &isoc_xfer_info->td_pools[i];
4359 4353 rval = ddi_dma_unbind_handle(td_pool_ptr->dma_handle);
4360 4354 ASSERT(rval == DDI_SUCCESS);
4361 4355 ddi_dma_mem_free(&td_pool_ptr->mem_handle);
4362 4356 ddi_dma_free_handle(&td_pool_ptr->dma_handle);
4363 4357 }
4364 4358 kmem_free(isoc_xfer_info->td_pools,
4365 4359 (sizeof (uhci_bulk_isoc_td_pool_t) *
4366 4360 isoc_xfer_info->num_pools));
4367 4361 uhci_deallocate_tw(uhcip, pp, tw);
4368 4362 }
4369 4363
4370 4364
4371 4365 /*
4372 4366 * uhci_handle_isoc_receive:
4373 4367 * - Sends the isoc data to the client
4374 4368 * - Inserts another isoc receive request
4375 4369 */
4376 4370 static int
4377 4371 uhci_handle_isoc_receive(
4378 4372 uhci_state_t *uhcip,
4379 4373 uhci_pipe_private_t *pp,
4380 4374 uhci_trans_wrapper_t *tw)
4381 4375 {
4382 4376 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4383 4377 "uhci_handle_isoc_receive: tw = 0x%p", (void *)tw);
4384 4378
4385 4379 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
4386 4380
4387 4381 /*
4388 4382 * -- check for pipe state being polling before
4389 4383 * inserting a new request. Check when is TD
4390 4384 * de-allocation being done? (so we can reuse the same TD)
4391 4385 */
4392 4386 if (uhci_start_isoc_receive_polling(uhcip,
4393 4387 pp->pp_pipe_handle, (usb_isoc_req_t *)tw->tw_curr_xfer_reqp,
4394 4388 0) != USB_SUCCESS) {
4395 4389 USB_DPRINTF_L2(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4396 4390 "uhci_handle_isoc_receive: receive polling failed");
4397 4391
4398 4392 return (USB_FAILURE);
4399 4393 }
4400 4394
4401 4395 return (USB_SUCCESS);
4402 4396 }
4403 4397
4404 4398
4405 4399 /*
4406 4400 * uhci_delete_isoc_td:
4407 4401 * - Delete from the outstanding command queue
4408 4402 * - Delete from the tw queue
4409 4403 * - Delete from the isoc queue
4410 4404 * - Delete from the HOST CONTROLLER list
4411 4405 */
4412 4406 static void
4413 4407 uhci_delete_isoc_td(uhci_state_t *uhcip, uhci_td_t *td)
4414 4408 {
4415 4409 uint32_t starting_frame = td->starting_frame;
4416 4410
4417 4411 if ((td->isoc_next == NULL) && (td->isoc_prev == NULL)) {
4418 4412 SetFL32(uhcip, uhcip->uhci_frame_lst_tablep[starting_frame],
4419 4413 GetTD32(uhcip, td->link_ptr));
4420 4414 uhcip->uhci_isoc_q_tailp[starting_frame] = 0;
4421 4415 } else if (td->isoc_next == NULL) {
4422 4416 td->isoc_prev->link_ptr = td->link_ptr;
4423 4417 td->isoc_prev->isoc_next = NULL;
4424 4418 uhcip->uhci_isoc_q_tailp[starting_frame] = td->isoc_prev;
4425 4419 } else if (td->isoc_prev == NULL) {
4426 4420 td->isoc_next->isoc_prev = NULL;
4427 4421 SetFL32(uhcip, uhcip->uhci_frame_lst_tablep[starting_frame],
4428 4422 GetTD32(uhcip, td->link_ptr));
4429 4423 } else {
4430 4424 td->isoc_prev->isoc_next = td->isoc_next;
4431 4425 td->isoc_next->isoc_prev = td->isoc_prev;
4432 4426 td->isoc_prev->link_ptr = td->link_ptr;
4433 4427 }
4434 4428
4435 4429 uhci_delete_td(uhcip, td);
4436 4430 }
4437 4431
4438 4432
4439 4433 /*
4440 4434 * uhci_send_isoc_receive
4441 4435 * - Allocates usb_isoc_request
4442 4436 * - Updates the isoc request
4443 4437 * - Inserts the isoc td's into the HC processing list.
4444 4438 */
4445 4439 int
4446 4440 uhci_start_isoc_receive_polling(
4447 4441 uhci_state_t *uhcip,
4448 4442 usba_pipe_handle_data_t *ph,
4449 4443 usb_isoc_req_t *isoc_req,
4450 4444 usb_flags_t usb_flags)
4451 4445 {
4452 4446 int ii, error;
4453 4447 size_t max_isoc_xfer_size, length, isoc_pkts_length;
4454 4448 ushort_t isoc_pkt_count;
4455 4449 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private;
4456 4450 usb_isoc_pkt_descr_t *isoc_pkt_descr;
4457 4451
4458 4452 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4459 4453 "uhci_start_isoc_receive_polling: usb_flags = %x", usb_flags);
4460 4454
4461 4455 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
4462 4456
4463 4457 max_isoc_xfer_size = ph->p_ep.wMaxPacketSize * UHCI_MAX_ISOC_PKTS;
4464 4458
4465 4459 if (isoc_req) {
4466 4460 isoc_pkt_descr = isoc_req->isoc_pkt_descr;
4467 4461 isoc_pkt_count = isoc_req->isoc_pkts_count;
4468 4462 isoc_pkts_length = isoc_req->isoc_pkts_length;
4469 4463 } else {
4470 4464 isoc_pkt_descr = ((usb_isoc_req_t *)
4471 4465 pp->pp_client_periodic_in_reqp)->isoc_pkt_descr;
4472 4466 isoc_pkt_count = ((usb_isoc_req_t *)
4473 4467 pp->pp_client_periodic_in_reqp)->isoc_pkts_count;
4474 4468 isoc_pkts_length = ((usb_isoc_req_t *)
4475 4469 pp->pp_client_periodic_in_reqp)->isoc_pkts_length;
4476 4470 }
4477 4471
4478 4472 for (ii = 0, length = 0; ii < isoc_pkt_count; ii++) {
4479 4473 length += isoc_pkt_descr->isoc_pkt_length;
4480 4474 isoc_pkt_descr++;
4481 4475 }
4482 4476
4483 4477 if ((isoc_pkts_length) && (isoc_pkts_length != length)) {
4484 4478
4485 4479 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
4486 4480 "uhci_start_isoc_receive_polling: isoc_pkts_length 0x%lx "
4487 4481 "is not equal to the sum of all pkt lengths 0x%lx in "
4488 4482 "an isoc request", isoc_pkts_length, length);
4489 4483
4490 4484 return (USB_FAILURE);
4491 4485 }
4492 4486
4493 4487 /* Check the size of isochronous request */
4494 4488 if (length > max_isoc_xfer_size) {
4495 4489 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4496 4490 "uhci_start_isoc_receive_polling: "
4497 4491 "Max isoc request size = %lx, Given isoc req size = %lx",
4498 4492 max_isoc_xfer_size, length);
4499 4493
4500 4494 return (USB_FAILURE);
4501 4495 }
4502 4496
4503 4497 /* Add the TD into the Host Controller's isoc list */
4504 4498 error = uhci_insert_isoc_td(uhcip, ph, isoc_req, length, usb_flags);
4505 4499
4506 4500 return (error);
4507 4501 }
4508 4502
4509 4503
4510 4504 /*
4511 4505 * uhci_remove_isoc_tds_tws
4512 4506 * This routine scans the pipe and removes all the td's
4513 4507 * and transfer wrappers and deallocates the memory
4514 4508 * associated with those td's and tw's.
4515 4509 */
4516 4510 void
4517 4511 uhci_remove_isoc_tds_tws(uhci_state_t *uhcip, uhci_pipe_private_t *pp)
4518 4512 {
4519 4513 uint_t rval, i;
4520 4514 uhci_td_t *tmp_td, *td_head;
4521 4515 usb_isoc_req_t *isoc_req;
4522 4516 uhci_trans_wrapper_t *tmp_tw, *tw_head;
4523 4517 uhci_bulk_isoc_xfer_t *isoc_xfer_info;
4524 4518 uhci_bulk_isoc_td_pool_t *td_pool_ptr;
4525 4519
4526 4520 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl,
4527 4521 "uhci_remove_isoc_tds_tws: pp = %p", (void *)pp);
4528 4522
4529 4523 tw_head = pp->pp_tw_head;
4530 4524 while (tw_head) {
4531 4525 tmp_tw = tw_head;
4532 4526 tw_head = tw_head->tw_next;
4533 4527 td_head = tmp_tw->tw_hctd_head;
4534 4528 if (tmp_tw->tw_direction == PID_IN) {
4535 4529 uhci_deallocate_periodic_in_resource(uhcip, pp,
4536 4530 tmp_tw);
4537 4531 } else if (tmp_tw->tw_direction == PID_OUT) {
4538 4532 uhci_hcdi_callback(uhcip, pp, pp->pp_pipe_handle,
4539 4533 tmp_tw, USB_CR_FLUSHED);
4540 4534 }
4541 4535
4542 4536 while (td_head) {
4543 4537 tmp_td = td_head;
4544 4538 td_head = td_head->tw_td_next;
4545 4539 uhci_delete_isoc_td(uhcip, tmp_td);
4546 4540 }
4547 4541
4548 4542 isoc_req = (usb_isoc_req_t *)tmp_tw->tw_isoc_req;
4549 4543 if (isoc_req) {
4550 4544 usb_free_isoc_req(isoc_req);
4551 4545 }
4552 4546
4553 4547 ASSERT(tmp_tw->tw_hctd_head == NULL);
4554 4548
4555 4549 if (tmp_tw->tw_xfer_info.td_pools) {
4556 4550 isoc_xfer_info =
4557 4551 (uhci_bulk_isoc_xfer_t *)&tmp_tw->tw_xfer_info;
4558 4552 for (i = 0; i < isoc_xfer_info->num_pools; i++) {
4559 4553 td_pool_ptr = &isoc_xfer_info->td_pools[i];
4560 4554 rval = ddi_dma_unbind_handle(
4561 4555 td_pool_ptr->dma_handle);
4562 4556 ASSERT(rval == DDI_SUCCESS);
4563 4557 ddi_dma_mem_free(&td_pool_ptr->mem_handle);
4564 4558 ddi_dma_free_handle(&td_pool_ptr->dma_handle);
4565 4559 }
4566 4560 kmem_free(isoc_xfer_info->td_pools,
4567 4561 (sizeof (uhci_bulk_isoc_td_pool_t) *
4568 4562 isoc_xfer_info->num_pools));
4569 4563 }
4570 4564
4571 4565 uhci_deallocate_tw(uhcip, pp, tmp_tw);
4572 4566 }
4573 4567 }
4574 4568
4575 4569
4576 4570 /*
4577 4571 * uhci_isoc_update_sw_frame_number()
4578 4572 * to avoid code duplication, call uhci_get_sw_frame_number()
4579 4573 */
4580 4574 void
4581 4575 uhci_isoc_update_sw_frame_number(uhci_state_t *uhcip)
4582 4576 {
4583 4577 (void) uhci_get_sw_frame_number(uhcip);
4584 4578 }
4585 4579
4586 4580
4587 4581 /*
4588 4582 * uhci_get_sw_frame_number:
4589 4583 * Hold the uhci_int_mutex before calling this routine.
4590 4584 */
4591 4585 uint64_t
4592 4586 uhci_get_sw_frame_number(uhci_state_t *uhcip)
4593 4587 {
4594 4588 uint64_t sw_frnum, hw_frnum, current_frnum;
4595 4589
4596 4590 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
4597 4591
4598 4592 sw_frnum = uhcip->uhci_sw_frnum;
4599 4593 hw_frnum = Get_OpReg16(FRNUM);
4600 4594
4601 4595 /*
4602 4596 * Check bit 10 in the software counter and hardware frame counter.
4603 4597 * If both are same, then don't increment the software frame counter
4604 4598 * (Bit 10 of hw frame counter toggle for every 1024 frames)
4605 4599 * The lower 11 bits of software counter contains the hardware frame
4606 4600 * counter value. The MSB (bit 10) of software counter is incremented
4607 4601 * for every 1024 frames either here or in get frame number routine.
4608 4602 */
4609 4603 if ((sw_frnum & UHCI_BIT_10_MASK) == (hw_frnum & UHCI_BIT_10_MASK)) {
4610 4604 /* The MSB of hw counter did not toggle */
4611 4605 current_frnum = ((sw_frnum & (SW_FRNUM_MASK)) | hw_frnum);
4612 4606 } else {
4613 4607 /*
4614 4608 * The hw counter wrapped around. And the interrupt handler
4615 4609 * did not get a chance to update the sw frame counter.
4616 4610 * So, update the sw frame counter and return correct frame no.
4617 4611 */
4618 4612 sw_frnum >>= UHCI_SIZE_OF_HW_FRNUM - 1;
4619 4613 current_frnum =
4620 4614 ((++sw_frnum << (UHCI_SIZE_OF_HW_FRNUM - 1)) | hw_frnum);
4621 4615 }
4622 4616 uhcip->uhci_sw_frnum = current_frnum;
4623 4617
4624 4618 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
4625 4619 "uhci_get_sw_frame_number: sw=%lld hd=%lld",
4626 4620 (unsigned long long)(uhcip->uhci_sw_frnum),
4627 4621 (unsigned long long)hw_frnum);
4628 4622
4629 4623 return (current_frnum);
4630 4624 }
4631 4625
4632 4626
4633 4627 /*
4634 4628 * uhci_cmd_timeout_hdlr:
4635 4629 * This routine will get called for every second. It checks for
4636 4630 * timed out control commands/bulk commands. Timeout any commands
4637 4631 * that exceeds the time out period specified by the pipe policy.
4638 4632 */
4639 4633 void
4640 4634 uhci_cmd_timeout_hdlr(void *arg)
4641 4635 {
4642 4636 uint_t flag = B_FALSE;
4643 4637 uhci_td_t *head, *tmp_td;
4644 4638 uhci_state_t *uhcip = (uhci_state_t *)arg;
4645 4639 uhci_pipe_private_t *pp;
4646 4640
4647 4641 /*
4648 4642 * Check whether any of the control xfers are timed out.
4649 4643 * If so, complete those commands with time out as reason.
4650 4644 */
4651 4645 mutex_enter(&uhcip->uhci_int_mutex);
4652 4646 head = uhcip->uhci_outst_tds_head;
4653 4647
4654 4648 while (head) {
4655 4649 /*
4656 4650 * If timeout out is zero, then dont timeout command.
4657 4651 */
4658 4652 if (head->tw->tw_timeout_cnt == 0) {
4659 4653 head = head->outst_td_next;
4660 4654 continue;
4661 4655 }
4662 4656
4663 4657 if (!(head->tw->tw_flags & TW_TIMEOUT_FLAG)) {
4664 4658 head->tw->tw_flags |= TW_TIMEOUT_FLAG;
4665 4659 --head->tw->tw_timeout_cnt;
4666 4660 }
4667 4661
4668 4662 /* only do it for bulk and control TDs */
4669 4663 if ((head->tw->tw_timeout_cnt == 0) &&
4670 4664 (head->tw->tw_handle_td != uhci_handle_isoc_td)) {
4671 4665
4672 4666 USB_DPRINTF_L3(PRINT_MASK_ATTA, uhcip->uhci_log_hdl,
4673 4667 "Command timed out: td = %p", (void *)head);
4674 4668
4675 4669 head->tw->tw_claim = UHCI_TIMEOUT_HDLR_CLAIMED;
4676 4670
4677 4671 /*
4678 4672 * Check finally whether the command completed
4679 4673 */
4680 4674 if (GetTD_status(uhcip, head) & UHCI_TD_ACTIVE) {
4681 4675 SetTD32(uhcip, head->link_ptr,
4682 4676 GetTD32(uhcip, head->link_ptr) |
4683 4677 HC_END_OF_LIST);
4684 4678 pp = head->tw->tw_pipe_private;
4685 4679 SetQH32(uhcip, pp->pp_qh->element_ptr,
4686 4680 GetQH32(uhcip, pp->pp_qh->element_ptr) |
4687 4681 HC_END_OF_LIST);
4688 4682 }
4689 4683
4690 4684 flag = B_TRUE;
4691 4685 }
4692 4686
4693 4687 head = head->outst_td_next;
4694 4688 }
4695 4689
4696 4690 if (flag) {
4697 4691 (void) uhci_wait_for_sof(uhcip);
4698 4692 }
4699 4693
4700 4694 head = uhcip->uhci_outst_tds_head;
4701 4695 while (head) {
4702 4696 if (head->tw->tw_flags & TW_TIMEOUT_FLAG) {
4703 4697 head->tw->tw_flags &= ~TW_TIMEOUT_FLAG;
4704 4698 }
4705 4699 if (head->tw->tw_claim == UHCI_TIMEOUT_HDLR_CLAIMED) {
4706 4700 head->tw->tw_claim = UHCI_NOT_CLAIMED;
4707 4701 tmp_td = head->tw->tw_hctd_head;
4708 4702 while (tmp_td) {
4709 4703 SetTD_status(uhcip, tmp_td,
4710 4704 UHCI_TD_CRC_TIMEOUT);
4711 4705 tmp_td = tmp_td->tw_td_next;
4712 4706 }
4713 4707 }
4714 4708 head = head->outst_td_next;
4715 4709 }
4716 4710
4717 4711 /*
4718 4712 * Process the td which was completed before shifting from normal
4719 4713 * mode to polled mode
4720 4714 */
4721 4715 if (uhcip->uhci_polled_flag == UHCI_POLLED_FLAG_TRUE) {
4722 4716 uhci_process_submitted_td_queue(uhcip);
4723 4717 uhcip->uhci_polled_flag = UHCI_POLLED_FLAG_FALSE;
4724 4718 } else if (flag) {
4725 4719 /* Process the completed/timed out commands */
4726 4720 uhci_process_submitted_td_queue(uhcip);
4727 4721 }
4728 4722
4729 4723 /* Re-register the control/bulk/intr commands' timeout handler */
4730 4724 if (uhcip->uhci_cmd_timeout_id) {
4731 4725 uhcip->uhci_cmd_timeout_id = timeout(uhci_cmd_timeout_hdlr,
4732 4726 (void *)uhcip, UHCI_ONE_SECOND);
4733 4727 }
4734 4728
4735 4729 mutex_exit(&uhcip->uhci_int_mutex);
4736 4730 }
4737 4731
4738 4732
4739 4733 /*
4740 4734 * uhci_wait_for_sof:
4741 4735 * Wait for the start of the next frame (implying any changes made in the
4742 4736 * lattice have now taken effect).
4743 4737 * To be sure this is the case, we wait for the completion of the current
4744 4738 * frame (which might have already been pending), then another complete
4745 4739 * frame to ensure everything has taken effect.
4746 4740 */
4747 4741 int
4748 4742 uhci_wait_for_sof(uhci_state_t *uhcip)
4749 4743 {
4750 4744 int n, error;
4751 4745 ushort_t cmd_reg;
4752 4746 usb_frame_number_t before_frame_number, after_frame_number;
4753 4747 clock_t rval;
4754 4748 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl,
4755 4749 "uhci_wait_for_sof: uhcip = %p", (void *)uhcip);
4756 4750
4757 4751 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
4758 4752
4759 4753 error = uhci_state_is_operational(uhcip);
4760 4754
4761 4755 if (error != USB_SUCCESS) {
4762 4756
4763 4757 return (error);
4764 4758 }
4765 4759
4766 4760 before_frame_number = uhci_get_sw_frame_number(uhcip);
4767 4761 for (n = 0; n < MAX_SOF_WAIT_COUNT; n++) {
4768 4762 SetTD_ioc(uhcip, uhcip->uhci_sof_td, 1);
4769 4763 uhcip->uhci_cv_signal = B_TRUE;
4770 4764
4771 4765 rval = cv_reltimedwait(&uhcip->uhci_cv_SOF,
4772 4766 &uhcip->uhci_int_mutex, UHCI_ONE_SECOND, TR_CLOCK_TICK);
4773 4767
4774 4768 after_frame_number = uhci_get_sw_frame_number(uhcip);
4775 4769 if ((rval == -1) &&
4776 4770 (after_frame_number <= before_frame_number)) {
4777 4771 cmd_reg = Get_OpReg16(USBCMD);
4778 4772 Set_OpReg16(USBCMD, (cmd_reg | USBCMD_REG_HC_RUN));
4779 4773 Set_OpReg16(USBINTR, ENABLE_ALL_INTRS);
4780 4774 after_frame_number = uhci_get_sw_frame_number(uhcip);
4781 4775 }
4782 4776 before_frame_number = after_frame_number;
4783 4777 }
4784 4778
4785 4779 SetTD_ioc(uhcip, uhcip->uhci_sof_td, 0);
4786 4780
4787 4781 return (uhcip->uhci_cv_signal ? USB_FAILURE : USB_SUCCESS);
4788 4782
4789 4783 }
4790 4784
4791 4785 /*
4792 4786 * uhci_allocate_periodic_in_resource:
4793 4787 * Allocate interrupt/isochronous request structure for the
4794 4788 * interrupt/isochronous IN transfer.
4795 4789 */
4796 4790 int
4797 4791 uhci_allocate_periodic_in_resource(
4798 4792 uhci_state_t *uhcip,
4799 4793 uhci_pipe_private_t *pp,
4800 4794 uhci_trans_wrapper_t *tw,
4801 4795 usb_flags_t flags)
4802 4796 {
4803 4797 size_t length = 0;
4804 4798 usb_opaque_t client_periodic_in_reqp;
4805 4799 usb_intr_req_t *cur_intr_req;
4806 4800 usb_isoc_req_t *curr_isoc_reqp;
4807 4801 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle;
4808 4802
4809 4803 USB_DPRINTF_L4(PRINT_MASK_HCDI, uhcip->uhci_log_hdl,
4810 4804 "uhci_allocate_periodic_in_resource:\n\t"
4811 4805 "ph = 0x%p, pp = 0x%p, tw = 0x%p, flags = 0x%x",
4812 4806 (void *)ph, (void *)pp, (void *)tw, flags);
4813 4807
4814 4808 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
4815 4809
4816 4810 /* Check the current periodic in request pointer */
4817 4811 if (tw->tw_curr_xfer_reqp) {
4818 4812 USB_DPRINTF_L2(PRINT_MASK_HCDI, uhcip->uhci_log_hdl,
4819 4813 "uhci_allocate_periodic_in_resource: Interrupt "
4820 4814 "request structure already exists: "
4821 4815 "allocation failed");
4822 4816
4823 4817 return (USB_SUCCESS);
4824 4818 }
4825 4819
4826 4820 /* Get the client periodic in request pointer */
4827 4821 client_periodic_in_reqp = pp->pp_client_periodic_in_reqp;
4828 4822
4829 4823 /*
4830 4824 * If it a periodic IN request and periodic request is NULL,
4831 4825 * allocate corresponding usb periodic IN request for the
4832 4826 * current periodic polling request and copy the information
4833 4827 * from the saved periodic request structure.
4834 4828 */
4835 4829 if (UHCI_XFER_TYPE(&ph->p_ep) == USB_EP_ATTR_INTR) {
4836 4830 /* Get the interrupt transfer length */
4837 4831 length = ((usb_intr_req_t *)client_periodic_in_reqp)->
4838 4832 intr_len;
4839 4833
4840 4834 cur_intr_req = usba_hcdi_dup_intr_req(ph->p_dip,
4841 4835 (usb_intr_req_t *)client_periodic_in_reqp, length, flags);
4842 4836 if (cur_intr_req == NULL) {
4843 4837 USB_DPRINTF_L2(PRINT_MASK_HCDI, uhcip->uhci_log_hdl,
4844 4838 "uhci_allocate_periodic_in_resource: Interrupt "
4845 4839 "request structure allocation failed");
4846 4840
4847 4841 return (USB_NO_RESOURCES);
4848 4842 }
4849 4843
4850 4844 /* Check and save the timeout value */
4851 4845 tw->tw_timeout_cnt = (cur_intr_req->intr_attributes &
4852 4846 USB_ATTRS_ONE_XFER) ? cur_intr_req->intr_timeout: 0;
4853 4847 tw->tw_curr_xfer_reqp = (usb_opaque_t)cur_intr_req;
4854 4848 tw->tw_length = cur_intr_req->intr_len;
4855 4849 } else {
4856 4850 ASSERT(client_periodic_in_reqp != NULL);
4857 4851
4858 4852 if ((curr_isoc_reqp = usba_hcdi_dup_isoc_req(ph->p_dip,
4859 4853 (usb_isoc_req_t *)client_periodic_in_reqp, flags)) ==
4860 4854 NULL) {
4861 4855 USB_DPRINTF_L2(PRINT_MASK_HCDI, uhcip->uhci_log_hdl,
4862 4856 "uhci_allocate_periodic_in_resource: Isochronous "
4863 4857 "request structure allocation failed");
4864 4858
4865 4859 return (USB_NO_RESOURCES);
4866 4860 }
4867 4861
4868 4862 /*
4869 4863 * Save the client's isochronous request pointer and
4870 4864 * length of isochronous transfer in transfer wrapper.
4871 4865 * The dup'ed request is saved in pp_client_periodic_in_reqp
4872 4866 */
4873 4867 tw->tw_curr_xfer_reqp =
4874 4868 (usb_opaque_t)pp->pp_client_periodic_in_reqp;
4875 4869 pp->pp_client_periodic_in_reqp = (usb_opaque_t)curr_isoc_reqp;
4876 4870 }
4877 4871
4878 4872 mutex_enter(&ph->p_mutex);
4879 4873 ph->p_req_count++;
4880 4874 mutex_exit(&ph->p_mutex);
4881 4875
4882 4876 return (USB_SUCCESS);
4883 4877 }
4884 4878
4885 4879
4886 4880 /*
4887 4881 * uhci_deallocate_periodic_in_resource:
4888 4882 * Deallocate interrupt/isochronous request structure for the
4889 4883 * interrupt/isochronous IN transfer.
4890 4884 */
4891 4885 void
4892 4886 uhci_deallocate_periodic_in_resource(
4893 4887 uhci_state_t *uhcip,
4894 4888 uhci_pipe_private_t *pp,
4895 4889 uhci_trans_wrapper_t *tw)
4896 4890 {
4897 4891 usb_opaque_t curr_xfer_reqp;
4898 4892 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle;
4899 4893
4900 4894 USB_DPRINTF_L4(PRINT_MASK_HCDI, uhcip->uhci_log_hdl,
4901 4895 "uhci_deallocate_periodic_in_resource: "
4902 4896 "pp = 0x%p tw = 0x%p", (void *)pp, (void *)tw);
4903 4897
4904 4898 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
4905 4899
4906 4900 curr_xfer_reqp = tw->tw_curr_xfer_reqp;
4907 4901 if (curr_xfer_reqp) {
4908 4902 /*
4909 4903 * Reset periodic in request usb isoch
4910 4904 * packet request pointers to null.
4911 4905 */
4912 4906 tw->tw_curr_xfer_reqp = NULL;
4913 4907 tw->tw_isoc_req = NULL;
4914 4908
4915 4909 mutex_enter(&ph->p_mutex);
4916 4910 ph->p_req_count--;
4917 4911 mutex_exit(&ph->p_mutex);
4918 4912
4919 4913 /*
4920 4914 * Free pre-allocated interrupt or isochronous requests.
4921 4915 */
4922 4916 switch (UHCI_XFER_TYPE(&ph->p_ep)) {
4923 4917 case USB_EP_ATTR_INTR:
4924 4918 usb_free_intr_req((usb_intr_req_t *)curr_xfer_reqp);
4925 4919 break;
4926 4920 case USB_EP_ATTR_ISOCH:
4927 4921 usb_free_isoc_req((usb_isoc_req_t *)curr_xfer_reqp);
4928 4922 break;
4929 4923 }
4930 4924 }
4931 4925 }
4932 4926
4933 4927
4934 4928 /*
4935 4929 * uhci_hcdi_callback()
4936 4930 * convenience wrapper around usba_hcdi_callback()
4937 4931 */
4938 4932 void
4939 4933 uhci_hcdi_callback(uhci_state_t *uhcip, uhci_pipe_private_t *pp,
4940 4934 usba_pipe_handle_data_t *ph, uhci_trans_wrapper_t *tw, usb_cr_t cr)
4941 4935 {
4942 4936 usb_opaque_t curr_xfer_reqp;
4943 4937
4944 4938 USB_DPRINTF_L4(PRINT_MASK_HCDI, uhcip->uhci_log_hdl,
4945 4939 "uhci_hcdi_callback: ph = 0x%p, tw = 0x%p, cr = 0x%x",
4946 4940 (void *)ph, (void *)tw, cr);
4947 4941
4948 4942 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
4949 4943
4950 4944 if (tw && tw->tw_curr_xfer_reqp) {
4951 4945 curr_xfer_reqp = tw->tw_curr_xfer_reqp;
4952 4946 tw->tw_curr_xfer_reqp = NULL;
4953 4947 tw->tw_isoc_req = NULL;
4954 4948 } else {
4955 4949 ASSERT(pp->pp_client_periodic_in_reqp != NULL);
4956 4950
4957 4951 curr_xfer_reqp = pp->pp_client_periodic_in_reqp;
4958 4952 pp->pp_client_periodic_in_reqp = NULL;
4959 4953 }
4960 4954
4961 4955 ASSERT(curr_xfer_reqp != NULL);
4962 4956
4963 4957 mutex_exit(&uhcip->uhci_int_mutex);
4964 4958 usba_hcdi_cb(ph, curr_xfer_reqp, cr);
4965 4959 mutex_enter(&uhcip->uhci_int_mutex);
4966 4960 }
4967 4961
4968 4962
4969 4963 /*
4970 4964 * uhci_state_is_operational:
4971 4965 *
4972 4966 * Check the Host controller state and return proper values.
4973 4967 */
4974 4968 int
4975 4969 uhci_state_is_operational(uhci_state_t *uhcip)
4976 4970 {
4977 4971 int val;
4978 4972
4979 4973 ASSERT(mutex_owned(&uhcip->uhci_int_mutex));
4980 4974
4981 4975 switch (uhcip->uhci_hc_soft_state) {
4982 4976 case UHCI_CTLR_INIT_STATE:
4983 4977 case UHCI_CTLR_SUSPEND_STATE:
4984 4978 val = USB_FAILURE;
4985 4979 break;
4986 4980 case UHCI_CTLR_OPERATIONAL_STATE:
4987 4981 val = USB_SUCCESS;
4988 4982 break;
4989 4983 case UHCI_CTLR_ERROR_STATE:
4990 4984 val = USB_HC_HARDWARE_ERROR;
4991 4985 break;
4992 4986 default:
4993 4987 val = USB_FAILURE;
4994 4988 break;
4995 4989 }
4996 4990
4997 4991 return (val);
4998 4992 }
4999 4993
5000 4994
5001 4995 #ifdef DEBUG
5002 4996 static void
5003 4997 uhci_print_td(uhci_state_t *uhcip, uhci_td_t *td)
5004 4998 {
5005 4999 uint_t *ptr = (uint_t *)td;
5006 5000
5007 5001 #ifndef lint
5008 5002 _NOTE(NO_COMPETING_THREADS_NOW);
5009 5003 #endif
5010 5004 USB_DPRINTF_L3(PRINT_MASK_DUMPING, uhcip->uhci_log_hdl,
5011 5005 "\tDWORD 1 0x%x\t DWORD 2 0x%x", ptr[0], ptr[1]);
5012 5006 USB_DPRINTF_L3(PRINT_MASK_DUMPING, uhcip->uhci_log_hdl,
5013 5007 "\tDWORD 3 0x%x\t DWORD 4 0x%x", ptr[2], ptr[3]);
5014 5008 USB_DPRINTF_L3(PRINT_MASK_DUMPING, uhcip->uhci_log_hdl,
5015 5009 "\tBytes xfered = %d", td->tw->tw_bytes_xfered);
5016 5010 USB_DPRINTF_L3(PRINT_MASK_DUMPING, uhcip->uhci_log_hdl,
5017 5011 "\tBytes Pending = %d", td->tw->tw_bytes_pending);
5018 5012 USB_DPRINTF_L3(PRINT_MASK_DUMPING, uhcip->uhci_log_hdl,
5019 5013 "Queue Head Details:");
5020 5014 uhci_print_qh(uhcip, td->tw->tw_pipe_private->pp_qh);
5021 5015
5022 5016 #ifndef lint
5023 5017 _NOTE(COMPETING_THREADS_NOW);
5024 5018 #endif
5025 5019 }
5026 5020
5027 5021
5028 5022 static void
5029 5023 uhci_print_qh(uhci_state_t *uhcip, queue_head_t *qh)
5030 5024 {
5031 5025 uint_t *ptr = (uint_t *)qh;
5032 5026
5033 5027 USB_DPRINTF_L3(PRINT_MASK_DUMPING, uhcip->uhci_log_hdl,
5034 5028 "\tLink Ptr = %x Element Ptr = %x", ptr[0], ptr[1]);
5035 5029 }
5036 5030 #endif
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