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4663 apic_cr8pri complicates pcplusmp
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--- old/usr/src/uts/i86pc/io/pcplusmp/apic.c
+++ new/usr/src/uts/i86pc/io/pcplusmp/apic.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
31 31 */
32 32
33 33 /*
34 34 * To understand how the pcplusmp module interacts with the interrupt subsystem
35 35 * read the theory statement in uts/i86pc/os/intr.c.
36 36 */
37 37
38 38 /*
39 39 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
40 40 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
41 41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
42 42 * PSMI 1.5 extensions are supported in Solaris Nevada.
43 43 * PSMI 1.6 extensions are supported in Solaris Nevada.
44 44 * PSMI 1.7 extensions are supported in Solaris Nevada.
45 45 */
46 46 #define PSMI_1_7
47 47
48 48 #include <sys/processor.h>
49 49 #include <sys/time.h>
50 50 #include <sys/psm.h>
51 51 #include <sys/smp_impldefs.h>
52 52 #include <sys/cram.h>
53 53 #include <sys/acpi/acpi.h>
54 54 #include <sys/acpica.h>
55 55 #include <sys/psm_common.h>
56 56 #include <sys/apic.h>
57 57 #include <sys/pit.h>
58 58 #include <sys/ddi.h>
59 59 #include <sys/sunddi.h>
60 60 #include <sys/ddi_impldefs.h>
61 61 #include <sys/pci.h>
62 62 #include <sys/promif.h>
63 63 #include <sys/x86_archext.h>
64 64 #include <sys/cpc_impl.h>
65 65 #include <sys/uadmin.h>
66 66 #include <sys/panic.h>
67 67 #include <sys/debug.h>
68 68 #include <sys/archsystm.h>
69 69 #include <sys/trap.h>
70 70 #include <sys/machsystm.h>
71 71 #include <sys/sysmacros.h>
72 72 #include <sys/cpuvar.h>
73 73 #include <sys/rm_platter.h>
74 74 #include <sys/privregs.h>
75 75 #include <sys/note.h>
76 76 #include <sys/pci_intr_lib.h>
77 77 #include <sys/spl.h>
78 78 #include <sys/clock.h>
79 79 #include <sys/cyclic.h>
80 80 #include <sys/dditypes.h>
81 81 #include <sys/sunddi.h>
82 82 #include <sys/x_call.h>
83 83 #include <sys/reboot.h>
84 84 #include <sys/hpet.h>
85 85 #include <sys/apic_common.h>
86 86 #include <sys/apic_timer.h>
87 87
88 88 /*
89 89 * Local Function Prototypes
90 90 */
91 91 static void apic_init_intr(void);
92 92
93 93 /*
94 94 * standard MP entries
95 95 */
96 96 static int apic_probe(void);
97 97 static int apic_getclkirq(int ipl);
98 98 static void apic_init(void);
99 99 static void apic_picinit(void);
100 100 static int apic_post_cpu_start(void);
101 101 static int apic_intr_enter(int ipl, int *vect);
102 102 static void apic_setspl(int ipl);
103 103 static void x2apic_setspl(int ipl);
104 104 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
105 105 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
106 106 static int apic_disable_intr(processorid_t cpun);
107 107 static void apic_enable_intr(processorid_t cpun);
108 108 static int apic_get_ipivect(int ipl, int type);
109 109 static void apic_post_cyclic_setup(void *arg);
110 110
111 111 /*
112 112 * The following vector assignments influence the value of ipltopri and
113 113 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
114 114 * idle to 0 and IPL 0 to 0xf to differentiate idle in case
115 115 * we care to do so in future. Note some IPLs which are rarely used
116 116 * will share the vector ranges and heavily used IPLs (5 and 6) have
117 117 * a wide range.
118 118 *
119 119 * This array is used to initialize apic_ipls[] (in apic_init()).
120 120 *
121 121 * IPL Vector range. as passed to intr_enter
122 122 * 0 none.
123 123 * 1,2,3 0x20-0x2f 0x0-0xf
124 124 * 4 0x30-0x3f 0x10-0x1f
125 125 * 5 0x40-0x5f 0x20-0x3f
126 126 * 6 0x60-0x7f 0x40-0x5f
127 127 * 7,8,9 0x80-0x8f 0x60-0x6f
128 128 * 10 0x90-0x9f 0x70-0x7f
129 129 * 11 0xa0-0xaf 0x80-0x8f
130 130 * ... ...
131 131 * 15 0xe0-0xef 0xc0-0xcf
132 132 * 15 0xf0-0xff 0xd0-0xdf
133 133 */
134 134 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
135 135 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
136 136 };
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137 137 /*
138 138 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
139 139 * NOTE that this is vector as passed into intr_enter which is
140 140 * programmed vector - 0x20 (APIC_BASE_VECT)
141 141 */
142 142
143 143 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
144 144 /* The taskpri to be programmed into apic to mask given ipl */
145 145
146 146 #if defined(__amd64)
147 -uchar_t apic_cr8pri[MAXIPL + 1]; /* unix ipl to cr8 pri */
147 +static unsigned char dummy_cpu_pri[MAXIPL + 1];
148 148 #endif
149 149
150 150 /*
151 151 * Correlation of the hardware vector to the IPL in use, initialized
152 152 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
153 153 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
154 154 * connected to errata-stricken IOAPICs
155 155 */
156 156 uchar_t apic_ipls[APIC_AVAIL_VECTOR];
157 157
158 158 /*
159 159 * Patchable global variables.
160 160 */
161 161 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
162 162 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
163 163
164 164 /*
165 165 * Local static data
166 166 */
167 167 static struct psm_ops apic_ops = {
168 168 apic_probe,
169 169
170 170 apic_init,
171 171 apic_picinit,
172 172 apic_intr_enter,
173 173 apic_intr_exit,
174 174 apic_setspl,
175 175 apic_addspl,
176 176 apic_delspl,
177 177 apic_disable_intr,
178 178 apic_enable_intr,
179 179 (int (*)(int))NULL, /* psm_softlvl_to_irq */
180 180 (void (*)(int))NULL, /* psm_set_softintr */
181 181
182 182 apic_set_idlecpu,
183 183 apic_unset_idlecpu,
184 184
185 185 apic_clkinit,
186 186 apic_getclkirq,
187 187 (void (*)(void))NULL, /* psm_hrtimeinit */
188 188 apic_gethrtime,
189 189
190 190 apic_get_next_processorid,
191 191 apic_cpu_start,
192 192 apic_post_cpu_start,
193 193 apic_shutdown,
194 194 apic_get_ipivect,
195 195 apic_send_ipi,
196 196
197 197 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
198 198 (void (*)(int, char *))NULL, /* psm_notify_error */
199 199 (void (*)(int))NULL, /* psm_notify_func */
200 200 apic_timer_reprogram,
201 201 apic_timer_enable,
202 202 apic_timer_disable,
203 203 apic_post_cyclic_setup,
204 204 apic_preshutdown,
205 205 apic_intr_ops, /* Advanced DDI Interrupt framework */
206 206 apic_state, /* save, restore apic state for S3 */
207 207 apic_cpu_ops, /* CPU control interface. */
208 208 };
209 209
210 210 struct psm_ops *psmops = &apic_ops;
211 211
212 212 static struct psm_info apic_psm_info = {
213 213 PSM_INFO_VER01_7, /* version */
214 214 PSM_OWN_EXCLUSIVE, /* ownership */
215 215 (struct psm_ops *)&apic_ops, /* operation */
216 216 APIC_PCPLUSMP_NAME, /* machine name */
217 217 "pcplusmp v1.4 compatible",
218 218 };
219 219
220 220 static void *apic_hdlp;
221 221
222 222 /*
223 223 * apic_let_idle_redistribute can have the following values:
224 224 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute.
225 225 * apic_redistribute_lock prevents multiple idle cpus from redistributing
226 226 */
227 227 int apic_num_idle_redistributions = 0;
228 228 static int apic_let_idle_redistribute = 0;
229 229
230 230 /* to gather intr data and redistribute */
231 231 static void apic_redistribute_compute(void);
232 232
233 233 /*
234 234 * This is the loadable module wrapper
235 235 */
236 236
237 237 int
238 238 _init(void)
239 239 {
240 240 if (apic_coarse_hrtime)
241 241 apic_ops.psm_gethrtime = &apic_gettime;
242 242 return (psm_mod_init(&apic_hdlp, &apic_psm_info));
243 243 }
244 244
245 245 int
246 246 _fini(void)
247 247 {
248 248 return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
249 249 }
250 250
251 251 int
252 252 _info(struct modinfo *modinfop)
253 253 {
254 254 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
255 255 }
256 256
257 257 static int
258 258 apic_probe(void)
259 259 {
260 260 /* check if apix is initialized */
261 261 if (apix_enable && apix_loaded())
262 262 return (PSM_FAILURE);
263 263 else
264 264 apix_enable = 0; /* continue using pcplusmp PSM */
265 265
266 266 return (apic_probe_common(apic_psm_info.p_mach_idstring));
267 267 }
268 268
269 269 static uchar_t
270 270 apic_xlate_vector_by_irq(uchar_t irq)
271 271 {
272 272 if (apic_irq_table[irq] == NULL)
273 273 return (0);
274 274
275 275 return (apic_irq_table[irq]->airq_vector);
276 276 }
277 277
278 278 void
279 279 apic_init(void)
280 280 {
281 281 int i;
282 282 int j = 1;
283 283
284 284 psm_get_ioapicid = apic_get_ioapicid;
285 285 psm_get_localapicid = apic_get_localapicid;
286 286 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
287 287
288 288 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
289 289 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
290 290 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
291 291 (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
292 292 /* get to highest vector at the same ipl */
293 293 continue;
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294 294 for (; j <= apic_vectortoipl[i]; j++) {
295 295 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
296 296 APIC_BASE_VECT;
297 297 }
298 298 }
299 299 for (; j < MAXIPL + 1; j++)
300 300 /* fill up any empty ipltopri slots */
301 301 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
302 302 apic_init_common();
303 303 #if defined(__amd64)
304 - /*
305 - * Make cpu-specific interrupt info point to cr8pri vector
306 - */
307 - for (i = 0; i <= MAXIPL; i++)
308 - apic_cr8pri[i] = apic_ipltopri[i] >> APIC_IPL_SHIFT;
309 - CPU->cpu_pri_data = apic_cr8pri;
304 + CPU->cpu_pri_data = dummy_cpu_pri;
310 305 #else
311 306 if (cpuid_have_cr8access(CPU))
312 307 apic_have_32bit_cr8 = 1;
313 308 #endif /* __amd64 */
314 309 }
315 310
316 311 static void
317 312 apic_init_intr(void)
318 313 {
319 314 processorid_t cpun = psm_get_cpu_id();
320 315 uint_t nlvt;
321 316 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
322 317
323 318 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
324 319
325 320 if (apic_mode == LOCAL_APIC) {
326 321 /*
327 322 * We are running APIC in MMIO mode.
328 323 */
329 324 if (apic_flat_model) {
330 325 apic_reg_ops->apic_write(APIC_FORMAT_REG,
331 326 APIC_FLAT_MODEL);
332 327 } else {
333 328 apic_reg_ops->apic_write(APIC_FORMAT_REG,
334 329 APIC_CLUSTER_MODEL);
335 330 }
336 331
337 332 apic_reg_ops->apic_write(APIC_DEST_REG,
338 333 AV_HIGH_ORDER >> cpun);
339 334 }
340 335
341 336 if (apic_directed_EOI_supported()) {
342 337 /*
343 338 * Setting the 12th bit in the Spurious Interrupt Vector
344 339 * Register suppresses broadcast EOIs generated by the local
345 340 * APIC. The suppression of broadcast EOIs happens only when
346 341 * interrupts are level-triggered.
347 342 */
348 343 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
349 344 }
350 345
351 346 /* need to enable APIC before unmasking NMI */
352 347 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
353 348
354 349 /*
355 350 * Presence of an invalid vector with delivery mode AV_FIXED can
356 351 * cause an error interrupt, even if the entry is masked...so
357 352 * write a valid vector to LVT entries along with the mask bit
358 353 */
359 354
360 355 /* All APICs have timer and LINT0/1 */
361 356 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
362 357 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
363 358 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
364 359
365 360 /*
366 361 * On integrated APICs, the number of LVT entries is
367 362 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
368 363 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
369 364 */
370 365
371 366 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
372 367 nlvt = 3;
373 368 } else {
374 369 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
375 370 0xFF) + 1;
376 371 }
377 372
378 373 if (nlvt >= 5) {
379 374 /* Enable performance counter overflow interrupt */
380 375
381 376 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
382 377 apic_enable_cpcovf_intr = 0;
383 378 if (apic_enable_cpcovf_intr) {
384 379 if (apic_cpcovf_vect == 0) {
385 380 int ipl = APIC_PCINT_IPL;
386 381 int irq = apic_get_ipivect(ipl, -1);
387 382
388 383 ASSERT(irq != -1);
389 384 apic_cpcovf_vect =
390 385 apic_irq_table[irq]->airq_vector;
391 386 ASSERT(apic_cpcovf_vect);
392 387 (void) add_avintr(NULL, ipl,
393 388 (avfunc)kcpc_hw_overflow_intr,
394 389 "apic pcint", irq, NULL, NULL, NULL, NULL);
395 390 kcpc_hw_overflow_intr_installed = 1;
396 391 kcpc_hw_enable_cpc_intr =
397 392 apic_cpcovf_mask_clear;
398 393 }
399 394 apic_reg_ops->apic_write(APIC_PCINT_VECT,
400 395 apic_cpcovf_vect);
401 396 }
402 397 }
403 398
404 399 if (nlvt >= 6) {
405 400 /* Only mask TM intr if the BIOS apparently doesn't use it */
406 401
407 402 uint32_t lvtval;
408 403
409 404 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
410 405 if (((lvtval & AV_MASK) == AV_MASK) ||
411 406 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
412 407 apic_reg_ops->apic_write(APIC_THERM_VECT,
413 408 AV_MASK|APIC_RESV_IRQ);
414 409 }
415 410 }
416 411
417 412 /* Enable error interrupt */
418 413
419 414 if (nlvt >= 4 && apic_enable_error_intr) {
420 415 if (apic_errvect == 0) {
421 416 int ipl = 0xf; /* get highest priority intr */
422 417 int irq = apic_get_ipivect(ipl, -1);
423 418
424 419 ASSERT(irq != -1);
425 420 apic_errvect = apic_irq_table[irq]->airq_vector;
426 421 ASSERT(apic_errvect);
427 422 /*
428 423 * Not PSMI compliant, but we are going to merge
429 424 * with ON anyway
430 425 */
431 426 (void) add_avintr((void *)NULL, ipl,
432 427 (avfunc)apic_error_intr, "apic error intr",
433 428 irq, NULL, NULL, NULL, NULL);
434 429 }
435 430 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
436 431 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
437 432 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
438 433 }
439 434
440 435 /* Enable CMCI interrupt */
441 436 if (cmi_enable_cmci) {
442 437
443 438 mutex_enter(&cmci_cpu_setup_lock);
444 439 if (cmci_cpu_setup_registered == 0) {
445 440 mutex_enter(&cpu_lock);
446 441 register_cpu_setup_func(cmci_cpu_setup, NULL);
447 442 mutex_exit(&cpu_lock);
448 443 cmci_cpu_setup_registered = 1;
449 444 }
450 445 mutex_exit(&cmci_cpu_setup_lock);
451 446
452 447 if (apic_cmci_vect == 0) {
453 448 int ipl = 0x2;
454 449 int irq = apic_get_ipivect(ipl, -1);
455 450
456 451 ASSERT(irq != -1);
457 452 apic_cmci_vect = apic_irq_table[irq]->airq_vector;
458 453 ASSERT(apic_cmci_vect);
459 454
460 455 (void) add_avintr(NULL, ipl,
461 456 (avfunc)cmi_cmci_trap,
462 457 "apic cmci intr", irq, NULL, NULL, NULL, NULL);
463 458 }
464 459 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect);
465 460 }
466 461 }
467 462
468 463 static void
469 464 apic_picinit(void)
470 465 {
471 466 int i, j;
472 467 uint_t isr;
473 468
474 469 /*
475 470 * Initialize and enable interrupt remapping before apic
476 471 * hardware initialization
477 472 */
478 473 apic_intrmap_init(apic_mode);
479 474
480 475 /*
481 476 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
482 477 * bit on without clearing it with EOI. Since softint
483 478 * uses vector 0x20 to interrupt itself, so softint will
484 479 * not work on this machine. In order to fix this problem
485 480 * a check is made to verify all the isr bits are clear.
486 481 * If not, EOIs are issued to clear the bits.
487 482 */
488 483 for (i = 7; i >= 1; i--) {
489 484 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
490 485 if (isr != 0)
491 486 for (j = 0; ((j < 32) && (isr != 0)); j++)
492 487 if (isr & (1 << j)) {
493 488 apic_reg_ops->apic_write(
494 489 APIC_EOI_REG, 0);
495 490 isr &= ~(1 << j);
496 491 apic_error |= APIC_ERR_BOOT_EOI;
497 492 }
498 493 }
499 494
500 495 /* set a flag so we know we have run apic_picinit() */
501 496 apic_picinit_called = 1;
502 497 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
503 498 LOCK_INIT_CLEAR(&apic_ioapic_lock);
504 499 LOCK_INIT_CLEAR(&apic_error_lock);
505 500 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
506 501
507 502 picsetup(); /* initialise the 8259 */
508 503
509 504 /* add nmi handler - least priority nmi handler */
510 505 LOCK_INIT_CLEAR(&apic_nmi_lock);
511 506
512 507 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
513 508 "pcplusmp NMI handler", (caddr_t)NULL))
514 509 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
515 510
516 511 /*
517 512 * Check for directed-EOI capability in the local APIC.
518 513 */
519 514 if (apic_directed_EOI_supported() == 1) {
520 515 apic_set_directed_EOI_handler();
521 516 }
522 517
523 518 apic_init_intr();
524 519
525 520 /* enable apic mode if imcr present */
526 521 if (apic_imcrp) {
527 522 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
528 523 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
529 524 }
530 525
531 526 ioapic_init_intr(IOAPIC_MASK);
532 527 }
533 528
534 529 #ifdef DEBUG
535 530 void
536 531 apic_break(void)
537 532 {
538 533 }
539 534 #endif /* DEBUG */
540 535
541 536 /*
542 537 * platform_intr_enter
543 538 *
544 539 * Called at the beginning of the interrupt service routine to
545 540 * mask all level equal to and below the interrupt priority
546 541 * of the interrupting vector. An EOI should be given to
547 542 * the interrupt controller to enable other HW interrupts.
548 543 *
549 544 * Return -1 for spurious interrupts
550 545 *
551 546 */
552 547 /*ARGSUSED*/
553 548 static int
554 549 apic_intr_enter(int ipl, int *vectorp)
555 550 {
556 551 uchar_t vector;
557 552 int nipl;
558 553 int irq;
559 554 ulong_t iflag;
560 555 apic_cpus_info_t *cpu_infop;
561 556
562 557 /*
563 558 * The real vector delivered is (*vectorp + 0x20), but our caller
564 559 * subtracts 0x20 from the vector before passing it to us.
565 560 * (That's why APIC_BASE_VECT is 0x20.)
566 561 */
567 562 vector = (uchar_t)*vectorp;
568 563
569 564 /* if interrupted by the clock, increment apic_nsec_since_boot */
570 565 if (vector == apic_clkvect) {
571 566 if (!apic_oneshot) {
572 567 /* NOTE: this is not MT aware */
573 568 apic_hrtime_stamp++;
574 569 apic_nsec_since_boot += apic_nsec_per_intr;
575 570 apic_hrtime_stamp++;
576 571 last_count_read = apic_hertz_count;
577 572 apic_redistribute_compute();
578 573 }
579 574
580 575 /* We will avoid all the book keeping overhead for clock */
581 576 nipl = apic_ipls[vector];
582 577
583 578 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
584 579 if (apic_mode == LOCAL_APIC) {
585 580 #if defined(__amd64)
586 581 setcr8((ulong_t)(apic_ipltopri[nipl] >>
587 582 APIC_IPL_SHIFT));
588 583 #else
589 584 if (apic_have_32bit_cr8)
590 585 setcr8((ulong_t)(apic_ipltopri[nipl] >>
591 586 APIC_IPL_SHIFT));
592 587 else
593 588 LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
594 589 (uint32_t)apic_ipltopri[nipl]);
595 590 #endif
596 591 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
597 592 } else {
598 593 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
599 594 X2APIC_WRITE(APIC_EOI_REG, 0);
600 595 }
601 596
602 597 return (nipl);
603 598 }
604 599
605 600 cpu_infop = &apic_cpus[psm_get_cpu_id()];
606 601
607 602 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
608 603 cpu_infop->aci_spur_cnt++;
609 604 return (APIC_INT_SPURIOUS);
610 605 }
611 606
612 607 /* Check if the vector we got is really what we need */
613 608 if (apic_revector_pending) {
614 609 /*
615 610 * Disable interrupts for the duration of
616 611 * the vector translation to prevent a self-race for
617 612 * the apic_revector_lock. This cannot be done
618 613 * in apic_xlate_vector because it is recursive and
619 614 * we want the vector translation to be atomic with
620 615 * respect to other (higher-priority) interrupts.
621 616 */
622 617 iflag = intr_clear();
623 618 vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
624 619 APIC_BASE_VECT;
625 620 intr_restore(iflag);
626 621 }
627 622
628 623 nipl = apic_ipls[vector];
629 624 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
630 625
631 626 if (apic_mode == LOCAL_APIC) {
632 627 #if defined(__amd64)
633 628 setcr8((ulong_t)(apic_ipltopri[nipl] >> APIC_IPL_SHIFT));
634 629 #else
635 630 if (apic_have_32bit_cr8)
636 631 setcr8((ulong_t)(apic_ipltopri[nipl] >>
637 632 APIC_IPL_SHIFT));
638 633 else
639 634 LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
640 635 (uint32_t)apic_ipltopri[nipl]);
641 636 #endif
642 637 } else {
643 638 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
644 639 }
645 640
646 641 cpu_infop->aci_current[nipl] = (uchar_t)irq;
647 642 cpu_infop->aci_curipl = (uchar_t)nipl;
648 643 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
649 644
650 645 /*
651 646 * apic_level_intr could have been assimilated into the irq struct.
652 647 * but, having it as a character array is more efficient in terms of
653 648 * cache usage. So, we leave it as is.
654 649 */
655 650 if (!apic_level_intr[irq]) {
656 651 if (apic_mode == LOCAL_APIC) {
657 652 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
658 653 } else {
659 654 X2APIC_WRITE(APIC_EOI_REG, 0);
660 655 }
661 656 }
662 657
663 658 #ifdef DEBUG
664 659 APIC_DEBUG_BUF_PUT(vector);
665 660 APIC_DEBUG_BUF_PUT(irq);
666 661 APIC_DEBUG_BUF_PUT(nipl);
667 662 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
668 663 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
669 664 drv_usecwait(apic_stretch_interrupts);
670 665
671 666 if (apic_break_on_cpu == psm_get_cpu_id())
672 667 apic_break();
673 668 #endif /* DEBUG */
674 669 return (nipl);
675 670 }
676 671
677 672 /*
678 673 * This macro is a common code used by MMIO local apic and X2APIC
679 674 * local apic.
680 675 */
681 676 #define APIC_INTR_EXIT() \
682 677 { \
683 678 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \
684 679 if (apic_level_intr[irq]) \
685 680 apic_reg_ops->apic_send_eoi(irq); \
686 681 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \
687 682 /* ISR above current pri could not be in progress */ \
688 683 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \
689 684 }
690 685
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691 686 /*
692 687 * Any changes made to this function must also change X2APIC
693 688 * version of intr_exit.
694 689 */
695 690 void
696 691 apic_intr_exit(int prev_ipl, int irq)
697 692 {
698 693 apic_cpus_info_t *cpu_infop;
699 694
700 695 #if defined(__amd64)
701 - setcr8((ulong_t)apic_cr8pri[prev_ipl]);
696 + setcr8((ulong_t)(apic_ipltopri[prev_ipl] >> APIC_IPL_SHIFT));
702 697 #else
703 698 if (apic_have_32bit_cr8)
704 699 setcr8((ulong_t)(apic_ipltopri[prev_ipl] >> APIC_IPL_SHIFT));
705 700 else
706 701 apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl];
707 702 #endif
708 703
709 704 APIC_INTR_EXIT();
710 705 }
711 706
712 707 /*
713 708 * Same as apic_intr_exit() except it uses MSR rather than MMIO
714 709 * to access local apic registers.
715 710 */
716 711 void
717 712 x2apic_intr_exit(int prev_ipl, int irq)
718 713 {
719 714 apic_cpus_info_t *cpu_infop;
720 715
721 716 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]);
722 717 APIC_INTR_EXIT();
723 718 }
724 719
725 720 intr_exit_fn_t
726 721 psm_intr_exit_fn(void)
727 722 {
728 723 if (apic_mode == LOCAL_X2APIC)
729 724 return (x2apic_intr_exit);
730 725
731 726 return (apic_intr_exit);
732 727 }
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733 728
734 729 /*
735 730 * Mask all interrupts below or equal to the given IPL.
736 731 * Any changes made to this function must also change X2APIC
737 732 * version of setspl.
738 733 */
739 734 static void
740 735 apic_setspl(int ipl)
741 736 {
742 737 #if defined(__amd64)
743 - setcr8((ulong_t)apic_cr8pri[ipl]);
738 + setcr8((ulong_t)(apic_ipltopri[ipl] >> APIC_IPL_SHIFT));
744 739 #else
745 740 if (apic_have_32bit_cr8)
746 741 setcr8((ulong_t)(apic_ipltopri[ipl] >> APIC_IPL_SHIFT));
747 742 else
748 743 apicadr[APIC_TASK_REG] = apic_ipltopri[ipl];
749 744 #endif
750 745
751 746 /* interrupts at ipl above this cannot be in progress */
752 747 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
753 748 /*
754 749 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
755 750 * have enough time to come in before the priority is raised again
756 751 * during the idle() loop.
757 752 */
758 753 if (apic_setspl_delay)
759 754 (void) apic_reg_ops->apic_get_pri();
760 755 }
761 756
762 757 /*
763 758 * X2APIC version of setspl.
764 759 * Mask all interrupts below or equal to the given IPL
765 760 */
766 761 static void
767 762 x2apic_setspl(int ipl)
768 763 {
769 764 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]);
770 765
771 766 /* interrupts at ipl above this cannot be in progress */
772 767 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
773 768 }
774 769
775 770 /*ARGSUSED*/
776 771 static int
777 772 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
778 773 {
779 774 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
780 775 }
781 776
782 777 static int
783 778 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
784 779 {
785 780 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
786 781 }
787 782
788 783 static int
789 784 apic_post_cpu_start(void)
790 785 {
791 786 int cpun;
792 787 static int cpus_started = 1;
793 788
794 789 /* We know this CPU + BSP started successfully. */
795 790 cpus_started++;
796 791
797 792 /*
798 793 * On BSP we would have enabled X2APIC, if supported by processor,
799 794 * in acpi_probe(), but on AP we do it here.
800 795 *
801 796 * We enable X2APIC mode only if BSP is running in X2APIC & the
802 797 * local APIC mode of the current CPU is MMIO (xAPIC).
803 798 */
804 799 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
805 800 apic_local_mode() == LOCAL_APIC) {
806 801 apic_enable_x2apic();
807 802 }
808 803
809 804 /*
810 805 * Switch back to x2apic IPI sending method for performance when target
811 806 * CPU has entered x2apic mode.
812 807 */
813 808 if (apic_mode == LOCAL_X2APIC) {
814 809 apic_switch_ipi_callback(B_FALSE);
815 810 }
816 811
817 812 splx(ipltospl(LOCK_LEVEL));
818 813 apic_init_intr();
819 814
820 815 /*
821 816 * since some systems don't enable the internal cache on the non-boot
822 817 * cpus, so we have to enable them here
823 818 */
824 819 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
825 820
826 821 #ifdef DEBUG
827 822 APIC_AV_PENDING_SET();
828 823 #else
829 824 if (apic_mode == LOCAL_APIC)
830 825 APIC_AV_PENDING_SET();
831 826 #endif /* DEBUG */
832 827
833 828 /*
834 829 * We may be booting, or resuming from suspend; aci_status will
835 830 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
836 831 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
837 832 */
838 833 cpun = psm_get_cpu_id();
839 834 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
840 835
841 836 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
842 837 return (PSM_SUCCESS);
843 838 }
844 839
845 840 /*
846 841 * type == -1 indicates it is an internal request. Do not change
847 842 * resv_vector for these requests
848 843 */
849 844 static int
850 845 apic_get_ipivect(int ipl, int type)
851 846 {
852 847 uchar_t vector;
853 848 int irq;
854 849
855 850 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
856 851 if (vector = apic_allocate_vector(ipl, irq, 1)) {
857 852 apic_irq_table[irq]->airq_mps_intr_index =
858 853 RESERVE_INDEX;
859 854 apic_irq_table[irq]->airq_vector = vector;
860 855 if (type != -1) {
861 856 apic_resv_vector[ipl] = vector;
862 857 }
863 858 return (irq);
864 859 }
865 860 }
866 861 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
867 862 return (-1); /* shouldn't happen */
868 863 }
869 864
870 865 static int
871 866 apic_getclkirq(int ipl)
872 867 {
873 868 int irq;
874 869
875 870 if ((irq = apic_get_ipivect(ipl, -1)) == -1)
876 871 return (-1);
877 872 /*
878 873 * Note the vector in apic_clkvect for per clock handling.
879 874 */
880 875 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
881 876 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
882 877 apic_clkvect));
883 878 return (irq);
884 879 }
885 880
886 881 /*
887 882 * Try and disable all interrupts. We just assign interrupts to other
888 883 * processors based on policy. If any were bound by user request, we
889 884 * let them continue and return failure. We do not bother to check
890 885 * for cache affinity while rebinding.
891 886 */
892 887
893 888 static int
894 889 apic_disable_intr(processorid_t cpun)
895 890 {
896 891 int bind_cpu = 0, i, hardbound = 0;
897 892 apic_irq_t *irq_ptr;
898 893 ulong_t iflag;
899 894
900 895 iflag = intr_clear();
901 896 lock_set(&apic_ioapic_lock);
902 897
903 898 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
904 899 if (apic_reprogram_info[i].done == B_FALSE) {
905 900 if (apic_reprogram_info[i].bindcpu == cpun) {
906 901 /*
907 902 * CPU is busy -- it's the target of
908 903 * a pending reprogramming attempt
909 904 */
910 905 lock_clear(&apic_ioapic_lock);
911 906 intr_restore(iflag);
912 907 return (PSM_FAILURE);
913 908 }
914 909 }
915 910 }
916 911
917 912 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
918 913
919 914 apic_cpus[cpun].aci_curipl = 0;
920 915
921 916 i = apic_min_device_irq;
922 917 for (; i <= apic_max_device_irq; i++) {
923 918 /*
924 919 * If there are bound interrupts on this cpu, then
925 920 * rebind them to other processors.
926 921 */
927 922 if ((irq_ptr = apic_irq_table[i]) != NULL) {
928 923 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
929 924 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
930 925 (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
931 926
932 927 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
933 928 hardbound = 1;
934 929 continue;
935 930 }
936 931
937 932 if (irq_ptr->airq_temp_cpu == cpun) {
938 933 do {
939 934 bind_cpu =
940 935 apic_find_cpu(APIC_CPU_INTR_ENABLE);
941 936 } while (apic_rebind_all(irq_ptr, bind_cpu));
942 937 }
943 938 }
944 939 }
945 940
946 941 lock_clear(&apic_ioapic_lock);
947 942 intr_restore(iflag);
948 943
949 944 if (hardbound) {
950 945 cmn_err(CE_WARN, "Could not disable interrupts on %d"
951 946 "due to user bound interrupts", cpun);
952 947 return (PSM_FAILURE);
953 948 }
954 949 else
955 950 return (PSM_SUCCESS);
956 951 }
957 952
958 953 /*
959 954 * Bind interrupts to the CPU's local APIC.
960 955 * Interrupts should not be bound to a CPU's local APIC until the CPU
961 956 * is ready to receive interrupts.
962 957 */
963 958 static void
964 959 apic_enable_intr(processorid_t cpun)
965 960 {
966 961 int i;
967 962 apic_irq_t *irq_ptr;
968 963 ulong_t iflag;
969 964
970 965 iflag = intr_clear();
971 966 lock_set(&apic_ioapic_lock);
972 967
973 968 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
974 969
975 970 i = apic_min_device_irq;
976 971 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
977 972 if ((irq_ptr = apic_irq_table[i]) != NULL) {
978 973 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
979 974 (void) apic_rebind_all(irq_ptr,
980 975 irq_ptr->airq_cpu);
981 976 }
982 977 }
983 978 }
984 979
985 980 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
986 981 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
987 982
988 983 lock_clear(&apic_ioapic_lock);
989 984 intr_restore(iflag);
990 985 }
991 986
992 987 /*
993 988 * If this module needs a periodic handler for the interrupt distribution, it
994 989 * can be added here. The argument to the periodic handler is not currently
995 990 * used, but is reserved for future.
996 991 */
997 992 static void
998 993 apic_post_cyclic_setup(void *arg)
999 994 {
1000 995 _NOTE(ARGUNUSED(arg))
1001 996
1002 997 cyc_handler_t cyh;
1003 998 cyc_time_t cyt;
1004 999
1005 1000 /* cpu_lock is held */
1006 1001 /* set up a periodic handler for intr redistribution */
1007 1002
1008 1003 /*
1009 1004 * In peridoc mode intr redistribution processing is done in
1010 1005 * apic_intr_enter during clk intr processing
1011 1006 */
1012 1007 if (!apic_oneshot)
1013 1008 return;
1014 1009
1015 1010 /*
1016 1011 * Register a periodical handler for the redistribution processing.
1017 1012 * Though we would generally prefer to use the DDI interface for
1018 1013 * periodic handler invocation, ddi_periodic_add(9F), we are
1019 1014 * unfortunately already holding cpu_lock, which ddi_periodic_add will
1020 1015 * attempt to take for us. Thus, we add our own cyclic directly:
1021 1016 */
1022 1017 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
1023 1018 cyh.cyh_arg = NULL;
1024 1019 cyh.cyh_level = CY_LOW_LEVEL;
1025 1020
1026 1021 cyt.cyt_when = 0;
1027 1022 cyt.cyt_interval = apic_redistribute_sample_interval;
1028 1023
1029 1024 apic_cyclic_id = cyclic_add(&cyh, &cyt);
1030 1025 }
1031 1026
1032 1027 static void
1033 1028 apic_redistribute_compute(void)
1034 1029 {
1035 1030 int i, j, max_busy;
1036 1031
1037 1032 if (apic_enable_dynamic_migration) {
1038 1033 if (++apic_nticks == apic_sample_factor_redistribution) {
1039 1034 /*
1040 1035 * Time to call apic_intr_redistribute().
1041 1036 * reset apic_nticks. This will cause max_busy
1042 1037 * to be calculated below and if it is more than
1043 1038 * apic_int_busy, we will do the whole thing
1044 1039 */
1045 1040 apic_nticks = 0;
1046 1041 }
1047 1042 max_busy = 0;
1048 1043 for (i = 0; i < apic_nproc; i++) {
1049 1044 if (!apic_cpu_in_range(i))
1050 1045 continue;
1051 1046
1052 1047 /*
1053 1048 * Check if curipl is non zero & if ISR is in
1054 1049 * progress
1055 1050 */
1056 1051 if (((j = apic_cpus[i].aci_curipl) != 0) &&
1057 1052 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1058 1053
1059 1054 int irq;
1060 1055 apic_cpus[i].aci_busy++;
1061 1056 irq = apic_cpus[i].aci_current[j];
1062 1057 apic_irq_table[irq]->airq_busy++;
1063 1058 }
1064 1059
1065 1060 if (!apic_nticks &&
1066 1061 (apic_cpus[i].aci_busy > max_busy))
1067 1062 max_busy = apic_cpus[i].aci_busy;
1068 1063 }
1069 1064 if (!apic_nticks) {
1070 1065 if (max_busy > apic_int_busy_mark) {
1071 1066 /*
1072 1067 * We could make the following check be
1073 1068 * skipped > 1 in which case, we get a
1074 1069 * redistribution at half the busy mark (due to
1075 1070 * double interval). Need to be able to collect
1076 1071 * more empirical data to decide if that is a
1077 1072 * good strategy. Punt for now.
1078 1073 */
1079 1074 if (apic_skipped_redistribute) {
1080 1075 apic_cleanup_busy();
1081 1076 apic_skipped_redistribute = 0;
1082 1077 } else {
1083 1078 apic_intr_redistribute();
1084 1079 }
1085 1080 } else
1086 1081 apic_skipped_redistribute++;
1087 1082 }
1088 1083 }
1089 1084 }
1090 1085
1091 1086
1092 1087 /*
1093 1088 * The following functions are in the platform specific file so that they
1094 1089 * can be different functions depending on whether we are running on
1095 1090 * bare metal or a hypervisor.
1096 1091 */
1097 1092
1098 1093 /*
1099 1094 * Check to make sure there are enough irq slots
1100 1095 */
1101 1096 int
1102 1097 apic_check_free_irqs(int count)
1103 1098 {
1104 1099 int i, avail;
1105 1100
1106 1101 avail = 0;
1107 1102 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1108 1103 if ((apic_irq_table[i] == NULL) ||
1109 1104 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
1110 1105 if (++avail >= count)
1111 1106 return (PSM_SUCCESS);
1112 1107 }
1113 1108 }
1114 1109 return (PSM_FAILURE);
1115 1110 }
1116 1111
1117 1112 /*
1118 1113 * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
1119 1114 */
1120 1115 int
1121 1116 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
1122 1117 int behavior)
1123 1118 {
1124 1119 int rcount, i;
1125 1120 uchar_t start, irqno;
1126 1121 uint32_t cpu;
1127 1122 major_t major;
1128 1123 apic_irq_t *irqptr;
1129 1124
1130 1125 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
1131 1126 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1132 1127 (void *)dip, inum, pri, count, behavior));
1133 1128
1134 1129 if (count > 1) {
1135 1130 if (behavior == DDI_INTR_ALLOC_STRICT &&
1136 1131 apic_multi_msi_enable == 0)
1137 1132 return (0);
1138 1133 if (apic_multi_msi_enable == 0)
1139 1134 count = 1;
1140 1135 }
1141 1136
1142 1137 if ((rcount = apic_navail_vector(dip, pri)) > count)
1143 1138 rcount = count;
1144 1139 else if (rcount == 0 || (rcount < count &&
1145 1140 behavior == DDI_INTR_ALLOC_STRICT))
1146 1141 return (0);
1147 1142
1148 1143 /* if not ISP2, then round it down */
1149 1144 if (!ISP2(rcount))
1150 1145 rcount = 1 << (highbit(rcount) - 1);
1151 1146
1152 1147 mutex_enter(&airq_mutex);
1153 1148
1154 1149 for (start = 0; rcount > 0; rcount >>= 1) {
1155 1150 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1156 1151 behavior == DDI_INTR_ALLOC_STRICT)
1157 1152 break;
1158 1153 }
1159 1154
1160 1155 if (start == 0) {
1161 1156 /* no vector available */
1162 1157 mutex_exit(&airq_mutex);
1163 1158 return (0);
1164 1159 }
1165 1160
1166 1161 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1167 1162 /* not enough free irq slots available */
1168 1163 mutex_exit(&airq_mutex);
1169 1164 return (0);
1170 1165 }
1171 1166
1172 1167 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1173 1168 for (i = 0; i < rcount; i++) {
1174 1169 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1175 1170 (uchar_t)-1) {
1176 1171 /*
1177 1172 * shouldn't happen because of the
1178 1173 * apic_check_free_irqs() check earlier
1179 1174 */
1180 1175 mutex_exit(&airq_mutex);
1181 1176 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1182 1177 "apic_allocate_irq failed\n"));
1183 1178 return (i);
1184 1179 }
1185 1180 apic_max_device_irq = max(irqno, apic_max_device_irq);
1186 1181 apic_min_device_irq = min(irqno, apic_min_device_irq);
1187 1182 irqptr = apic_irq_table[irqno];
1188 1183 #ifdef DEBUG
1189 1184 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1190 1185 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1191 1186 "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1192 1187 #endif
1193 1188 apic_vector_to_irq[start + i] = (uchar_t)irqno;
1194 1189
1195 1190 irqptr->airq_vector = (uchar_t)(start + i);
1196 1191 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1197 1192 irqptr->airq_intin_no = (uchar_t)rcount;
1198 1193 irqptr->airq_ipl = pri;
1199 1194 irqptr->airq_vector = start + i;
1200 1195 irqptr->airq_origirq = (uchar_t)(inum + i);
1201 1196 irqptr->airq_share_id = 0;
1202 1197 irqptr->airq_mps_intr_index = MSI_INDEX;
1203 1198 irqptr->airq_dip = dip;
1204 1199 irqptr->airq_major = major;
1205 1200 if (i == 0) /* they all bound to the same cpu */
1206 1201 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
1207 1202 0xff, 0xff);
1208 1203 else
1209 1204 irqptr->airq_cpu = cpu;
1210 1205 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1211 1206 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1212 1207 (void *)irqptr->airq_dip, irqptr->airq_vector,
1213 1208 irqptr->airq_origirq, pri));
1214 1209 }
1215 1210 mutex_exit(&airq_mutex);
1216 1211 return (rcount);
1217 1212 }
1218 1213
1219 1214 /*
1220 1215 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1221 1216 */
1222 1217 int
1223 1218 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1224 1219 int behavior)
1225 1220 {
1226 1221 int rcount, i;
1227 1222 major_t major;
1228 1223
1229 1224 mutex_enter(&airq_mutex);
1230 1225
1231 1226 if ((rcount = apic_navail_vector(dip, pri)) > count)
1232 1227 rcount = count;
1233 1228 else if (rcount == 0 || (rcount < count &&
1234 1229 behavior == DDI_INTR_ALLOC_STRICT)) {
1235 1230 rcount = 0;
1236 1231 goto out;
1237 1232 }
1238 1233
1239 1234 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1240 1235 /* not enough free irq slots available */
1241 1236 rcount = 0;
1242 1237 goto out;
1243 1238 }
1244 1239
1245 1240 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1246 1241 for (i = 0; i < rcount; i++) {
1247 1242 uchar_t vector, irqno;
1248 1243 apic_irq_t *irqptr;
1249 1244
1250 1245 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1251 1246 (uchar_t)-1) {
1252 1247 /*
1253 1248 * shouldn't happen because of the
1254 1249 * apic_check_free_irqs() check earlier
1255 1250 */
1256 1251 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1257 1252 "apic_allocate_irq failed\n"));
1258 1253 rcount = i;
1259 1254 goto out;
1260 1255 }
1261 1256 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1262 1257 /*
1263 1258 * shouldn't happen because of the
1264 1259 * apic_navail_vector() call earlier
1265 1260 */
1266 1261 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1267 1262 "apic_allocate_vector failed\n"));
1268 1263 rcount = i;
1269 1264 goto out;
1270 1265 }
1271 1266 apic_max_device_irq = max(irqno, apic_max_device_irq);
1272 1267 apic_min_device_irq = min(irqno, apic_min_device_irq);
1273 1268 irqptr = apic_irq_table[irqno];
1274 1269 irqptr->airq_vector = (uchar_t)vector;
1275 1270 irqptr->airq_ipl = pri;
1276 1271 irqptr->airq_origirq = (uchar_t)(inum + i);
1277 1272 irqptr->airq_share_id = 0;
1278 1273 irqptr->airq_mps_intr_index = MSIX_INDEX;
1279 1274 irqptr->airq_dip = dip;
1280 1275 irqptr->airq_major = major;
1281 1276 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1282 1277 }
1283 1278 out:
1284 1279 mutex_exit(&airq_mutex);
1285 1280 return (rcount);
1286 1281 }
1287 1282
1288 1283 /*
1289 1284 * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1290 1285 * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1291 1286 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1292 1287 * requests and allocated only when pri is set.
1293 1288 */
1294 1289 uchar_t
1295 1290 apic_allocate_vector(int ipl, int irq, int pri)
1296 1291 {
1297 1292 int lowest, highest, i;
1298 1293
1299 1294 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1300 1295 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1301 1296
1302 1297 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1303 1298 lowest -= APIC_VECTOR_PER_IPL;
1304 1299
1305 1300 #ifdef DEBUG
1306 1301 if (apic_restrict_vector) /* for testing shared interrupt logic */
1307 1302 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1308 1303 #endif /* DEBUG */
1309 1304 if (pri == 0)
1310 1305 highest -= APIC_HI_PRI_VECTS;
1311 1306
1312 1307 for (i = lowest; i <= highest; i++) {
1313 1308 if (APIC_CHECK_RESERVE_VECTORS(i))
1314 1309 continue;
1315 1310 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1316 1311 apic_vector_to_irq[i] = (uchar_t)irq;
1317 1312 return (i);
1318 1313 }
1319 1314 }
1320 1315
1321 1316 return (0);
1322 1317 }
1323 1318
1324 1319 /* Mark vector as not being used by any irq */
1325 1320 void
1326 1321 apic_free_vector(uchar_t vector)
1327 1322 {
1328 1323 apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1329 1324 }
1330 1325
1331 1326 /*
1332 1327 * Call rebind to do the actual programming.
1333 1328 * Must be called with interrupts disabled and apic_ioapic_lock held
1334 1329 * 'p' is polymorphic -- if this function is called to process a deferred
1335 1330 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1336 1331 * the irq pointer is retrieved. If not doing deferred reprogramming,
1337 1332 * p is of the type 'apic_irq_t *'.
1338 1333 *
1339 1334 * apic_ioapic_lock must be held across this call, as it protects apic_rebind
1340 1335 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1341 1336 * taken offline after a cpu is selected, but before apic_rebind is called to
1342 1337 * bind interrupts to it.
1343 1338 */
1344 1339 int
1345 1340 apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1346 1341 {
1347 1342 apic_irq_t *irqptr;
1348 1343 struct ioapic_reprogram_data *drep = NULL;
1349 1344 int rv;
1350 1345
1351 1346 if (deferred) {
1352 1347 drep = (struct ioapic_reprogram_data *)p;
1353 1348 ASSERT(drep != NULL);
1354 1349 irqptr = drep->irqp;
1355 1350 } else
1356 1351 irqptr = (apic_irq_t *)p;
1357 1352
1358 1353 ASSERT(irqptr != NULL);
1359 1354
1360 1355 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1361 1356 if (rv) {
1362 1357 /*
1363 1358 * CPU is not up or interrupts are disabled. Fall back to
1364 1359 * the first available CPU
1365 1360 */
1366 1361 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1367 1362 drep);
1368 1363 }
1369 1364
1370 1365 return (rv);
1371 1366 }
1372 1367
1373 1368
1374 1369 uchar_t
1375 1370 apic_modify_vector(uchar_t vector, int irq)
1376 1371 {
1377 1372 apic_vector_to_irq[vector] = (uchar_t)irq;
1378 1373 return (vector);
1379 1374 }
1380 1375
1381 1376 char *
1382 1377 apic_get_apic_type(void)
1383 1378 {
1384 1379 return (apic_psm_info.p_mach_idstring);
1385 1380 }
1386 1381
1387 1382 void
1388 1383 x2apic_update_psm(void)
1389 1384 {
1390 1385 struct psm_ops *pops = &apic_ops;
1391 1386
1392 1387 ASSERT(pops != NULL);
1393 1388
1394 1389 pops->psm_intr_exit = x2apic_intr_exit;
1395 1390 pops->psm_setspl = x2apic_setspl;
1396 1391
1397 1392 pops->psm_send_ipi = x2apic_send_ipi;
1398 1393 send_dirintf = pops->psm_send_ipi;
1399 1394
1400 1395 apic_mode = LOCAL_X2APIC;
1401 1396 apic_change_ops();
1402 1397 }
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